From: Simon Horman <simon.horman@corigine.com>
To: Maxime Chevallier <maxime.chevallier@bootlin.com>
Cc: Mark Brown <broonie@kernel.org>,
davem@davemloft.net, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org, alexis.lothore@bootlin.com,
thomas.petazzoni@bootlin.com, Andrew Lunn <andrew@lunn.ch>,
Jakub Kicinski <kuba@kernel.org>,
Eric Dumazet <edumazet@google.com>,
Paolo Abeni <pabeni@redhat.com>,
Florian Fainelli <f.fainelli@gmail.com>,
Heiner Kallweit <hkallweit1@gmail.com>,
Russell King <linux@armlinux.org.uk>,
Vladimir Oltean <vladimir.oltean@nxp.com>,
Ioana Ciornei <ioana.ciornei@nxp.com>,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Jose Abreu <joabreu@synopsys.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Giuseppe Cavallaro <peppe.cavallaro@st.com>
Subject: Re: [PATCH net-next v2 1/4] net: mdio: Introduce a regmap-based mdio driver
Date: Thu, 25 May 2023 13:02:39 +0200 [thread overview]
Message-ID: <ZG9AT4EeCmoyN5N2@corigine.com> (raw)
In-Reply-To: <20230525101126.370108-2-maxime.chevallier@bootlin.com>
On Thu, May 25, 2023 at 12:11:23PM +0200, Maxime Chevallier wrote:
> There exists several examples today of devices that embed an ethernet
> PHY or PCS directly inside an SoC. In this situation, either the device
> is controlled through a vendor-specific register set, or sometimes
> exposes the standard 802.3 registers that are typically accessed over
> MDIO.
>
> As phylib and phylink are designed to use mdiodevices, this driver
> allows creating a virtual MDIO bus, that translates mdiodev register
> accesses to regmap accesses.
>
> The reason we use regmap is because there are at least 3 such devices
> known today, 2 of them are Altera TSE PCS's, memory-mapped, exposed
> with a 4-byte stride in stmmac's dwmac-socfpga variant, and a 2-byte
> stride in altera-tse. The other one (nxp,sja1110-base-tx-mdio) is
> exposed over SPI.
>
> Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
...
> +struct mii_bus *devm_mdio_regmap_register(struct device *dev,
> + const struct mdio_regmap_config *config)
> +{
> + struct mdio_regmap_config *mrc;
> + struct mii_bus *mii;
> + int rc;
> +
> + if (!config->parent)
> + return ERR_PTR(-EINVAL);
> +
> + mii = devm_mdiobus_alloc_size(config->parent, sizeof(*mrc));
> + if (!mii)
> + return ERR_PTR(-ENOMEM);
> +
> + mrc = mii->priv;
> + memcpy(mrc, config, sizeof(*mrc));
> +
> + mrc->regmap = config->regmap;
> + mrc->valid_addr = config->valid_addr;
> +
> + mii->name = DRV_NAME;
> + strscpy(mii->id, config->name, MII_BUS_ID_SIZE);
> + mii->parent = config->parent;
> + mii->read = mdio_regmap_read_c22;
> + mii->write = mdio_regmap_write_c22;
> +
> + if (config->autoscan)
> + mii->phy_mask = ~BIT(config->valid_addr);
> + else
> + mii->phy_mask = ~0UL;
Hi Maxime,
phy_mask is a u32.
But 0UL may be either 32 or 64 bits wide.
I think a better approach would be to use U32_MAX.
> +
> + rc = devm_mdiobus_register(dev, mii);
> + if (rc) {
> + dev_err(config->parent, "Cannot register MDIO bus![%s] (%d)\n", mii->id, rc);
> + return ERR_PTR(rc);
> + }
> +
> + return mii;
> +}
> +EXPORT_SYMBOL_GPL(devm_mdio_regmap_register);
> +
> +MODULE_DESCRIPTION("MDIO API over regmap");
> +MODULE_AUTHOR("Maxime Chevallier <maxime.chevallier@bootlin.com>");
> +MODULE_LICENSE("GPL");
next prev parent reply other threads:[~2023-05-25 11:02 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-25 10:11 [PATCH net-next v2 0/4] net: add a regmap-based mdio driver and drop TSE PCS Maxime Chevallier
2023-05-25 10:11 ` [PATCH net-next v2 1/4] net: mdio: Introduce a regmap-based mdio driver Maxime Chevallier
2023-05-25 11:02 ` Simon Horman [this message]
2023-05-25 12:43 ` Maxime Chevallier
2023-05-25 15:00 ` Simon Horman
2023-05-25 11:11 ` Russell King (Oracle)
2023-05-25 12:41 ` Maxime Chevallier
2023-05-25 10:11 ` [PATCH net-next v2 2/4] net: ethernet: altera-tse: Convert to mdio-regmap and use PCS Lynx Maxime Chevallier
2023-05-25 10:11 ` [PATCH net-next v2 3/4] net: pcs: Drop the TSE PCS driver Maxime Chevallier
2023-05-25 10:11 ` [PATCH net-next v2 4/4] net: stmmac: dwmac-sogfpga: use the lynx pcs driver Maxime Chevallier
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ZG9AT4EeCmoyN5N2@corigine.com \
--to=simon.horman@corigine.com \
--cc=alexandre.torgue@foss.st.com \
--cc=alexis.lothore@bootlin.com \
--cc=andrew@lunn.ch \
--cc=broonie@kernel.org \
--cc=davem@davemloft.net \
--cc=edumazet@google.com \
--cc=f.fainelli@gmail.com \
--cc=hkallweit1@gmail.com \
--cc=ioana.ciornei@nxp.com \
--cc=joabreu@synopsys.com \
--cc=kuba@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-stm32@st-md-mailman.stormreply.com \
--cc=linux@armlinux.org.uk \
--cc=maxime.chevallier@bootlin.com \
--cc=mcoquelin.stm32@gmail.com \
--cc=netdev@vger.kernel.org \
--cc=pabeni@redhat.com \
--cc=peppe.cavallaro@st.com \
--cc=thomas.petazzoni@bootlin.com \
--cc=vladimir.oltean@nxp.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).