From: andy.shevchenko@gmail.com
To: Jiawen Wu <jiawenwu@trustnetic.com>
Cc: netdev@vger.kernel.org, jarkko.nikula@linux.intel.com,
andriy.shevchenko@linux.intel.com,
mika.westerberg@linux.intel.com, jsd@semihalf.com,
Jose.Abreu@synopsys.com, andrew@lunn.ch, hkallweit1@gmail.com,
linux@armlinux.org.uk, linux-i2c@vger.kernel.org,
linux-gpio@vger.kernel.org, mengyuanlou@net-swift.com
Subject: Re: [PATCH net-next v8 6/9] net: txgbe: Support GPIO to SFP socket
Date: Mon, 15 May 2023 12:42:21 +0300 [thread overview]
Message-ID: <ZGH-fRzbGd_eCASk@surfacebook> (raw)
In-Reply-To: <20230515063200.301026-7-jiawenwu@trustnetic.com>
Mon, May 15, 2023 at 02:31:57PM +0800, Jiawen Wu kirjoitti:
> Register GPIO chip and handle GPIO IRQ for SFP socket.
...
> +static int txgbe_gpio_direction_out(struct gpio_chip *chip, unsigned int offset,
> + int val)
> +{
> + struct wx *wx = gpiochip_get_data(chip);
> + unsigned long flags;
> + u32 set;
> +
> + spin_lock_irqsave(&wx->gpio_lock, flags);
> + set = val ? BIT(offset) : 0;
Why is this under the lock?
> + wr32m(wx, WX_GPIO_DR, BIT(offset), set);
> + wr32m(wx, WX_GPIO_DDR, BIT(offset), BIT(offset));
> + spin_unlock_irqrestore(&wx->gpio_lock, flags);
> +
> + return 0;
> +}
...
> +static void txgbe_toggle_trigger(struct gpio_chip *gc, unsigned int offset)
> +{
> + struct wx *wx = gpiochip_get_data(gc);
> + u32 pol;
> + int val;
> +
> + pol = rd32(wx, WX_GPIO_POLARITY);
> + val = gc->get(gc, offset);
Can't you use directly the respective rd32()?
> + if (val)
> + pol &= ~BIT(offset);
> + else
> + pol |= BIT(offset);
> +
> + wr32(wx, WX_GPIO_POLARITY, pol);
> +}
...
> +static void txgbe_irq_handler(struct irq_desc *desc)
> +{
> + struct irq_chip *chip = irq_desc_get_chip(desc);
> + struct wx *wx = irq_desc_get_handler_data(desc);
> + struct txgbe *txgbe = wx->priv;
> + irq_hw_number_t hwirq;
> + unsigned long gpioirq;
> + struct gpio_chip *gc;
> +
> + chained_irq_enter(chip, desc);
Seems spin_lock() call is missing in this function.
> + gpioirq = rd32(wx, WX_GPIO_INTSTATUS);
> +
> + gc = txgbe->gpio;
> + for_each_set_bit(hwirq, &gpioirq, gc->ngpio) {
> + int gpio = irq_find_mapping(gc->irq.domain, hwirq);
> + u32 irq_type = irq_get_trigger_type(gpio);
> +
> + generic_handle_irq(gpio);
Can generic_handle_domain_irq() be used here?
> + if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
> + txgbe_toggle_trigger(gc, hwirq);
> + }
> +
> + chained_irq_exit(chip, desc);
> +
> + /* unmask interrupt */
> + wx_intr_enable(wx, TXGBE_INTR_MISC(wx));
> +}
...
> +static int txgbe_gpio_init(struct txgbe *txgbe)
> +{
> + struct gpio_irq_chip *girq;
> + struct wx *wx = txgbe->wx;
> + struct gpio_chip *gc;
> + struct device *dev;
> + int ret;
> + dev = &wx->pdev->dev;
This can be united with the defintion above.
struct device *dev = &wx->pdev->dev;
> + gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
> + if (!gc)
> + return -ENOMEM;
> +
> + gc->label = devm_kasprintf(dev, GFP_KERNEL, "txgbe_gpio-%x",
> + (wx->pdev->bus->number << 8) | wx->pdev->devfn);
> + gc->base = -1;
> + gc->ngpio = 6;
> + gc->owner = THIS_MODULE;
> + gc->parent = dev;
> + gc->fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_GPIO]);
Looking at the I²C case, I'm wondering if gpio-regmap can be used for this piece.
> + gc->get = txgbe_gpio_get;
> + gc->get_direction = txgbe_gpio_get_direction;
> + gc->direction_input = txgbe_gpio_direction_in;
> + gc->direction_output = txgbe_gpio_direction_out;
> +
> + girq = &gc->irq;
> + gpio_irq_chip_set_chip(girq, &txgbe_gpio_irq_chip);
> + girq->parent_handler = txgbe_irq_handler;
> + girq->parent_handler_data = wx;
> + girq->num_parents = 1;
> + girq->parents = devm_kcalloc(dev, girq->num_parents,
> + sizeof(*girq->parents), GFP_KERNEL);
> + if (!girq->parents)
> + return -ENOMEM;
> + girq->parents[0] = wx->msix_entries[wx->num_q_vectors].vector;
> + girq->default_type = IRQ_TYPE_NONE;
> + girq->handler = handle_bad_irq;
> +
> + ret = devm_gpiochip_add_data(dev, gc, wx);
> + if (ret)
> + return ret;
> + spin_lock_init(&wx->gpio_lock);
Isn't it too late?
> + txgbe->gpio = gc;
> +
> + return 0;
> +}
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2023-05-15 9:42 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-15 6:31 [PATCH net-next v8 0/9] TXGBE PHYLINK support Jiawen Wu
2023-05-15 6:31 ` [PATCH net-next v8 1/9] net: txgbe: Add software nodes to support phylink Jiawen Wu
2023-05-15 6:31 ` [PATCH net-next v8 2/9] i2c: designware: Add driver support for Wangxun 10Gb NIC Jiawen Wu
2023-05-15 9:24 ` andy.shevchenko
2023-05-17 8:49 ` Jarkko Nikula
2023-05-17 9:25 ` Jiawen Wu
2023-05-17 9:44 ` Andy Shevchenko
2023-05-19 13:26 ` Jarkko Nikula
2023-05-17 9:40 ` Andy Shevchenko
2023-05-15 6:31 ` [PATCH net-next v8 3/9] net: txgbe: Register fixed rate clock Jiawen Wu
2023-05-15 6:31 ` [PATCH net-next v8 4/9] net: txgbe: Register I2C platform device Jiawen Wu
2023-05-15 9:29 ` andy.shevchenko
2023-05-15 6:31 ` [PATCH net-next v8 5/9] net: txgbe: Add SFP module identify Jiawen Wu
2023-05-15 6:31 ` [PATCH net-next v8 6/9] net: txgbe: Support GPIO to SFP socket Jiawen Wu
2023-05-15 9:42 ` andy.shevchenko [this message]
2023-05-16 2:38 ` Jiawen Wu
2023-05-16 7:12 ` Andy Shevchenko
2023-05-16 9:39 ` Paolo Abeni
2023-05-16 10:31 ` Russell King (Oracle)
2023-05-17 2:55 ` Jiawen Wu
2023-05-17 10:26 ` Andy Shevchenko
2023-05-17 15:00 ` Andrew Lunn
2023-05-18 11:49 ` Jiawen Wu
2023-05-18 12:27 ` Andy Shevchenko
2023-05-18 16:02 ` Michael Walle
2023-05-18 16:07 ` Andy Shevchenko
2023-05-23 9:55 ` Jiawen Wu
2023-05-23 11:07 ` Andy Shevchenko
2023-05-23 11:10 ` Andy Shevchenko
2023-05-18 12:48 ` Andrew Lunn
2023-05-19 2:25 ` Jiawen Wu
2023-05-19 13:13 ` Andrew Lunn
2023-05-22 9:00 ` Jiawen Wu
2023-05-22 9:06 ` Jiawen Wu
2023-05-22 10:58 ` Jiawen Wu
2023-05-22 21:36 ` 'Andy Shevchenko'
2023-05-23 2:08 ` Jiawen Wu
2023-05-23 6:12 ` Jiawen Wu
2023-05-19 8:24 ` Jiawen Wu
2023-05-19 8:51 ` Jiawen Wu
2023-05-19 13:24 ` Andrew Lunn
2023-05-15 21:36 ` Andy Shevchenko
2023-05-16 2:05 ` Jiawen Wu
2023-05-17 10:29 ` 'Andy Shevchenko'
2023-05-15 6:31 ` [PATCH net-next v8 7/9] net: pcs: Add 10GBASE-R mode for Synopsys Designware XPCS Jiawen Wu
2023-05-15 6:31 ` [PATCH net-next v8 8/9] net: txgbe: Implement phylink pcs Jiawen Wu
2023-05-16 2:45 ` Lars-Peter Clausen
2023-05-15 6:32 ` [PATCH net-next v8 9/9] net: txgbe: Support phylink MAC layer Jiawen Wu
2023-05-16 9:43 ` Paolo Abeni
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