From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 913278833 for ; Fri, 11 Aug 2023 22:23:06 +0000 (UTC) Received: from pandora.armlinux.org.uk (unknown [IPv6:2001:4d48:ad52:32c8:5054:ff:fe00:142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B6B81703; Fri, 11 Aug 2023 15:22:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=armlinux.org.uk; s=pandora-2019; h=Sender:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=bPZ6eb6D+5nlXp0LzoMf2AoIFF7EdtsEvpEfZCHzjiI=; b=xfHVd0qaUbmZh3B9YRJYOI4nvw IJv4wL6ukw1CyguOkaUYiWVxDWYSQC/CgG1oRhMWnVwlc7gyFC87Z6KYYMDMTHhZpO20hyBUm7L19 zcmmEADFGqXGGUlZIjDbkcNFNQCeBLho7ClZc6pndLDYJevyi1Q+qtk1HKvvMfNpRTKM2mXQHU2xI Br5nZkc0X8l4kKm5Se1QF3fMUDjBOlt/Y47Jxar86NhBIA1aO5/zShjC/mHTCAOxpYbI6td43ZUgj nPQgHP5yDWUcgu1H1oUNhAT+OkXH8aNUfUt9QFYa3Pos3N6WxqvlAt5MgNyx+IjKnA+jq7jrfFXXT 51WU8/Pg==; Received: from shell.armlinux.org.uk ([fd8f:7570:feb6:1:5054:ff:fe00:4ec]:50692) by pandora.armlinux.org.uk with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1qUaWi-00063h-04; Fri, 11 Aug 2023 23:22:36 +0100 Received: from linux by shell.armlinux.org.uk with local (Exim 4.94.2) (envelope-from ) id 1qUaWg-0003El-8N; Fri, 11 Aug 2023 23:22:34 +0100 Date: Fri, 11 Aug 2023 23:22:34 +0100 From: "Russell King (Oracle)" To: Giulio Benetti Cc: Broadcom internal kernel review list , Andrew Lunn , Heiner Kallweit , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Florian Fainelli , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Reinhart , James Autry , Matthew Maron Subject: Re: [PATCH] net: phy: broadcom: add support for BCM5221 phy Message-ID: References: <20230811215322.8679-1-giulio.benetti@benettiengineering.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230811215322.8679-1-giulio.benetti@benettiengineering.com> Sender: Russell King (Oracle) X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED,RDNS_NONE, SPF_HELO_NONE,SPF_NONE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net On Fri, Aug 11, 2023 at 11:53:22PM +0200, Giulio Benetti wrote: > + reg = phy_read(phydev, MII_BRCM_FET_INTREG); > + if (reg < 0) > + return reg; > + > + /* Unmask events we are interested in and mask interrupts globally. */ > + reg = MII_BRCM_FET_IR_ENABLE | > + MII_BRCM_FET_IR_MASK; > + > + err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); > + if (err < 0) > + return err; Please explain why you read MII_BRCM_FET_INTREG, then discard its value and write a replacement value. > + > + /* Enable auto MDIX */ > + err = phy_clear_bits(phydev, BCM5221_AEGSR, BCM5221_AEGSR_MDIX_DIS); > + if (err < 0) > + return err; > + > + /* Enable shadow register access */ > + brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST); > + if (brcmtest < 0) > + return brcmtest; > + > + reg = brcmtest | MII_BRCM_FET_BT_SRE; > + > + err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); > + if (err < 0) > + return err; I think you should consider locking the MDIO bus while the device is switched to the shadow register set, so that other accesses don't happen that may interfere with this. > +static int bcm5221_suspend(struct phy_device *phydev) > +{ > + int reg, err, err2, brcmtest; > + > + /* Enable shadow register access */ > + brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST); > + if (brcmtest < 0) > + return brcmtest; > + > + reg = brcmtest | MII_BRCM_FET_BT_SRE; > + > + err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); > + if (err < 0) > + return err; > + > + /* Force Low Power Mode with clock enabled */ > + err = phy_set_bits(phydev, MII_BRCM_FET_SHDW_AUXMODE4, > + BCM5221_SHDW_AM4_EN_CLK_LPM | > + BCM5221_SHDW_AM4_FORCE_LPM); > + > + /* Disable shadow register access */ > + err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); > + if (!err) > + err = err2; Same here. > + > + return err; > +} > + > +static int bcm5221_resume(struct phy_device *phydev) > +{ > + int reg, err, err2, brcmtest; > + > + /* Enable shadow register access */ > + brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST); > + if (brcmtest < 0) > + return brcmtest; > + > + reg = brcmtest | MII_BRCM_FET_BT_SRE; > + > + err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); > + if (err < 0) > + return err; > + > + /* Exit Low Power Mode with clock enabled */ > + err = phy_clear_bits(phydev, MII_BRCM_FET_SHDW_AUXMODE4, > + BCM5221_SHDW_AM4_FORCE_LPM); > + > + /* Disable shadow register access */ > + err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest); > + if (!err) > + err = err2; And, of course, same here. Thanks. -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!