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From: Jiri Pirko <jiri@resnulli.us>
To: Jakub Kicinski <kuba@kernel.org>
Cc: Vadim Fedorenko <vadim.fedorenko@linux.dev>,
	Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
	Jonathan Lemon <jonathan.lemon@gmail.com>,
	Paolo Abeni <pabeni@redhat.com>,
	Milena Olech <milena.olech@intel.com>,
	Michal Michalik <michal.michalik@intel.com>,
	linux-arm-kernel@lists.infradead.org, poros@redhat.com,
	mschmidt@redhat.com, netdev@vger.kernel.org,
	linux-clk@vger.kernel.org, Bart Van Assche <bvanassche@acm.org>,
	intel-wired-lan@lists.osuosl.org, Jiri Pirko <jiri@nvidia.com>
Subject: Re: [PATCH net-next v4 3/9] dpll: core: Add DPLL framework base functions
Date: Tue, 15 Aug 2023 08:00:52 +0200	[thread overview]
Message-ID: <ZNsUlAk/XIcPsMY0@nanopsycho> (raw)
In-Reply-To: <20230814201709.655a24e2@kernel.org>

Tue, Aug 15, 2023 at 05:17:09AM CEST, kuba@kernel.org wrote:
>On Fri, 11 Aug 2023 21:03:34 +0100 Vadim Fedorenko wrote:

[...]


>> +int dpll_device_register(struct dpll_device *dpll, enum dpll_type type,
>> +			 const struct dpll_device_ops *ops, void *priv)
>> +{
>> +	struct dpll_device_registration *reg;
>> +	bool first_registration = false;
>> +
>> +	if (WARN_ON(!ops))
>> +		return -EINVAL;
>> +	if (WARN_ON(!ops->mode_get))
>> +		return -EINVAL;
>> +	if (WARN_ON(!ops->lock_status_get))
>> +		return -EINVAL;
>> +	if (WARN_ON(type < DPLL_TYPE_PPS || type > DPLL_TYPE_MAX))
>> +		return -EINVAL;
>> +
>> +	mutex_lock(&dpll_lock);
>> +	reg = dpll_device_registration_find(dpll, ops, priv);
>> +	if (reg) {
>> +		mutex_unlock(&dpll_lock);
>> +		return -EEXIST;
>> +	}
>> +
>> +	reg = kzalloc(sizeof(*reg), GFP_KERNEL);
>> +	if (!reg) {
>> +		mutex_unlock(&dpll_lock);
>> +		return -ENOMEM;
>> +	}
>> +	reg->ops = ops;
>> +	reg->priv = priv;
>> +	dpll->type = type;
>> +	first_registration = list_empty(&dpll->registration_list);
>> +	list_add_tail(&reg->list, &dpll->registration_list);
>> +	if (!first_registration) {
>> +		mutex_unlock(&dpll_lock);
>> +		return 0;
>> +	}
>> +
>> +	xa_set_mark(&dpll_device_xa, dpll->id, DPLL_REGISTERED);
>> +	mutex_unlock(&dpll_lock);
>> +
>> +	return 0;
>> +}
>> +EXPORT_SYMBOL_GPL(dpll_device_register);
>
>Is the registration flow documented? It's a bit atypical so we should
>write some pseudocode somewhere.

We have examples in 3 drivers with actual code. But sure, could use some
documentation.


>
>> +/**
>> + * dpll_device_unregister - unregister dpll device
>> + * @dpll: registered dpll pointer
>> + * @ops: ops for a dpll device
>> + * @priv: pointer to private information of owner
>> + *
>> + * Unregister device, make it unavailable for userspace.
>> + * Note: It does not free the memory
>> + * Context: Acquires a lock (dpll_lock)
>> + */
>> +void dpll_device_unregister(struct dpll_device *dpll,
>> +			    const struct dpll_device_ops *ops, void *priv)
>> +{
>> +	struct dpll_device_registration *reg;
>> +
>> +	mutex_lock(&dpll_lock);
>> +	ASSERT_DPLL_REGISTERED(dpll);
>> +	reg = dpll_device_registration_find(dpll, ops, priv);
>> +	if (WARN_ON(!reg)) {
>> +		mutex_unlock(&dpll_lock);
>> +		return;
>> +	}
>> +	list_del(&reg->list);
>> +	kfree(reg);
>> +
>> +	if (!list_empty(&dpll->registration_list)) {
>> +		mutex_unlock(&dpll_lock);
>> +		return;
>> +	}
>> +	xa_clear_mark(&dpll_device_xa, dpll->id, DPLL_REGISTERED);
>> +	mutex_unlock(&dpll_lock);
>> +}
>> +EXPORT_SYMBOL_GPL(dpll_device_unregister);
>
>> +/**
>> + * struct dpll_pin - structure for a dpll pin
>> + * @id:			unique id number for pin given by dpll subsystem
>> + * @pin_idx:		index of a pin given by dev driver
>> + * @clock_id:		clock_id of creator
>> + * @module:		module of creator
>> + * @dpll_refs:		hold referencees to dplls pin was registered with
>> + * @parent_refs:	hold references to parent pins pin was registered with
>> + * @prop:		pointer to pin properties given by registerer
>> + * @rclk_dev_name:	holds name of device when pin can recover clock from it
>> + * @refcount:		refcount
>> + **/
>> +struct dpll_pin {
>> +	u32 id;
>> +	u32 pin_idx;
>> +	u64 clock_id;
>> +	struct module *module;
>> +	struct xarray dpll_refs;
>> +	struct xarray parent_refs;
>> +	const struct dpll_pin_properties *prop;
>> +	char *rclk_dev_name;
>
>Where is rclk_dev_name filled in?

Leftover, should be removed.

[..]


  reply	other threads:[~2023-08-15  6:00 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-11 20:03 [PATCH net-next v4 0/9] Create common DPLL configuration API Vadim Fedorenko
2023-08-11 20:03 ` [PATCH net-next v4 1/9] dpll: documentation on DPLL subsystem interface Vadim Fedorenko
2023-08-15  2:52   ` Jakub Kicinski
2023-08-11 20:03 ` [PATCH net-next v4 2/9] dpll: spec: Add Netlink spec in YAML Vadim Fedorenko
2023-08-15  2:43   ` Jakub Kicinski
2023-08-17 18:40     ` Kubalewski, Arkadiusz
2023-08-17 23:36       ` Jakub Kicinski
2023-08-18  7:23         ` Jiri Pirko
2023-08-21 10:15           ` Kubalewski, Arkadiusz
2023-08-22 16:54             ` Jakub Kicinski
2023-08-11 20:03 ` [PATCH net-next v4 3/9] dpll: core: Add DPLL framework base functions Vadim Fedorenko
2023-08-15  3:17   ` Jakub Kicinski
2023-08-15  6:00     ` Jiri Pirko [this message]
2023-08-15 18:20     ` Vadim Fedorenko
2023-08-15 18:28       ` Jakub Kicinski
2023-08-15 18:38         ` Vadim Fedorenko
2023-08-11 20:03 ` [PATCH net-next v4 4/9] dpll: netlink: " Vadim Fedorenko
2023-08-15  3:23   ` Jakub Kicinski
2023-08-15  3:24   ` Jakub Kicinski
2023-08-15 15:18     ` Vadim Fedorenko
2023-08-15 16:55       ` Jakub Kicinski
2023-08-15 18:25         ` Vadim Fedorenko
2023-08-11 20:03 ` [PATCH net-next v4 5/9] netdev: expose DPLL pin handle for netdevice Vadim Fedorenko
2023-08-11 20:03 ` [PATCH net-next v4 6/9] ice: add admin commands to access cgu configuration Vadim Fedorenko
2023-08-11 20:03 ` [PATCH net-next v4 7/9] ice: implement dpll interface to control cgu Vadim Fedorenko
2023-08-12  6:19   ` Jiri Pirko
2023-08-11 20:03 ` [PATCH net-next v4 8/9] ptp_ocp: implement DPLL ops Vadim Fedorenko
2023-08-11 20:03 ` [PATCH net-next v4 9/9] mlx5: Implement SyncE support using DPLL infrastructure Vadim Fedorenko
2023-08-12  6:22 ` [PATCH net-next v4 0/9] Create common DPLL configuration API Jiri Pirko
2023-08-12 11:20   ` Vadim Fedorenko
2023-08-15  2:45 ` Jakub Kicinski
2023-08-15 11:36   ` Vadim Fedorenko
2023-08-15 11:52     ` Jiri Pirko
2023-08-15 14:32       ` Vadim Fedorenko
2023-08-15 17:02       ` Jakub Kicinski
2023-08-18 10:15         ` Kubalewski, Arkadiusz
2023-08-18 21:03           ` Jakub Kicinski

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