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Date: Fri, 17 Nov 2023 12:47:54 +0000
From: "Russell King (Oracle)" <linux@armlinux.org.uk>
To: Robert Marko <robimarko@gmail.com>
Cc: andrew@lunn.ch, hkallweit1@gmail.com, davem@davemloft.net,
	edumazet@google.com, kuba@kernel.org, pabeni@redhat.com,
	ansuelsmth@gmail.com, netdev@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH net-next 2/2] net: phy: aquantia: enable USXGMII autoneg
 on AQR107
Message-ID: <ZVdg+vFb46aFRtC0@shell.armlinux.org.uk>
References: <20231117100958.425354-1-robimarko@gmail.com>
 <20231117100958.425354-2-robimarko@gmail.com>
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Sender: Russell King (Oracle) <linux@armlinux.org.uk>

On Fri, Nov 17, 2023 at 11:09:49AM +0100, Robert Marko wrote:
> In case USXGMII is being used as the PHY interface mode then USXGMII
> autoneg must be enabled as well.
> 
> HW defaults to USXGMII autoneg being disabled which then results in
> autoneg timeout, so enable it in case USXGMII is used.

I was led to believe that the bitfield in bits 8:7 of the
VEND1_GLOBAL_CFG_* registers, when set to value '1' is something
to do with selecting USXGMII mode as opposed to 10GBASE-R. Could
you look in to that and whether that is the more correct way of
configuring the PHY for USXGMII mode?

Thanks.

-- 
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