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Date: Mon, 20 Nov 2023 22:03:48 +0800
From: Jisheng Zhang <jszhang@kernel.org>
To: Andrew Lunn <andrew@lunn.ch>
Cc: HeinerKallweit <hkallweit1@gmail.com>,
	Russell King <linux@armlinux.org.uk>,
	"David S.Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Conor Dooley <conor.dooley@microchip.com>, netdev@vger.kernel.org,
	linux-riscv@lists.infradead.org
Subject: Re: [RFC] support built-in ethernet phy which needs some mmio
 accesses
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References: <ZVoUPW8pJmv5AT10@xhacker>
 <b8c29d27-e0a2-4378-ba5f-6d95a438c023@lunn.ch>
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In-Reply-To: <b8c29d27-e0a2-4378-ba5f-6d95a438c023@lunn.ch>

On Sun, Nov 19, 2023 at 05:18:49PM +0100, Andrew Lunn wrote:
> On Sun, Nov 19, 2023 at 09:57:17PM +0800, Jisheng Zhang wrote:
> > Hi,
> > 
> > I want to upstream milkv duo (powered by cv1800b) ethernet support. The SoC
> > contains a built-in eth phy which also needs some initialization via.
> > mmio access during init. So, I need to do something like this(sol A):
> 
> What does this initialisation do?

Per my understanding of the vendor code, it reads calibration data from
efuse then apply the setting, set tx bias current, set MLT3 phase code,
and so on. I can see it switches to page 5, page 16, page 17 etc. to
apply settings. Compared with normal phy driver, the programming is
done via. the mmio rather than phy_read/write.

Here is the vendor source code:
https://github.com/milkv-duo/duo-buildroot-sdk/blob/develop/linux_5.10/drivers/net/phy/cvitek.c

Hi Heiner,

IIUC, the initialization also needs redo after power off, so it's
not init-once action.

Thanks
> 
> If you are turning on clocks, write a common clock provider, which the
> PHY driver can use. If its a reset, write a reset driver. If its a
> regulator, write a regulator driver, etc.
> 
>       Andrew