[PATCH net-next 00/15] Realtek RTL822x PHY rework to c45 and SerDes interface switching

[PATCH net-next 00/15] Realtek RTL822x PHY rework to c45 and SerDes interface switching

[Marek Behún]

Hi,

this series reworks the realtek PHY driver's support for rtl822x
2.5G transceivers:

- First I change the driver so that the high level driver methods
  only use clause 45 register accesses (the only clause 22 accesses
  are left when accessing c45 registers indirectly, if the MDIO bus
  does not support clause 45 accesses).
  The driver starts using the genphy_c45_* methods.

  At this point the driver is ready to be used on a MDIO bus capable
  of only clause 45 accesses, but will still work on clause 22 only
  MDIO bus.

- I then add support for SerDes mode switching between 2500base-x
  and sgmii, based on autonegotiated copper speed.

All this is done so that we can support another 2.5G copper SFP
module, which is enabled by the last patch.

Marek

Alexander Couzens (1):
  net: phy: realtek: configure SerDes mode for rtl822x PHYs

Marek Behún (14):
  net: phy: fail early with error code if indirect MMD access fails
  net: phy: export indirect MMD register accessors
  net: phy: realtek: rework MMD register access methods
  net: phy: realtek: fill .read_mmd and .write_mmd methods for all
    rtl822x PHYs
  net: mdio: add 2.5g and 5g related PMA speed constants
  net: phy: realtek: use generic MDIO constants
  net: phy: realtek: set is_c45 and fill in c45 IDs in PHY probe for
    rtl822x PHYs
  net: phy: realtek: use generic clause 45 feature reading for rtl822x
    PHYs
  net: phy: realtek: read standard MMD register for rtlgen speed
    capability
  net: phy: realtek: use generic c45 AN config with 1000baseT vendor
    extension for rtl822x
  net: phy: realtek: use generic c45 status reading with 1000baseT
    vendor extension for rtl822x
  net: phy: realtek: use generic c45 suspend/resume for rtl822x
  net: phy: realtek: drop .read_page and .write_page for rtl822x series
  net: sfp: add quirk for another multigig RollBall transceiver

 drivers/net/phy/phy-core.c |  54 ++++--
 drivers/net/phy/realtek.c  | 343 ++++++++++++++++++++++---------------
 drivers/net/phy/sfp.c      |   1 +
 include/linux/phy.h        |  10 ++
 include/uapi/linux/mdio.h  |   2 +
 5 files changed, 257 insertions(+), 153 deletions(-)

-- 
2.41.0

[PATCH net-next 01/15] net: phy: fail early with error code if indirect MMD access fails

[Marek Behún]

Check return values of __mdiobus_write() in mmd_phy_indirect() and
return value of mmd_phy_indirect() itself.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/phy-core.c | 52 +++++++++++++++++++++++++++++---------
 1 file changed, 40 insertions(+), 12 deletions(-)

diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
index 15f349e5995a..9318b65cca95 100644
--- a/drivers/net/phy/phy-core.c
+++ b/drivers/net/phy/phy-core.c
@@ -526,18 +526,50 @@ int phy_speed_down_core(struct phy_device *phydev)
 	return 0;
 }
 
-static void mmd_phy_indirect(struct mii_bus *bus, int phy_addr, int devad,
-			     u16 regnum)
+static int mmd_phy_indirect(struct mii_bus *bus, int phy_addr, int devad,
+			    u16 regnum)
 {
+	int ret;
+
 	/* Write the desired MMD Devad */
-	__mdiobus_write(bus, phy_addr, MII_MMD_CTRL, devad);
+	ret = __mdiobus_write(bus, phy_addr, MII_MMD_CTRL, devad);
+	if (ret < 0)
+		return ret;
 
 	/* Write the desired MMD register address */
-	__mdiobus_write(bus, phy_addr, MII_MMD_DATA, regnum);
+	ret = __mdiobus_write(bus, phy_addr, MII_MMD_DATA, regnum);
+	if (ret < 0)
+		return ret;
 
 	/* Select the Function : DATA with no post increment */
-	__mdiobus_write(bus, phy_addr, MII_MMD_CTRL,
-			devad | MII_MMD_CTRL_NOINCR);
+	return __mdiobus_write(bus, phy_addr, MII_MMD_CTRL,
+			       devad | MII_MMD_CTRL_NOINCR);
+}
+
+static int mmd_phy_read_indirect(struct mii_bus *bus, int phy_addr, int devad,
+				 u32 regnum)
+{
+	int ret;
+
+	ret = mmd_phy_indirect(bus, phy_addr, devad, regnum);
+	if (ret < 0)
+		return ret;
+
+	/* Read the content of the MMD's selected register */
+	return __mdiobus_read(bus, phy_addr, MII_MMD_DATA);
+}
+
+static int mmd_phy_write_indirect(struct mii_bus *bus, int phy_addr, int devad,
+				  u32 regnum, u16 val)
+{
+	int ret;
+
+	ret = mmd_phy_indirect(bus, phy_addr, devad, regnum);
+	if (ret < 0)
+		return ret;
+
+	/* Write the data into MMD's selected register */
+	return __mdiobus_write(bus, phy_addr, MII_MMD_DATA, val);
 }
 
 static int mmd_phy_read(struct mii_bus *bus, int phy_addr, bool is_c45,
@@ -546,9 +578,7 @@ static int mmd_phy_read(struct mii_bus *bus, int phy_addr, bool is_c45,
 	if (is_c45)
 		return __mdiobus_c45_read(bus, phy_addr, devad, regnum);
 
-	mmd_phy_indirect(bus, phy_addr, devad, regnum);
-	/* Read the content of the MMD's selected register */
-	return __mdiobus_read(bus, phy_addr, MII_MMD_DATA);
+	return mmd_phy_read_indirect(bus, phy_addr, devad, regnum);
 }
 
 static int mmd_phy_write(struct mii_bus *bus, int phy_addr, bool is_c45,
@@ -557,9 +587,7 @@ static int mmd_phy_write(struct mii_bus *bus, int phy_addr, bool is_c45,
 	if (is_c45)
 		return __mdiobus_c45_write(bus, phy_addr, devad, regnum, val);
 
-	mmd_phy_indirect(bus, phy_addr, devad, regnum);
-	/* Write the data into MMD's selected register */
-	return __mdiobus_write(bus, phy_addr, MII_MMD_DATA, val);
+	return mmd_phy_write_indirect(bus, phy_addr, devad, regnum, val);
 }
 
 /**
-- 
2.41.0

[PATCH net-next 02/15] net: phy: export indirect MMD register accessors

[Marek Behún]

Export mmd_phy_read_indirect() and mmd_phy_write_indirect(), the
indirect MMD accessors, so that the functions can be used from the
.read_mmd / .write_mmd phy_driver methods.

Add a __ prefix to these functions.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/phy-core.c | 14 ++++++++------
 include/linux/phy.h        | 10 ++++++++++
 2 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
index 9318b65cca95..150020cfa593 100644
--- a/drivers/net/phy/phy-core.c
+++ b/drivers/net/phy/phy-core.c
@@ -546,8 +546,8 @@ static int mmd_phy_indirect(struct mii_bus *bus, int phy_addr, int devad,
 			       devad | MII_MMD_CTRL_NOINCR);
 }
 
-static int mmd_phy_read_indirect(struct mii_bus *bus, int phy_addr, int devad,
-				 u32 regnum)
+int __mmd_phy_read_indirect(struct mii_bus *bus, int phy_addr, int devad,
+			    u32 regnum)
 {
 	int ret;
 
@@ -558,9 +558,10 @@ static int mmd_phy_read_indirect(struct mii_bus *bus, int phy_addr, int devad,
 	/* Read the content of the MMD's selected register */
 	return __mdiobus_read(bus, phy_addr, MII_MMD_DATA);
 }
+EXPORT_SYMBOL(__mmd_phy_read_indirect);
 
-static int mmd_phy_write_indirect(struct mii_bus *bus, int phy_addr, int devad,
-				  u32 regnum, u16 val)
+int __mmd_phy_write_indirect(struct mii_bus *bus, int phy_addr, int devad,
+			     u32 regnum, u16 val)
 {
 	int ret;
 
@@ -571,6 +572,7 @@ static int mmd_phy_write_indirect(struct mii_bus *bus, int phy_addr, int devad,
 	/* Write the data into MMD's selected register */
 	return __mdiobus_write(bus, phy_addr, MII_MMD_DATA, val);
 }
+EXPORT_SYMBOL(__mmd_phy_write_indirect);
 
 static int mmd_phy_read(struct mii_bus *bus, int phy_addr, bool is_c45,
 			int devad, u32 regnum)
@@ -578,7 +580,7 @@ static int mmd_phy_read(struct mii_bus *bus, int phy_addr, bool is_c45,
 	if (is_c45)
 		return __mdiobus_c45_read(bus, phy_addr, devad, regnum);
 
-	return mmd_phy_read_indirect(bus, phy_addr, devad, regnum);
+	return __mmd_phy_read_indirect(bus, phy_addr, devad, regnum);
 }
 
 static int mmd_phy_write(struct mii_bus *bus, int phy_addr, bool is_c45,
@@ -587,7 +589,7 @@ static int mmd_phy_write(struct mii_bus *bus, int phy_addr, bool is_c45,
 	if (is_c45)
 		return __mdiobus_c45_write(bus, phy_addr, devad, regnum, val);
 
-	return mmd_phy_write_indirect(bus, phy_addr, devad, regnum, val);
+	return __mmd_phy_write_indirect(bus, phy_addr, devad, regnum, val);
 }
 
 /**
diff --git a/include/linux/phy.h b/include/linux/phy.h
index e9e85d347587..65b79b155f3a 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -1358,6 +1358,16 @@ int phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum);
 	__ret; \
 })
 
+/*
+ * __mmd_phy_read_indirect, __mmd_phy_write_indirect - Convenience functions for
+ * indirectly accessing MMD registers via clause 22 registers 13 and 14. Can be
+ * used in phy_driver's .read_mmd and .write_mmd methods.
+ */
+int __mmd_phy_read_indirect(struct mii_bus *bus, int phy_addr, int devad,
+			    u32 regnum);
+int __mmd_phy_write_indirect(struct mii_bus *bus, int phy_addr, int devad,
+			     u32 regnum, u16 val);
+
 /*
  * __phy_read_mmd - Convenience function for reading a register
  * from an MMD on a given PHY.
-- 
2.41.0

[PATCH net-next 03/15] net: phy: realtek: rework MMD register access methods

[Marek Behún]

The .read_mmd() and .write_mmd() methods for rtlgen and rtl822x
currently allow access to only 6 MMD registers, via a vendor specific
mechanism (a paged read / write).

The PHY specification explains that MMD registers for MMDs 1 to 30 can
be accessed via the clause 22 indirect mechanism through registers 13
and 14, but this is not possible for MMD 31.

A Realtek contact explained that MMD 31 registers can be accessed by
setting clause 22 page register (register 31):
  page = mmd_reg >> 4
  reg = 0x10 | ((mmd_reg & 0xf) >> 1)

This mechanism is currently used in the driver. For example the
.read_mmd() method accesses the PCS.EEE_ABLE register by setting page
to 0xa5c and accessing register 0x12. By the formulas above, this
corresponds to MMD register 31.a5c4. The Realtek contact confirmed that
the PCS.EEE_ABLE register (3.0014) is also available via MMD alias
31.a5c4, and this is also true for the other registers:

  register name   address   page.reg  alias
  PCS.EEE_ABLE    3.0x0014  0xa5c.12  31.0xa5c4
  PCS.EEE_ABLE2   3.0x0015  0xa6e.16  31.0xa6ec
  AN.EEE_ADV      7.0x003c  0xa5d.10  31.0xa5d0
  AN.EEE_LPABLE   7.0x003d  0xa5d.11  31.0xa5d2
  AN.EEE_ADV2     7.0x003e  0xa6d.12  31.0xa6d4
  AN.EEE_LPABLE2  7.0x003f  0xa6d.10  31.0xa6d0

Since the registers are also available at the true MMD addresses where
they can be accessed via the indirect mechanism (via registers 13 and
14) we can rework the code to be more generic and allow access to all
MMD registers.

Rework the .read_mmd() and .write_mmd() methods for rtlgen and rtl822x
PHYs:
- use direct clause 45 access if the MDIO bus supports it
- use the indirect access via clause 22 registers 13 and 14 for MMDs
  1 to 30
- use the vendor specific method to access MMD 31 registers

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/realtek.c | 111 ++++++++++++++++----------------------
 1 file changed, 45 insertions(+), 66 deletions(-)

diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 894172a3e15f..6e84f460a888 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -585,84 +585,63 @@ static int rtlgen_read_status(struct phy_device *phydev)
 	return rtlgen_get_speed(phydev);
 }
 
-static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
+static int rtlgen_read_mmd(struct phy_device *phydev, int dev, u16 reg)
 {
-	int ret;
+	struct mii_bus *bus = phydev->mdio.bus;
+	int addr = phydev->mdio.addr;
+	int page, ret;
 
-	if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
-		rtl821x_write_page(phydev, 0xa5c);
-		ret = __phy_read(phydev, 0x12);
-		rtl821x_write_page(phydev, 0);
-	} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
-		rtl821x_write_page(phydev, 0xa5d);
-		ret = __phy_read(phydev, 0x10);
-		rtl821x_write_page(phydev, 0);
-	} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
-		rtl821x_write_page(phydev, 0xa5d);
-		ret = __phy_read(phydev, 0x11);
-		rtl821x_write_page(phydev, 0);
-	} else {
-		ret = -EOPNOTSUPP;
-	}
+	/* use c45 access if MDIO bus supports them */
+	if (bus->read_c45)
+		return __mdiobus_c45_read(bus, addr, dev, reg);
 
-	return ret;
-}
+	/* use c22 indirect access for MMD != 31 */
+	if (dev != MDIO_MMD_VEND2)
+		return __mmd_phy_read_indirect(bus, addr, dev, reg);
 
-static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
-			    u16 val)
-{
-	int ret;
+	/* MDIO_MMD_VEND2 registers need to be accessed in a different way */
+	page = reg >> 4;
+	reg = 0x10 | ((reg & 0xf) >> 1);
 
-	if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
-		rtl821x_write_page(phydev, 0xa5d);
-		ret = __phy_write(phydev, 0x10, val);
-		rtl821x_write_page(phydev, 0);
-	} else {
-		ret = -EOPNOTSUPP;
-	}
+	ret = rtl821x_write_page(phydev, page);
+	if (ret < 0)
+		return ret;
 
-	return ret;
+	ret = __phy_read(phydev, reg);
+	if (ret < 0)
+		return ret;
+
+	return rtl821x_write_page(phydev, 0) ?: ret;
 }
 
-static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
+static int rtlgen_write_mmd(struct phy_device *phydev, int dev, u16 reg,
+			    u16 val)
 {
-	int ret = rtlgen_read_mmd(phydev, devnum, regnum);
-
-	if (ret != -EOPNOTSUPP)
-		return ret;
+	struct mii_bus *bus = phydev->mdio.bus;
+	int addr = phydev->mdio.addr;
+	int page, ret;
 
-	if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
-		rtl821x_write_page(phydev, 0xa6e);
-		ret = __phy_read(phydev, 0x16);
-		rtl821x_write_page(phydev, 0);
-	} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
-		rtl821x_write_page(phydev, 0xa6d);
-		ret = __phy_read(phydev, 0x12);
-		rtl821x_write_page(phydev, 0);
-	} else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
-		rtl821x_write_page(phydev, 0xa6d);
-		ret = __phy_read(phydev, 0x10);
-		rtl821x_write_page(phydev, 0);
-	}
+	/* use c45 access if MDIO bus supports them */
+	if (bus->write_c45)
+		return __mdiobus_c45_write(bus, addr, dev, reg, val);
 
-	return ret;
-}
+	/* use c22 indirect access for MMD != 31 */
+	if (dev != MDIO_MMD_VEND2)
+		return __mmd_phy_write_indirect(bus, addr, dev, reg, val);
 
-static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
-			     u16 val)
-{
-	int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
+	/* MDIO_MMD_VEND2 registers need to be accessed in a different way */
+	page = reg >> 4;
+	reg = 0x10 | ((reg & 0xf) >> 1);
 
-	if (ret != -EOPNOTSUPP)
+	ret = rtl821x_write_page(phydev, page);
+	if (ret < 0)
 		return ret;
 
-	if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
-		rtl821x_write_page(phydev, 0xa6d);
-		ret = __phy_write(phydev, 0x12, val);
-		rtl821x_write_page(phydev, 0);
-	}
+	ret = __phy_write(phydev, reg, val);
+	if (ret < 0)
+		return ret;
 
-	return ret;
+	return rtl821x_write_page(phydev, 0) ?: ret;
 }
 
 static int rtl822x_get_features(struct phy_device *phydev)
@@ -993,8 +972,8 @@ static struct phy_driver realtek_drvs[] = {
 		.resume		= rtlgen_resume,
 		.read_page	= rtl821x_read_page,
 		.write_page	= rtl821x_write_page,
-		.read_mmd	= rtl822x_read_mmd,
-		.write_mmd	= rtl822x_write_mmd,
+		.read_mmd	= rtlgen_read_mmd,
+		.write_mmd	= rtlgen_write_mmd,
 	}, {
 		PHY_ID_MATCH_EXACT(0x001cc840),
 		.name		= "RTL8226B_RTL8221B 2.5Gbps PHY",
@@ -1005,8 +984,8 @@ static struct phy_driver realtek_drvs[] = {
 		.resume		= rtlgen_resume,
 		.read_page	= rtl821x_read_page,
 		.write_page	= rtl821x_write_page,
-		.read_mmd	= rtl822x_read_mmd,
-		.write_mmd	= rtl822x_write_mmd,
+		.read_mmd	= rtlgen_read_mmd,
+		.write_mmd	= rtlgen_write_mmd,
 	}, {
 		PHY_ID_MATCH_EXACT(0x001cc838),
 		.name           = "RTL8226-CG 2.5Gbps PHY",
-- 
2.41.0

[PATCH net-next 04/15] net: phy: realtek: fill .read_mmd and .write_mmd methods for all rtl822x PHYs

[Marek Behún]

Fill in the .read_mmd() and .write_mmd() methods for all rtl822x PHYs,
so that we can start reimplementing rtl822x driver methods into using
genphy_c45_* functions.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/realtek.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 6e84f460a888..8f11320b38a8 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -996,6 +996,8 @@ static struct phy_driver realtek_drvs[] = {
 		.resume         = rtlgen_resume,
 		.read_page      = rtl821x_read_page,
 		.write_page     = rtl821x_write_page,
+		.read_mmd	= rtlgen_read_mmd,
+		.write_mmd	= rtlgen_write_mmd,
 	}, {
 		PHY_ID_MATCH_EXACT(0x001cc848),
 		.name           = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
@@ -1006,6 +1008,8 @@ static struct phy_driver realtek_drvs[] = {
 		.resume         = rtlgen_resume,
 		.read_page      = rtl821x_read_page,
 		.write_page     = rtl821x_write_page,
+		.read_mmd	= rtlgen_read_mmd,
+		.write_mmd	= rtlgen_write_mmd,
 	}, {
 		PHY_ID_MATCH_EXACT(0x001cc849),
 		.name           = "RTL8221B-VB-CG 2.5Gbps PHY",
@@ -1016,6 +1020,8 @@ static struct phy_driver realtek_drvs[] = {
 		.resume         = rtlgen_resume,
 		.read_page      = rtl821x_read_page,
 		.write_page     = rtl821x_write_page,
+		.read_mmd	= rtlgen_read_mmd,
+		.write_mmd	= rtlgen_write_mmd,
 	}, {
 		PHY_ID_MATCH_EXACT(0x001cc84a),
 		.name           = "RTL8221B-VM-CG 2.5Gbps PHY",
@@ -1026,6 +1032,8 @@ static struct phy_driver realtek_drvs[] = {
 		.resume         = rtlgen_resume,
 		.read_page      = rtl821x_read_page,
 		.write_page     = rtl821x_write_page,
+		.read_mmd	= rtlgen_read_mmd,
+		.write_mmd	= rtlgen_write_mmd,
 	}, {
 		PHY_ID_MATCH_EXACT(0x001cc961),
 		.name		= "RTL8366RB Gigabit Ethernet",
-- 
2.41.0

[PATCH net-next 05/15] net: mdio: add 2.5g and 5g related PMA speed constants

[Marek Behún]

Add constants indicating 2.5g and 5g ability in the MMD PMA speed
register.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 include/uapi/linux/mdio.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h
index d03863da180e..3c9097502403 100644
--- a/include/uapi/linux/mdio.h
+++ b/include/uapi/linux/mdio.h
@@ -138,6 +138,8 @@
 #define MDIO_PMA_SPEED_1000		0x0010	/* 1000M capable */
 #define MDIO_PMA_SPEED_100		0x0020	/* 100M capable */
 #define MDIO_PMA_SPEED_10		0x0040	/* 10M capable */
+#define MDIO_PMA_SPEED_2_5G		0x2000	/* 2.5G capable */
+#define MDIO_PMA_SPEED_5G		0x4000	/* 5G capable */
 #define MDIO_PCS_SPEED_10P2B		0x0002	/* 10PASS-TS/2BASE-TL capable */
 #define MDIO_PCS_SPEED_2_5G		0x0040	/* 2.5G capable */
 #define MDIO_PCS_SPEED_5G		0x0080	/* 5G capable */
-- 
2.41.0

[PATCH net-next 06/15] net: phy: realtek: use generic MDIO constants

[Marek Behún]

Drop the ad-hoc MDIO constants used in the driver and use generic
constants instead.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/realtek.c | 30 +++++++++++++-----------------
 1 file changed, 13 insertions(+), 17 deletions(-)

diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 8f11320b38a8..52a7022d6a64 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -57,14 +57,6 @@
 #define RTL8366RB_POWER_SAVE			0x15
 #define RTL8366RB_POWER_SAVE_ON			BIT(12)
 
-#define RTL_SUPPORTS_5000FULL			BIT(14)
-#define RTL_SUPPORTS_2500FULL			BIT(13)
-#define RTL_SUPPORTS_10000FULL			BIT(0)
-#define RTL_ADV_2500FULL			BIT(7)
-#define RTL_LPADV_10000FULL			BIT(11)
-#define RTL_LPADV_5000FULL			BIT(6)
-#define RTL_LPADV_2500FULL			BIT(5)
-
 #define RTL9000A_GINMR				0x14
 #define RTL9000A_GINMR_LINK_STATUS		BIT(4)
 
@@ -653,11 +645,11 @@ static int rtl822x_get_features(struct phy_device *phydev)
 		return val;
 
 	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
-			 phydev->supported, val & RTL_SUPPORTS_2500FULL);
+			 phydev->supported, val & MDIO_PMA_SPEED_2_5G);
 	linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
-			 phydev->supported, val & RTL_SUPPORTS_5000FULL);
+			 phydev->supported, val & MDIO_PMA_SPEED_5G);
 	linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
-			 phydev->supported, val & RTL_SUPPORTS_10000FULL);
+			 phydev->supported, val & MDIO_SPEED_10G);
 
 	return genphy_read_abilities(phydev);
 }
@@ -671,10 +663,11 @@ static int rtl822x_config_aneg(struct phy_device *phydev)
 
 		if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 				      phydev->advertising))
-			adv2500 = RTL_ADV_2500FULL;
+			adv2500 = MDIO_AN_10GBT_CTRL_ADV2_5G;
 
 		ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
-					       RTL_ADV_2500FULL, adv2500);
+					       MDIO_AN_10GBT_CTRL_ADV2_5G,
+					       adv2500);
 		if (ret < 0)
 			return ret;
 	}
@@ -693,11 +686,14 @@ static int rtl822x_read_status(struct phy_device *phydev)
 			return lpadv;
 
 		linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
-			phydev->lp_advertising, lpadv & RTL_LPADV_10000FULL);
+				 phydev->lp_advertising,
+				 lpadv & MDIO_AN_10GBT_STAT_LP10G);
 		linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
-			phydev->lp_advertising, lpadv & RTL_LPADV_5000FULL);
+				 phydev->lp_advertising,
+				 lpadv & MDIO_AN_10GBT_STAT_LP5G);
 		linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
-			phydev->lp_advertising, lpadv & RTL_LPADV_2500FULL);
+				 phydev->lp_advertising,
+				 lpadv & MDIO_AN_10GBT_STAT_LP2_5G);
 	}
 
 	ret = genphy_read_status(phydev);
@@ -715,7 +711,7 @@ static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
 	val = phy_read(phydev, 0x13);
 	phy_write(phydev, RTL821x_PAGE_SELECT, 0);
 
-	return val >= 0 && val & RTL_SUPPORTS_2500FULL;
+	return val >= 0 && val & MDIO_PMA_SPEED_2_5G;
 }
 
 static int rtlgen_match_phy_device(struct phy_device *phydev)
-- 
2.41.0

[PATCH net-next 07/15] net: phy: realtek: set is_c45 and fill in c45 IDs in PHY probe for rtl822x PHYs

[Marek Behún]

If the rtl822x was probed via clause 22 addressing, we need to set
phydev->is_c45 and fill in phydev->c45_ids so that genphy_c45_*
functions will work properly.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/realtek.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 52a7022d6a64..c621ce9378c5 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -636,6 +636,18 @@ static int rtlgen_write_mmd(struct phy_device *phydev, int dev, u16 reg,
 	return rtl821x_write_page(phydev, 0) ?: ret;
 }
 
+static int rtl822x_probe(struct phy_device *phydev)
+{
+	/* if the PHY was probed via c22, set is_c45 and fill in c45 IDs */
+	if (!phydev->is_c45) {
+		phydev->is_c45 = true;
+
+		return phy_get_c45_ids(phydev);
+	}
+
+	return 0;
+}
+
 static int rtl822x_get_features(struct phy_device *phydev)
 {
 	int val;
@@ -961,6 +973,7 @@ static struct phy_driver realtek_drvs[] = {
 	}, {
 		.name		= "RTL8226 2.5Gbps PHY",
 		.match_phy_device = rtl8226_match_phy_device,
+		.probe		= rtl822x_probe,
 		.get_features	= rtl822x_get_features,
 		.config_aneg	= rtl822x_config_aneg,
 		.read_status	= rtl822x_read_status,
@@ -973,6 +986,7 @@ static struct phy_driver realtek_drvs[] = {
 	}, {
 		PHY_ID_MATCH_EXACT(0x001cc840),
 		.name		= "RTL8226B_RTL8221B 2.5Gbps PHY",
+		.probe		= rtl822x_probe,
 		.get_features	= rtl822x_get_features,
 		.config_aneg	= rtl822x_config_aneg,
 		.read_status	= rtl822x_read_status,
@@ -985,6 +999,7 @@ static struct phy_driver realtek_drvs[] = {
 	}, {
 		PHY_ID_MATCH_EXACT(0x001cc838),
 		.name           = "RTL8226-CG 2.5Gbps PHY",
+		.probe		= rtl822x_probe,
 		.get_features   = rtl822x_get_features,
 		.config_aneg    = rtl822x_config_aneg,
 		.read_status    = rtl822x_read_status,
@@ -997,6 +1012,7 @@ static struct phy_driver realtek_drvs[] = {
 	}, {
 		PHY_ID_MATCH_EXACT(0x001cc848),
 		.name           = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
+		.probe		= rtl822x_probe,
 		.get_features   = rtl822x_get_features,
 		.config_aneg    = rtl822x_config_aneg,
 		.read_status    = rtl822x_read_status,
@@ -1009,6 +1025,7 @@ static struct phy_driver realtek_drvs[] = {
 	}, {
 		PHY_ID_MATCH_EXACT(0x001cc849),
 		.name           = "RTL8221B-VB-CG 2.5Gbps PHY",
+		.probe		= rtl822x_probe,
 		.get_features   = rtl822x_get_features,
 		.config_aneg    = rtl822x_config_aneg,
 		.read_status    = rtl822x_read_status,
@@ -1021,6 +1038,7 @@ static struct phy_driver realtek_drvs[] = {
 	}, {
 		PHY_ID_MATCH_EXACT(0x001cc84a),
 		.name           = "RTL8221B-VM-CG 2.5Gbps PHY",
+		.probe		= rtl822x_probe,
 		.get_features   = rtl822x_get_features,
 		.config_aneg    = rtl822x_config_aneg,
 		.read_status    = rtl822x_read_status,
-- 
2.41.0

[PATCH net-next 08/15] net: phy: realtek: use generic clause 45 feature reading for rtl822x PHYs

[Marek Behún]

Now that rtl822x PHYs .read_mmd() and .write_mmd() methods support
accessing all MMD registers, drop the .get_features() method so that
phy_probe() will use the generic genphy_c45_pma_read_abilities(),
which works properly on these trasceivers.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/realtek.c | 24 ------------------------
 1 file changed, 24 deletions(-)

diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index c621ce9378c5..66515981d2aa 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -648,24 +648,6 @@ static int rtl822x_probe(struct phy_device *phydev)
 	return 0;
 }
 
-static int rtl822x_get_features(struct phy_device *phydev)
-{
-	int val;
-
-	val = phy_read_paged(phydev, 0xa61, 0x13);
-	if (val < 0)
-		return val;
-
-	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
-			 phydev->supported, val & MDIO_PMA_SPEED_2_5G);
-	linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
-			 phydev->supported, val & MDIO_PMA_SPEED_5G);
-	linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
-			 phydev->supported, val & MDIO_SPEED_10G);
-
-	return genphy_read_abilities(phydev);
-}
-
 static int rtl822x_config_aneg(struct phy_device *phydev)
 {
 	int ret = 0;
@@ -974,7 +956,6 @@ static struct phy_driver realtek_drvs[] = {
 		.name		= "RTL8226 2.5Gbps PHY",
 		.match_phy_device = rtl8226_match_phy_device,
 		.probe		= rtl822x_probe,
-		.get_features	= rtl822x_get_features,
 		.config_aneg	= rtl822x_config_aneg,
 		.read_status	= rtl822x_read_status,
 		.suspend	= genphy_suspend,
@@ -987,7 +968,6 @@ static struct phy_driver realtek_drvs[] = {
 		PHY_ID_MATCH_EXACT(0x001cc840),
 		.name		= "RTL8226B_RTL8221B 2.5Gbps PHY",
 		.probe		= rtl822x_probe,
-		.get_features	= rtl822x_get_features,
 		.config_aneg	= rtl822x_config_aneg,
 		.read_status	= rtl822x_read_status,
 		.suspend	= genphy_suspend,
@@ -1000,7 +980,6 @@ static struct phy_driver realtek_drvs[] = {
 		PHY_ID_MATCH_EXACT(0x001cc838),
 		.name           = "RTL8226-CG 2.5Gbps PHY",
 		.probe		= rtl822x_probe,
-		.get_features   = rtl822x_get_features,
 		.config_aneg    = rtl822x_config_aneg,
 		.read_status    = rtl822x_read_status,
 		.suspend        = genphy_suspend,
@@ -1013,7 +992,6 @@ static struct phy_driver realtek_drvs[] = {
 		PHY_ID_MATCH_EXACT(0x001cc848),
 		.name           = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
 		.probe		= rtl822x_probe,
-		.get_features   = rtl822x_get_features,
 		.config_aneg    = rtl822x_config_aneg,
 		.read_status    = rtl822x_read_status,
 		.suspend        = genphy_suspend,
@@ -1026,7 +1004,6 @@ static struct phy_driver realtek_drvs[] = {
 		PHY_ID_MATCH_EXACT(0x001cc849),
 		.name           = "RTL8221B-VB-CG 2.5Gbps PHY",
 		.probe		= rtl822x_probe,
-		.get_features   = rtl822x_get_features,
 		.config_aneg    = rtl822x_config_aneg,
 		.read_status    = rtl822x_read_status,
 		.suspend        = genphy_suspend,
@@ -1039,7 +1016,6 @@ static struct phy_driver realtek_drvs[] = {
 		PHY_ID_MATCH_EXACT(0x001cc84a),
 		.name           = "RTL8221B-VM-CG 2.5Gbps PHY",
 		.probe		= rtl822x_probe,
-		.get_features   = rtl822x_get_features,
 		.config_aneg    = rtl822x_config_aneg,
 		.read_status    = rtl822x_read_status,
 		.suspend        = genphy_suspend,
-- 
2.41.0

[PATCH net-next 09/15] net: phy: realtek: read standard MMD register for rtlgen speed capability

[Marek Behún]

Read the standard "PMA/PMD speed ability" register instead of it's
vendor specific alias via paging in rtlgen_supports_2_5gbps(), which is
used by the .match_phy_device method.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/realtek.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 66515981d2aa..0bb56d89157a 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -699,11 +699,7 @@ static int rtl822x_read_status(struct phy_device *phydev)
 
 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
 {
-	int val;
-
-	phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
-	val = phy_read(phydev, 0x13);
-	phy_write(phydev, RTL821x_PAGE_SELECT, 0);
+	int val = rtlgen_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_SPEED);
 
 	return val >= 0 && val & MDIO_PMA_SPEED_2_5G;
 }
-- 
2.41.0

[PATCH net-next 10/15] net: phy: realtek: use generic c45 AN config with 1000baseT vendor extension for rtl822x

[Marek Behún]

Now that rtl822x PHYs .read_mmd() and .write_mmd() methods support
accessing all MMD registers, use the generic clause 45 functions
genphy_c45_an_config_aneg() and genphy_c45_pma_setup_forced() instead
of the clause 22 for configuring autonegotiation for the rtl822x
series.

Because 802.3-2018 does not define MMD registers for configuring
1000baseT autonegotiation, use vendor specific MMD register for this,
similar to how the marvell10g driver does it.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/realtek.c | 33 ++++++++++++++++++++-------------
 1 file changed, 20 insertions(+), 13 deletions(-)

diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 0bb56d89157a..592de975248f 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -54,6 +54,8 @@
 						 RTL8201F_ISR_LINK)
 #define RTL8201F_IER				0x13
 
+#define RTL8221_GBCR				0xa412
+
 #define RTL8366RB_POWER_SAVE			0x15
 #define RTL8366RB_POWER_SAVE_ON			BIT(12)
 
@@ -650,23 +652,28 @@ static int rtl822x_probe(struct phy_device *phydev)
 
 static int rtl822x_config_aneg(struct phy_device *phydev)
 {
-	int ret = 0;
+	bool changed = false;
+	u16 val;
+	int ret;
 
-	if (phydev->autoneg == AUTONEG_ENABLE) {
-		u16 adv2500 = 0;
+	if (phydev->autoneg == AUTONEG_DISABLE)
+		return genphy_c45_pma_setup_forced(phydev);
 
-		if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
-				      phydev->advertising))
-			adv2500 = MDIO_AN_10GBT_CTRL_ADV2_5G;
+	ret = genphy_c45_an_config_aneg(phydev);
+	if (ret < 0)
+		return ret;
+	if (ret > 0)
+		changed = true;
 
-		ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
-					       MDIO_AN_10GBT_CTRL_ADV2_5G,
-					       adv2500);
-		if (ret < 0)
-			return ret;
-	}
+	val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
+	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, RTL8221_GBCR,
+				     ADVERTISE_1000FULL, val);
+	if (ret < 0)
+		return ret;
+	if (ret > 0)
+		changed = true;
 
-	return __genphy_config_aneg(phydev, ret);
+	return genphy_c45_check_and_restart_aneg(phydev, changed);
 }
 
 static int rtl822x_read_status(struct phy_device *phydev)
-- 
2.41.0

[PATCH net-next 11/15] net: phy: realtek: use generic c45 status reading with 1000baseT vendor extension for rtl822x

[Marek Behún]

Now that rtl822x PHYs .read_mmd() and .write_mmd() methods support
accessing all MMD registers, use the generic clause 45 function
genphy_c45_read_status() instead of the current clause 22 version for
reading status for the rtl822x series of Realtek transceivers.

Because 802.3-2018 does not define MMD registers for reading 1000baseT
autonegotiation status, use vendor specific MMD register for this.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/realtek.c | 28 ++++++++--------------------
 1 file changed, 8 insertions(+), 20 deletions(-)

diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 592de975248f..f36b2bfabe57 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -55,6 +55,7 @@
 #define RTL8201F_IER				0x13
 
 #define RTL8221_GBCR				0xa412
+#define RTL8221_GANLPAR				0xa414
 
 #define RTL8366RB_POWER_SAVE			0x15
 #define RTL8366RB_POWER_SAVE_ON			BIT(12)
@@ -678,30 +679,17 @@ static int rtl822x_config_aneg(struct phy_device *phydev)
 
 static int rtl822x_read_status(struct phy_device *phydev)
 {
-	int ret;
+	int val;
 
 	if (phydev->autoneg == AUTONEG_ENABLE) {
-		int lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
-
-		if (lpadv < 0)
-			return lpadv;
-
-		linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
-				 phydev->lp_advertising,
-				 lpadv & MDIO_AN_10GBT_STAT_LP10G);
-		linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
-				 phydev->lp_advertising,
-				 lpadv & MDIO_AN_10GBT_STAT_LP5G);
-		linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
-				 phydev->lp_advertising,
-				 lpadv & MDIO_AN_10GBT_STAT_LP2_5G);
-	}
+		val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8221_GANLPAR);
+		if (val < 0)
+			return val;
 
-	ret = genphy_read_status(phydev);
-	if (ret < 0)
-		return ret;
+		mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
+	}
 
-	return rtlgen_get_speed(phydev);
+	return genphy_c45_read_status(phydev);
 }
 
 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
-- 
2.41.0

[PATCH net-next 12/15] net: phy: realtek: use generic c45 suspend/resume for rtl822x

[Marek Behún]

Now that rtl822x PHYs .read_mmd() and .write_mmd() methods support
accessing all MMD registers, use the generic clause 45 functions
genphy_c45_pma_suspend() and genphy_c45_pma_resume() for the rtl822x
series of Realtek transceivers.

Add a 20ms delay after resume, as done in the current resume
implementation.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/realtek.c | 36 ++++++++++++++++++++++++------------
 1 file changed, 24 insertions(+), 12 deletions(-)

diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index f36b2bfabe57..cf608d390aa5 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -651,6 +651,18 @@ static int rtl822x_probe(struct phy_device *phydev)
 	return 0;
 }
 
+static int rtl822x_resume(struct phy_device *phydev)
+{
+	int ret = genphy_c45_pma_resume(phydev);
+
+	if (ret < 0)
+		return ret;
+
+	msleep(20);
+
+	return 0;
+}
+
 static int rtl822x_config_aneg(struct phy_device *phydev)
 {
 	bool changed = false;
@@ -949,8 +961,8 @@ static struct phy_driver realtek_drvs[] = {
 		.probe		= rtl822x_probe,
 		.config_aneg	= rtl822x_config_aneg,
 		.read_status	= rtl822x_read_status,
-		.suspend	= genphy_suspend,
-		.resume		= rtlgen_resume,
+		.suspend	= genphy_c45_pma_suspend,
+		.resume		= rtl822x_resume,
 		.read_page	= rtl821x_read_page,
 		.write_page	= rtl821x_write_page,
 		.read_mmd	= rtlgen_read_mmd,
@@ -961,8 +973,8 @@ static struct phy_driver realtek_drvs[] = {
 		.probe		= rtl822x_probe,
 		.config_aneg	= rtl822x_config_aneg,
 		.read_status	= rtl822x_read_status,
-		.suspend	= genphy_suspend,
-		.resume		= rtlgen_resume,
+		.suspend	= genphy_c45_pma_suspend,
+		.resume		= rtl822x_resume,
 		.read_page	= rtl821x_read_page,
 		.write_page	= rtl821x_write_page,
 		.read_mmd	= rtlgen_read_mmd,
@@ -973,8 +985,8 @@ static struct phy_driver realtek_drvs[] = {
 		.probe		= rtl822x_probe,
 		.config_aneg    = rtl822x_config_aneg,
 		.read_status    = rtl822x_read_status,
-		.suspend        = genphy_suspend,
-		.resume         = rtlgen_resume,
+		.suspend	= genphy_c45_pma_suspend,
+		.resume		= rtl822x_resume,
 		.read_page      = rtl821x_read_page,
 		.write_page     = rtl821x_write_page,
 		.read_mmd	= rtlgen_read_mmd,
@@ -985,8 +997,8 @@ static struct phy_driver realtek_drvs[] = {
 		.probe		= rtl822x_probe,
 		.config_aneg    = rtl822x_config_aneg,
 		.read_status    = rtl822x_read_status,
-		.suspend        = genphy_suspend,
-		.resume         = rtlgen_resume,
+		.suspend	= genphy_c45_pma_suspend,
+		.resume		= rtl822x_resume,
 		.read_page      = rtl821x_read_page,
 		.write_page     = rtl821x_write_page,
 		.read_mmd	= rtlgen_read_mmd,
@@ -997,8 +1009,8 @@ static struct phy_driver realtek_drvs[] = {
 		.probe		= rtl822x_probe,
 		.config_aneg    = rtl822x_config_aneg,
 		.read_status    = rtl822x_read_status,
-		.suspend        = genphy_suspend,
-		.resume         = rtlgen_resume,
+		.suspend	= genphy_c45_pma_suspend,
+		.resume		= rtl822x_resume,
 		.read_page      = rtl821x_read_page,
 		.write_page     = rtl821x_write_page,
 		.read_mmd	= rtlgen_read_mmd,
@@ -1009,8 +1021,8 @@ static struct phy_driver realtek_drvs[] = {
 		.probe		= rtl822x_probe,
 		.config_aneg    = rtl822x_config_aneg,
 		.read_status    = rtl822x_read_status,
-		.suspend        = genphy_suspend,
-		.resume         = rtlgen_resume,
+		.suspend	= genphy_c45_pma_suspend,
+		.resume		= rtl822x_resume,
 		.read_page      = rtl821x_read_page,
 		.write_page     = rtl821x_write_page,
 		.read_mmd	= rtlgen_read_mmd,
-- 
2.41.0

[PATCH net-next 13/15] net: phy: realtek: drop .read_page and .write_page for rtl822x series

[Marek Behún]

Drop the .read_page() and .write_page() methods for rtl822x series.

The rtl822x driver methods are now reimplemented to only access clause
45 registers and these are the last methods that explicitly access
clause 22 registers.

If the underlying MDIO bus is clause 22, the paging mechanism is still
used internally in the .read_mmd() and .write_mmd() methods when
accessing registers in MMD 31.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/realtek.c | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index cf608d390aa5..e2f68ac4b005 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -963,8 +963,6 @@ static struct phy_driver realtek_drvs[] = {
 		.read_status	= rtl822x_read_status,
 		.suspend	= genphy_c45_pma_suspend,
 		.resume		= rtl822x_resume,
-		.read_page	= rtl821x_read_page,
-		.write_page	= rtl821x_write_page,
 		.read_mmd	= rtlgen_read_mmd,
 		.write_mmd	= rtlgen_write_mmd,
 	}, {
@@ -975,8 +973,6 @@ static struct phy_driver realtek_drvs[] = {
 		.read_status	= rtl822x_read_status,
 		.suspend	= genphy_c45_pma_suspend,
 		.resume		= rtl822x_resume,
-		.read_page	= rtl821x_read_page,
-		.write_page	= rtl821x_write_page,
 		.read_mmd	= rtlgen_read_mmd,
 		.write_mmd	= rtlgen_write_mmd,
 	}, {
@@ -987,8 +983,6 @@ static struct phy_driver realtek_drvs[] = {
 		.read_status    = rtl822x_read_status,
 		.suspend	= genphy_c45_pma_suspend,
 		.resume		= rtl822x_resume,
-		.read_page      = rtl821x_read_page,
-		.write_page     = rtl821x_write_page,
 		.read_mmd	= rtlgen_read_mmd,
 		.write_mmd	= rtlgen_write_mmd,
 	}, {
@@ -999,8 +993,6 @@ static struct phy_driver realtek_drvs[] = {
 		.read_status    = rtl822x_read_status,
 		.suspend	= genphy_c45_pma_suspend,
 		.resume		= rtl822x_resume,
-		.read_page      = rtl821x_read_page,
-		.write_page     = rtl821x_write_page,
 		.read_mmd	= rtlgen_read_mmd,
 		.write_mmd	= rtlgen_write_mmd,
 	}, {
@@ -1011,8 +1003,6 @@ static struct phy_driver realtek_drvs[] = {
 		.read_status    = rtl822x_read_status,
 		.suspend	= genphy_c45_pma_suspend,
 		.resume		= rtl822x_resume,
-		.read_page      = rtl821x_read_page,
-		.write_page     = rtl821x_write_page,
 		.read_mmd	= rtlgen_read_mmd,
 		.write_mmd	= rtlgen_write_mmd,
 	}, {
@@ -1023,8 +1013,6 @@ static struct phy_driver realtek_drvs[] = {
 		.read_status    = rtl822x_read_status,
 		.suspend	= genphy_c45_pma_suspend,
 		.resume		= rtl822x_resume,
-		.read_page      = rtl821x_read_page,
-		.write_page     = rtl821x_write_page,
 		.read_mmd	= rtlgen_read_mmd,
 		.write_mmd	= rtlgen_write_mmd,
 	}, {
-- 
2.41.0

[PATCH net-next 14/15] net: phy: realtek: configure SerDes mode for rtl822x PHYs

[Marek Behún]

From: Alexander Couzens <lynxis@fe80.eu>

The rtl822x series support switching SerDes mode between 2500base-x and
sgmii based on the negotiated copper speed.

Configure this switching mode according to SerDes modes supported by
host.

Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
[ refactored, dropped HiSGMII mode and changed commit message ]
Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/realtek.c | 97 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 95 insertions(+), 2 deletions(-)

diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index e2f68ac4b005..5d03c5b7afb5 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -54,6 +54,11 @@
 						 RTL8201F_ISR_LINK)
 #define RTL8201F_IER				0x13
 
+#define RTL822X_VND1_SERDES_OPTION			0x697a
+#define RTL822X_VND1_SERDES_OPTION_MODE_MASK		GENMASK(5, 0)
+#define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII	0
+#define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX	2
+
 #define RTL8221_GBCR				0xa412
 #define RTL8221_GANLPAR				0xa414
 
@@ -663,6 +668,60 @@ static int rtl822x_resume(struct phy_device *phydev)
 	return 0;
 }
 
+static int rtl822x_config_init(struct phy_device *phydev)
+{
+	bool has_2500, has_sgmii;
+	u16 mode;
+	int ret;
+
+	has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX,
+			    phydev->host_interfaces) ||
+		   phydev->interface == PHY_INTERFACE_MODE_2500BASEX;
+
+	has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII,
+			     phydev->host_interfaces) ||
+		    phydev->interface == PHY_INTERFACE_MODE_SGMII;
+
+	if (!has_2500 && !has_sgmii)
+		return 0;
+
+	/* fill in possible interfaces */
+	__assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces,
+		     has_2500);
+	__assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces,
+		     has_sgmii);
+
+	/* determine SerDes option mode */
+	if (has_2500 && !has_sgmii)
+		mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX;
+	else
+		mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII;
+
+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0);
+	if (ret < 0)
+		return ret;
+
+	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1,
+				     RTL822X_VND1_SERDES_OPTION,
+				     RTL822X_VND1_SERDES_OPTION_MODE_MASK,
+				     mode);
+	if (ret < 0)
+		return ret;
+
+	/* the following 3 writes into SerDes control are needed for 2500base-x
+	 * mode to work properly
+	 */
+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503);
+	if (ret < 0)
+		return ret;
+
+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455);
+	if (ret < 0)
+		return ret;
+
+	return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020);
+}
+
 static int rtl822x_config_aneg(struct phy_device *phydev)
 {
 	bool changed = false;
@@ -689,9 +748,31 @@ static int rtl822x_config_aneg(struct phy_device *phydev)
 	return genphy_c45_check_and_restart_aneg(phydev, changed);
 }
 
+static void rtl822x_update_interface(struct phy_device *phydev)
+{
+	/* PHY changes SerDes mode between 2500base-x and sgmii based on
+	 * copper speed, if sgmii is supported
+	 */
+	if (!test_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces))
+		return;
+
+	switch (phydev->speed) {
+	case SPEED_2500:
+		phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
+		break;
+	case SPEED_1000:
+	case SPEED_100:
+	case SPEED_10:
+		phydev->interface = PHY_INTERFACE_MODE_SGMII;
+		break;
+	default:
+		break;
+	}
+}
+
 static int rtl822x_read_status(struct phy_device *phydev)
 {
-	int val;
+	int ret, val;
 
 	if (phydev->autoneg == AUTONEG_ENABLE) {
 		val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8221_GANLPAR);
@@ -701,7 +782,13 @@ static int rtl822x_read_status(struct phy_device *phydev)
 		mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
 	}
 
-	return genphy_c45_read_status(phydev);
+	ret = genphy_c45_read_status(phydev);
+	if (ret < 0)
+		return ret;
+
+	rtl822x_update_interface(phydev);
+
+	return 0;
 }
 
 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
@@ -959,6 +1046,7 @@ static struct phy_driver realtek_drvs[] = {
 		.name		= "RTL8226 2.5Gbps PHY",
 		.match_phy_device = rtl8226_match_phy_device,
 		.probe		= rtl822x_probe,
+		.config_init	= rtl822x_config_init,
 		.config_aneg	= rtl822x_config_aneg,
 		.read_status	= rtl822x_read_status,
 		.suspend	= genphy_c45_pma_suspend,
@@ -969,6 +1057,7 @@ static struct phy_driver realtek_drvs[] = {
 		PHY_ID_MATCH_EXACT(0x001cc840),
 		.name		= "RTL8226B_RTL8221B 2.5Gbps PHY",
 		.probe		= rtl822x_probe,
+		.config_init	= rtl822x_config_init,
 		.config_aneg	= rtl822x_config_aneg,
 		.read_status	= rtl822x_read_status,
 		.suspend	= genphy_c45_pma_suspend,
@@ -979,6 +1068,7 @@ static struct phy_driver realtek_drvs[] = {
 		PHY_ID_MATCH_EXACT(0x001cc838),
 		.name           = "RTL8226-CG 2.5Gbps PHY",
 		.probe		= rtl822x_probe,
+		.config_init	= rtl822x_config_init,
 		.config_aneg    = rtl822x_config_aneg,
 		.read_status    = rtl822x_read_status,
 		.suspend	= genphy_c45_pma_suspend,
@@ -989,6 +1079,7 @@ static struct phy_driver realtek_drvs[] = {
 		PHY_ID_MATCH_EXACT(0x001cc848),
 		.name           = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
 		.probe		= rtl822x_probe,
+		.config_init	= rtl822x_config_init,
 		.config_aneg    = rtl822x_config_aneg,
 		.read_status    = rtl822x_read_status,
 		.suspend	= genphy_c45_pma_suspend,
@@ -999,6 +1090,7 @@ static struct phy_driver realtek_drvs[] = {
 		PHY_ID_MATCH_EXACT(0x001cc849),
 		.name           = "RTL8221B-VB-CG 2.5Gbps PHY",
 		.probe		= rtl822x_probe,
+		.config_init	= rtl822x_config_init,
 		.config_aneg    = rtl822x_config_aneg,
 		.read_status    = rtl822x_read_status,
 		.suspend	= genphy_c45_pma_suspend,
@@ -1009,6 +1101,7 @@ static struct phy_driver realtek_drvs[] = {
 		PHY_ID_MATCH_EXACT(0x001cc84a),
 		.name           = "RTL8221B-VM-CG 2.5Gbps PHY",
 		.probe		= rtl822x_probe,
+		.config_init	= rtl822x_config_init,
 		.config_aneg    = rtl822x_config_aneg,
 		.read_status    = rtl822x_read_status,
 		.suspend	= genphy_c45_pma_suspend,
-- 
2.41.0

[PATCH net-next 15/15] net: sfp: add quirk for another multigig RollBall transceiver

[Marek Behún]

Add quirk for another RollBall copper transceiver: Turris RTSFP-2.5G,
containing 2.5g capable RTL8221B PHY.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/net/phy/sfp.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/phy/sfp.c b/drivers/net/phy/sfp.c
index 3780a96d2caa..44ce8eba900a 100644
--- a/drivers/net/phy/sfp.c
+++ b/drivers/net/phy/sfp.c
@@ -499,6 +499,7 @@ static const struct sfp_quirk sfp_quirks[] = {
 	SFP_QUIRK_M("OEM", "SFP-2.5G-T", sfp_quirk_oem_2_5g),
 	SFP_QUIRK_F("OEM", "RTSFP-10", sfp_fixup_rollball_cc),
 	SFP_QUIRK_F("OEM", "RTSFP-10G", sfp_fixup_rollball_cc),
+	SFP_QUIRK_F("Turris", "RTSFP-2.5G", sfp_fixup_rollball),
 	SFP_QUIRK_F("Turris", "RTSFP-10", sfp_fixup_rollball),
 	SFP_QUIRK_F("Turris", "RTSFP-10G", sfp_fixup_rollball),
 };
-- 
2.41.0

Re: [PATCH net-next 00/15] Realtek RTL822x PHY rework to c45 and SerDes interface switching

[Heiner Kallweit]

On 20.12.2023 16:55, Marek Behún wrote:
> Hi,
> 
> this series reworks the realtek PHY driver's support for rtl822x
> 2.5G transceivers:
> 
> - First I change the driver so that the high level driver methods
>   only use clause 45 register accesses (the only clause 22 accesses
>   are left when accessing c45 registers indirectly, if the MDIO bus
>   does not support clause 45 accesses).
>   The driver starts using the genphy_c45_* methods.
> 
>   At this point the driver is ready to be used on a MDIO bus capable
>   of only clause 45 accesses, but will still work on clause 22 only
>   MDIO bus.
> 
> - I then add support for SerDes mode switching between 2500base-x
>   and sgmii, based on autonegotiated copper speed.
> 
> All this is done so that we can support another 2.5G copper SFP
> module, which is enabled by the last patch.
> 

Has been verified that the RTL8125-integrated PHY's still work
properly with this patch set?

Re: [PATCH net-next 00/15] Realtek RTL822x PHY rework to c45 and SerDes interface switching

[Marek Behún]

On Wed, 20 Dec 2023 17:20:07 +0100
Heiner Kallweit <hkallweit1@gmail.com> wrote:

> On 20.12.2023 16:55, Marek Behún wrote:
> > Hi,
> > 
> > this series reworks the realtek PHY driver's support for rtl822x
> > 2.5G transceivers:
> > 
> > - First I change the driver so that the high level driver methods
> >   only use clause 45 register accesses (the only clause 22 accesses
> >   are left when accessing c45 registers indirectly, if the MDIO bus
> >   does not support clause 45 accesses).
> >   The driver starts using the genphy_c45_* methods.
> > 
> >   At this point the driver is ready to be used on a MDIO bus capable
> >   of only clause 45 accesses, but will still work on clause 22 only
> >   MDIO bus.
> > 
> > - I then add support for SerDes mode switching between 2500base-x
> >   and sgmii, based on autonegotiated copper speed.
> > 
> > All this is done so that we can support another 2.5G copper SFP
> > module, which is enabled by the last patch.
> >   
> 
> Has been verified that the RTL8125-integrated PHY's still work
> properly with this patch set?
> 

Hi Heiner,

no, I wanted to send you an email to test this. I do not have the
controllers with integrates PHYs.

Can you test this?

Also do you have a controller where the rtlgen driver is used but it
only supports 1gbps ? I.e. where the PHY ID is RTL_GENERIC_PHYID
(0x001cc800).

I am asking because I am told that it also is clause 45, so the drivers
can potentially be merged completely (the rtl822x_ functions can be
merged with rtlgen_ functions and everything rewritten to clause 45,
and gentphy_c45_ functions can be used).

Marek

Re: [PATCH net-next 00/15] Realtek RTL822x PHY rework to c45 and SerDes interface switching

[Heiner Kallweit]

On 20.12.2023 17:25, Marek Behún wrote:
> On Wed, 20 Dec 2023 17:20:07 +0100
> Heiner Kallweit <hkallweit1@gmail.com> wrote:
> 
>> On 20.12.2023 16:55, Marek Behún wrote:
>>> Hi,
>>>
>>> this series reworks the realtek PHY driver's support for rtl822x
>>> 2.5G transceivers:
>>>
>>> - First I change the driver so that the high level driver methods
>>>   only use clause 45 register accesses (the only clause 22 accesses
>>>   are left when accessing c45 registers indirectly, if the MDIO bus
>>>   does not support clause 45 accesses).
>>>   The driver starts using the genphy_c45_* methods.
>>>
>>>   At this point the driver is ready to be used on a MDIO bus capable
>>>   of only clause 45 accesses, but will still work on clause 22 only
>>>   MDIO bus.
>>>
>>> - I then add support for SerDes mode switching between 2500base-x
>>>   and sgmii, based on autonegotiated copper speed.
>>>
>>> All this is done so that we can support another 2.5G copper SFP
>>> module, which is enabled by the last patch.
>>>   
>>
>> Has been verified that the RTL8125-integrated PHY's still work
>> properly with this patch set?
>>
> 
> Hi Heiner,
> 
> no, I wanted to send you an email to test this. I do not have the
> controllers with integrates PHYs.
> 
Quite some newer consumer mainboards come with on-board RTL8125, also
a lot of cheap add-on cards with this chip is available.
RTL8125 comes in different flavors, with different integrated PHY's.
I have one add-on card with RTL8125 that I can use for testing.

> Can you test this?
> 
> Also do you have a controller where the rtlgen driver is used but it
> only supports 1gbps ? I.e. where the PHY ID is RTL_GENERIC_PHYID
> (0x001cc800).
> 
Most of the consumer mainboards and PC's come with such a MAC/PHY
controller, nowadays it's usually RTL8111h. And yes, I have such a
test system.
Note that there are also PHY's with this generic ID that are 100M only
(on certain RTL8101 chips).

> I am asking because I am told that it also is clause 45, so the drivers
> can potentially be merged completely (the rtl822x_ functions can be
> merged with rtlgen_ functions and everything rewritten to clause 45,
> and gentphy_c45_ functions can be used).
> 
I doubt it's C45, most likely the integrated 1G PHY's are an evolution
of RTL8211f and similar PHY's. There may also be differences between
all the PHY's sharing the generic id 0x001cc800. But I can't say for
sure because I don't have access to any Realtek datasheets.

To be 100% sure testing would have to be done on all relevant RTL8101/
RTL8168/RTL8125 chip versions.

> Marek

Heiner

Re: [PATCH net-next 13/15] net: phy: realtek: drop .read_page and .write_page for rtl822x series

[Heiner Kallweit]

On 20.12.2023 16:55, Marek Behún wrote:
> Drop the .read_page() and .write_page() methods for rtl822x series.
> 
> The rtl822x driver methods are now reimplemented to only access clause
> 45 registers and these are the last methods that explicitly access
> clause 22 registers.
> 
> If the underlying MDIO bus is clause 22, the paging mechanism is still
> used internally in the .read_mmd() and .write_mmd() methods when
> accessing registers in MMD 31.
> 
> Signed-off-by: Marek Behún <kabel@kernel.org>
> ---
>  drivers/net/phy/realtek.c | 12 ------------
>  1 file changed, 12 deletions(-)
> 
> diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
> index cf608d390aa5..e2f68ac4b005 100644
> --- a/drivers/net/phy/realtek.c
> +++ b/drivers/net/phy/realtek.c
> @@ -963,8 +963,6 @@ static struct phy_driver realtek_drvs[] = {
>  		.read_status	= rtl822x_read_status,
>  		.suspend	= genphy_c45_pma_suspend,
>  		.resume		= rtl822x_resume,
> -		.read_page	= rtl821x_read_page,
> -		.write_page	= rtl821x_write_page,
>  		.read_mmd	= rtlgen_read_mmd,
>  		.write_mmd	= rtlgen_write_mmd,
>  	}, {
> @@ -975,8 +973,6 @@ static struct phy_driver realtek_drvs[] = {
>  		.read_status	= rtl822x_read_status,
>  		.suspend	= genphy_c45_pma_suspend,
>  		.resume		= rtl822x_resume,
> -		.read_page	= rtl821x_read_page,
> -		.write_page	= rtl821x_write_page,
>  		.read_mmd	= rtlgen_read_mmd,
>  		.write_mmd	= rtlgen_write_mmd,
>  	}, {
> @@ -987,8 +983,6 @@ static struct phy_driver realtek_drvs[] = {
>  		.read_status    = rtl822x_read_status,
>  		.suspend	= genphy_c45_pma_suspend,
>  		.resume		= rtl822x_resume,
> -		.read_page      = rtl821x_read_page,
> -		.write_page     = rtl821x_write_page,
>  		.read_mmd	= rtlgen_read_mmd,
>  		.write_mmd	= rtlgen_write_mmd,
>  	}, {
> @@ -999,8 +993,6 @@ static struct phy_driver realtek_drvs[] = {
>  		.read_status    = rtl822x_read_status,
>  		.suspend	= genphy_c45_pma_suspend,
>  		.resume		= rtl822x_resume,
> -		.read_page      = rtl821x_read_page,
> -		.write_page     = rtl821x_write_page,
>  		.read_mmd	= rtlgen_read_mmd,
>  		.write_mmd	= rtlgen_write_mmd,
>  	}, {
> @@ -1011,8 +1003,6 @@ static struct phy_driver realtek_drvs[] = {
>  		.read_status    = rtl822x_read_status,
>  		.suspend	= genphy_c45_pma_suspend,
>  		.resume		= rtl822x_resume,
> -		.read_page      = rtl821x_read_page,
> -		.write_page     = rtl821x_write_page,
>  		.read_mmd	= rtlgen_read_mmd,
>  		.write_mmd	= rtlgen_write_mmd,
>  	}, {
> @@ -1023,8 +1013,6 @@ static struct phy_driver realtek_drvs[] = {
>  		.read_status    = rtl822x_read_status,
>  		.suspend	= genphy_c45_pma_suspend,
>  		.resume		= rtl822x_resume,
> -		.read_page      = rtl821x_read_page,
> -		.write_page     = rtl821x_write_page,
>  		.read_mmd	= rtlgen_read_mmd,
>  		.write_mmd	= rtlgen_write_mmd,
>  	}, {

Dropping the read_page/write_page hooks will be problematic,
because they are used by the PHY initialization in e.g.
rtl8125a_2_hw_phy_config().

Re: [PATCH net-next 13/15] net: phy: realtek: drop .read_page and .write_page for rtl822x series

[Marek Behún]

On Wed, 20 Dec 2023 18:23:21 +0100
Heiner Kallweit <hkallweit1@gmail.com> wrote:

> On 20.12.2023 16:55, Marek Behún wrote:
> > Drop the .read_page() and .write_page() methods for rtl822x series.
> > 
> > The rtl822x driver methods are now reimplemented to only access clause
> > 45 registers and these are the last methods that explicitly access
> > clause 22 registers.
> > 
> > If the underlying MDIO bus is clause 22, the paging mechanism is still
> > used internally in the .read_mmd() and .write_mmd() methods when
> > accessing registers in MMD 31.
> > 
> > Signed-off-by: Marek Behún <kabel@kernel.org>
> > ---
> >  drivers/net/phy/realtek.c | 12 ------------
> >  1 file changed, 12 deletions(-)
> > 
> > diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
> > index cf608d390aa5..e2f68ac4b005 100644
> > --- a/drivers/net/phy/realtek.c
> > +++ b/drivers/net/phy/realtek.c
> > @@ -963,8 +963,6 @@ static struct phy_driver realtek_drvs[] = {
> >  		.read_status	= rtl822x_read_status,
> >  		.suspend	= genphy_c45_pma_suspend,
> >  		.resume		= rtl822x_resume,
> > -		.read_page	= rtl821x_read_page,
> > -		.write_page	= rtl821x_write_page,
> >  		.read_mmd	= rtlgen_read_mmd,
> >  		.write_mmd	= rtlgen_write_mmd,
> >  	}, {
> > @@ -975,8 +973,6 @@ static struct phy_driver realtek_drvs[] = {
> >  		.read_status	= rtl822x_read_status,
> >  		.suspend	= genphy_c45_pma_suspend,
> >  		.resume		= rtl822x_resume,
> > -		.read_page	= rtl821x_read_page,
> > -		.write_page	= rtl821x_write_page,
> >  		.read_mmd	= rtlgen_read_mmd,
> >  		.write_mmd	= rtlgen_write_mmd,
> >  	}, {
> > @@ -987,8 +983,6 @@ static struct phy_driver realtek_drvs[] = {
> >  		.read_status    = rtl822x_read_status,
> >  		.suspend	= genphy_c45_pma_suspend,
> >  		.resume		= rtl822x_resume,
> > -		.read_page      = rtl821x_read_page,
> > -		.write_page     = rtl821x_write_page,
> >  		.read_mmd	= rtlgen_read_mmd,
> >  		.write_mmd	= rtlgen_write_mmd,
> >  	}, {
> > @@ -999,8 +993,6 @@ static struct phy_driver realtek_drvs[] = {
> >  		.read_status    = rtl822x_read_status,
> >  		.suspend	= genphy_c45_pma_suspend,
> >  		.resume		= rtl822x_resume,
> > -		.read_page      = rtl821x_read_page,
> > -		.write_page     = rtl821x_write_page,
> >  		.read_mmd	= rtlgen_read_mmd,
> >  		.write_mmd	= rtlgen_write_mmd,
> >  	}, {
> > @@ -1011,8 +1003,6 @@ static struct phy_driver realtek_drvs[] = {
> >  		.read_status    = rtl822x_read_status,
> >  		.suspend	= genphy_c45_pma_suspend,
> >  		.resume		= rtl822x_resume,
> > -		.read_page      = rtl821x_read_page,
> > -		.write_page     = rtl821x_write_page,
> >  		.read_mmd	= rtlgen_read_mmd,
> >  		.write_mmd	= rtlgen_write_mmd,
> >  	}, {
> > @@ -1023,8 +1013,6 @@ static struct phy_driver realtek_drvs[] = {
> >  		.read_status    = rtl822x_read_status,
> >  		.suspend	= genphy_c45_pma_suspend,
> >  		.resume		= rtl822x_resume,
> > -		.read_page      = rtl821x_read_page,
> > -		.write_page     = rtl821x_write_page,
> >  		.read_mmd	= rtlgen_read_mmd,
> >  		.write_mmd	= rtlgen_write_mmd,
> >  	}, {  
> 
> Dropping the read_page/write_page hooks will be problematic,
> because they are used by the PHY initialization in e.g.
> rtl8125a_2_hw_phy_config().

I see. 

Maybe it would be simpler to just remove it from this series.

Looking at all instances of paged access in r8169, most of them seem to
access the vendor 2 MMD registers. Also the person from Realtek says
that MMD registers are available also on 1gbps PHYs.

Looking at PHY specs for RTL8211 series, all of them (as old as 2009)
seem to document MMD access.

So I think we can safely add .read_mmd() and .write_mmd() methods to
all the PHYs in realtek.c that may be used by r8169, and then we can
change the relevant phy_read/write/modify_paged calls into
phy_read/write/modify_mmd in r8169 according to the formula.

(The relevant accesses being those where page is set to value >= 0xa00.)

What do you think?

Marek

Re: [PATCH net-next 00/15] Realtek RTL822x PHY rework to c45 and SerDes interface switching

[Heiner Kallweit]

On 20.12.2023 17:25, Marek Behún wrote:
> On Wed, 20 Dec 2023 17:20:07 +0100
> Heiner Kallweit <hkallweit1@gmail.com> wrote:
> 
>> On 20.12.2023 16:55, Marek Behún wrote:
>>> Hi,
>>>
>>> this series reworks the realtek PHY driver's support for rtl822x
>>> 2.5G transceivers:
>>>
>>> - First I change the driver so that the high level driver methods
>>>   only use clause 45 register accesses (the only clause 22 accesses
>>>   are left when accessing c45 registers indirectly, if the MDIO bus
>>>   does not support clause 45 accesses).
>>>   The driver starts using the genphy_c45_* methods.
>>>
>>>   At this point the driver is ready to be used on a MDIO bus capable
>>>   of only clause 45 accesses, but will still work on clause 22 only
>>>   MDIO bus.
>>>
>>> - I then add support for SerDes mode switching between 2500base-x
>>>   and sgmii, based on autonegotiated copper speed.
>>>
>>> All this is done so that we can support another 2.5G copper SFP
>>> module, which is enabled by the last patch.
>>>   
>>
>> Has been verified that the RTL8125-integrated PHY's still work
>> properly with this patch set?
>>
> 
> Hi Heiner,
> 
> no, I wanted to send you an email to test this. I do not have the
> controllers with integrates PHYs.
> 
> Can you test this?
> 
> Also do you have a controller where the rtlgen driver is used but it
> only supports 1gbps ? I.e. where the PHY ID is RTL_GENERIC_PHYID
> (0x001cc800).
> 
> I am asking because I am told that it also is clause 45, so the drivers
> can potentially be merged completely (the rtl822x_ functions can be
> merged with rtlgen_ functions and everything rewritten to clause 45,
> and gentphy_c45_ functions can be used).
> 
At least on RTL8168h indirect MMD reads return 0 always.
IIRC this was the reason why the rtlgen functions use the vendor-specific
registers.

> Marek

Re: [PATCH net-next 00/15] Realtek RTL822x PHY rework to c45 and SerDes interface switching

[Marek Behún]

On Sat, 23 Dec 2023 20:09:33 +0100
Heiner Kallweit <hkallweit1@gmail.com> wrote:

> On 20.12.2023 17:25, Marek Behún wrote:
> > On Wed, 20 Dec 2023 17:20:07 +0100
> > Heiner Kallweit <hkallweit1@gmail.com> wrote:
> >   
> >> On 20.12.2023 16:55, Marek Behún wrote:  
> >>> Hi,
> >>>
> >>> this series reworks the realtek PHY driver's support for rtl822x
> >>> 2.5G transceivers:
> >>>
> >>> - First I change the driver so that the high level driver methods
> >>>   only use clause 45 register accesses (the only clause 22 accesses
> >>>   are left when accessing c45 registers indirectly, if the MDIO bus
> >>>   does not support clause 45 accesses).
> >>>   The driver starts using the genphy_c45_* methods.
> >>>
> >>>   At this point the driver is ready to be used on a MDIO bus capable
> >>>   of only clause 45 accesses, but will still work on clause 22 only
> >>>   MDIO bus.
> >>>
> >>> - I then add support for SerDes mode switching between 2500base-x
> >>>   and sgmii, based on autonegotiated copper speed.
> >>>
> >>> All this is done so that we can support another 2.5G copper SFP
> >>> module, which is enabled by the last patch.
> >>>     
> >>
> >> Has been verified that the RTL8125-integrated PHY's still work
> >> properly with this patch set?
> >>  
> > 
> > Hi Heiner,
> > 
> > no, I wanted to send you an email to test this. I do not have the
> > controllers with integrates PHYs.
> > 
> > Can you test this?
> > 
> > Also do you have a controller where the rtlgen driver is used but it
> > only supports 1gbps ? I.e. where the PHY ID is RTL_GENERIC_PHYID
> > (0x001cc800).
> > 
> > I am asking because I am told that it also is clause 45, so the drivers
> > can potentially be merged completely (the rtl822x_ functions can be
> > merged with rtlgen_ functions and everything rewritten to clause 45,
> > and gentphy_c45_ functions can be used).
> >   
> At least on RTL8168h indirect MMD reads return 0 always.
> IIRC this was the reason why the rtlgen functions use the vendor-specific
> registers.

Looking at the code in r8169_phy_config.c, I see function
  rtl8168h_config_eee_phy()
with three paged writes to vendor registers, but the writes do not access
the same registers as the .read_mmd() methods for the PCS_EEE / AN_EEE registers
in realtek.c PHY driver.

It seems for now it would be best to keep the methods for paged
accesses.

Could you test the patchset without the patch that removes the paged
access methods?

The rewrite of the read_mmd / write_mmd methods should not cause
problems. I am told by the realtek contact you gave me that:

  If FE PHY supports EEE, then it will support MMD register and it will
  also support use internal registers to access theses MMD registers.

Marek

Re: [PATCH net-next 00/15] Realtek RTL822x PHY rework to c45 and SerDes interface switching

[Heiner Kallweit]

On 25.12.2023 11:28, Marek Behún wrote:
> On Sat, 23 Dec 2023 20:09:33 +0100
> Heiner Kallweit <hkallweit1@gmail.com> wrote:
> 
>> On 20.12.2023 17:25, Marek Behún wrote:
>>> On Wed, 20 Dec 2023 17:20:07 +0100
>>> Heiner Kallweit <hkallweit1@gmail.com> wrote:
>>>   
>>>> On 20.12.2023 16:55, Marek Behún wrote:  
>>>>> Hi,
>>>>>
>>>>> this series reworks the realtek PHY driver's support for rtl822x
>>>>> 2.5G transceivers:
>>>>>
>>>>> - First I change the driver so that the high level driver methods
>>>>>   only use clause 45 register accesses (the only clause 22 accesses
>>>>>   are left when accessing c45 registers indirectly, if the MDIO bus
>>>>>   does not support clause 45 accesses).
>>>>>   The driver starts using the genphy_c45_* methods.
>>>>>
>>>>>   At this point the driver is ready to be used on a MDIO bus capable
>>>>>   of only clause 45 accesses, but will still work on clause 22 only
>>>>>   MDIO bus.
>>>>>
>>>>> - I then add support for SerDes mode switching between 2500base-x
>>>>>   and sgmii, based on autonegotiated copper speed.
>>>>>
>>>>> All this is done so that we can support another 2.5G copper SFP
>>>>> module, which is enabled by the last patch.
>>>>>     
>>>>
>>>> Has been verified that the RTL8125-integrated PHY's still work
>>>> properly with this patch set?
>>>>  
>>>
>>> Hi Heiner,
>>>
>>> no, I wanted to send you an email to test this. I do not have the
>>> controllers with integrates PHYs.
>>>
>>> Can you test this?
>>>
>>> Also do you have a controller where the rtlgen driver is used but it
>>> only supports 1gbps ? I.e. where the PHY ID is RTL_GENERIC_PHYID
>>> (0x001cc800).
>>>
>>> I am asking because I am told that it also is clause 45, so the drivers
>>> can potentially be merged completely (the rtl822x_ functions can be
>>> merged with rtlgen_ functions and everything rewritten to clause 45,
>>> and gentphy_c45_ functions can be used).
>>>   
>> At least on RTL8168h indirect MMD reads return 0 always.
>> IIRC this was the reason why the rtlgen functions use the vendor-specific
>> registers.
> 
> Looking at the code in r8169_phy_config.c, I see function
>   rtl8168h_config_eee_phy()
> with three paged writes to vendor registers, but the writes do not access
> the same registers as the .read_mmd() methods for the PCS_EEE / AN_EEE registers
> in realtek.c PHY driver.
> 
That's some other undocumented EEE-related magic copied from the vendor driver.

> It seems for now it would be best to keep the methods for paged
> accesses.
> 
> Could you test the patchset without the patch that removes the paged
> access methods?
> 
> The rewrite of the read_mmd / write_mmd methods should not cause
> problems. I am told by the realtek contact you gave me that:
> 

I tested on RTL8125A and RTL8125B, and on both indirect MMD reads return 0.
I tested with reading MDIO_MMD_PCS / MDIO_PCS_EEE_ABLE. Reading this register
should return 6. So it seems indirect MMD access was somehow and for whatever
reason disabled by Realtek for the RTL8125-internal PHY's (provided that
indirect C22 MMD access is supported by the standalone versions).

Note:
Internal PHY of RTL8125A has PHY ID 0x001cc800 (RTL8226 2.5Gbps PHY)
Internal PHY of RTL8125B has PHY ID 0x001cc840 (RTL8226B_RTL8221B 2.5Gbps PHY)

Consequence is that we can't replace reading the vendor-specific registers
with standard MMD reads.

>   If FE PHY supports EEE, then it will support MMD register and it will
>   also support use internal registers to access theses MMD registers.
> 
> Marek

Heiner

Re: [PATCH net-next 05/15] net: mdio: add 2.5g and 5g related PMA speed constants

[Russell King (Oracle)]

On Wed, Dec 20, 2023 at 04:55:08PM +0100, Marek Behún wrote:
> Add constants indicating 2.5g and 5g ability in the MMD PMA speed
> register.
> 
> Signed-off-by: Marek Behún <kabel@kernel.org>

Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>

Thanks!

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

Re: [PATCH net-next 06/15] net: phy: realtek: use generic MDIO constants

[Russell King (Oracle)]

On Wed, Dec 20, 2023 at 04:55:09PM +0100, Marek Behún wrote:
> Drop the ad-hoc MDIO constants used in the driver and use generic
> constants instead.
> 
> Signed-off-by: Marek Behún <kabel@kernel.org>

Great, all for using our generic constants!

Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>

Thanks!

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

Re: [PATCH net-next 01/15] net: phy: fail early with error code if indirect MMD access fails

[Russell King (Oracle)]

On Wed, Dec 20, 2023 at 04:55:04PM +0100, Marek Behún wrote:
> Check return values of __mdiobus_write() in mmd_phy_indirect() and
> return value of mmd_phy_indirect() itself.
> 
> Signed-off-by: Marek Behún <kabel@kernel.org>

I think the reason it was done this way is based on the reasoning that
if the bus has failed then the last read/write will also fail. However,
if we had a spurious failure (and they _do_ happen) then one of the
previous writes e.g. to the indirect address register could have failed
and we could end up corrupting a different register.

Therefore, this makes sense (and some of my commentry should probably
be in the patch description to explain why the change is being made.)

Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>

Thanks!

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

Re: [PATCH net-next 02/15] net: phy: export indirect MMD register accessors

[Russell King (Oracle)]

On Wed, Dec 20, 2023 at 04:55:05PM +0100, Marek Behún wrote:
> Export mmd_phy_read_indirect() and mmd_phy_write_indirect(), the
> indirect MMD accessors, so that the functions can be used from the
> .read_mmd / .write_mmd phy_driver methods.
> 
> Add a __ prefix to these functions.
> 
> Signed-off-by: Marek Behún <kabel@kernel.org>

Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>

Thanks!

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

Re: [PATCH net-next 03/15] net: phy: realtek: rework MMD register access methods

[Russell King (Oracle)]

On Wed, Dec 20, 2023 at 04:55:06PM +0100, Marek Behún wrote:
> The .read_mmd() and .write_mmd() methods for rtlgen and rtl822x
> currently allow access to only 6 MMD registers, via a vendor specific
> mechanism (a paged read / write).
> 
> The PHY specification explains that MMD registers for MMDs 1 to 30 can
> be accessed via the clause 22 indirect mechanism through registers 13
> and 14, but this is not possible for MMD 31.
> 
> A Realtek contact explained that MMD 31 registers can be accessed by
> setting clause 22 page register (register 31):
>   page = mmd_reg >> 4
>   reg = 0x10 | ((mmd_reg & 0xf) >> 1)
> 
> This mechanism is currently used in the driver. For example the
> .read_mmd() method accesses the PCS.EEE_ABLE register by setting page
> to 0xa5c and accessing register 0x12. By the formulas above, this
> corresponds to MMD register 31.a5c4. The Realtek contact confirmed that
> the PCS.EEE_ABLE register (3.0014) is also available via MMD alias
> 31.a5c4, and this is also true for the other registers:
> 
>   register name   address   page.reg  alias
>   PCS.EEE_ABLE    3.0x0014  0xa5c.12  31.0xa5c4
>   PCS.EEE_ABLE2   3.0x0015  0xa6e.16  31.0xa6ec
>   AN.EEE_ADV      7.0x003c  0xa5d.10  31.0xa5d0
>   AN.EEE_LPABLE   7.0x003d  0xa5d.11  31.0xa5d2
>   AN.EEE_ADV2     7.0x003e  0xa6d.12  31.0xa6d4
>   AN.EEE_LPABLE2  7.0x003f  0xa6d.10  31.0xa6d0
> 
> Since the registers are also available at the true MMD addresses where
> they can be accessed via the indirect mechanism (via registers 13 and
> 14) we can rework the code to be more generic and allow access to all
> MMD registers.
> 
> Rework the .read_mmd() and .write_mmd() methods for rtlgen and rtl822x
> PHYs:
> - use direct clause 45 access if the MDIO bus supports it
> - use the indirect access via clause 22 registers 13 and 14 for MMDs
>   1 to 30
> - use the vendor specific method to access MMD 31 registers
> 
> Signed-off-by: Marek Behún <kabel@kernel.org>
> ---

Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>

Thanks!

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

Re: [PATCH net-next 04/15] net: phy: realtek: fill .read_mmd and .write_mmd methods for all rtl822x PHYs

[Russell King (Oracle)]

On Wed, Dec 20, 2023 at 04:55:07PM +0100, Marek Behún wrote:
> Fill in the .read_mmd() and .write_mmd() methods for all rtl822x PHYs,
> so that we can start reimplementing rtl822x driver methods into using
> genphy_c45_* functions.
> 
> Signed-off-by: Marek Behún <kabel@kernel.org>

Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>

Thanks!

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

Re: [PATCH net-next 03/15] net: phy: realtek: rework MMD register access methods

[Heiner Kallweit]

On 02.01.2024 12:16, Russell King (Oracle) wrote:
> On Wed, Dec 20, 2023 at 04:55:06PM +0100, Marek Behún wrote:
>> The .read_mmd() and .write_mmd() methods for rtlgen and rtl822x
>> currently allow access to only 6 MMD registers, via a vendor specific
>> mechanism (a paged read / write).
>>
>> The PHY specification explains that MMD registers for MMDs 1 to 30 can
>> be accessed via the clause 22 indirect mechanism through registers 13
>> and 14, but this is not possible for MMD 31.
>>
>> A Realtek contact explained that MMD 31 registers can be accessed by
>> setting clause 22 page register (register 31):
>>   page = mmd_reg >> 4
>>   reg = 0x10 | ((mmd_reg & 0xf) >> 1)
>>
>> This mechanism is currently used in the driver. For example the
>> .read_mmd() method accesses the PCS.EEE_ABLE register by setting page
>> to 0xa5c and accessing register 0x12. By the formulas above, this
>> corresponds to MMD register 31.a5c4. The Realtek contact confirmed that
>> the PCS.EEE_ABLE register (3.0014) is also available via MMD alias
>> 31.a5c4, and this is also true for the other registers:
>>
>>   register name   address   page.reg  alias
>>   PCS.EEE_ABLE    3.0x0014  0xa5c.12  31.0xa5c4
>>   PCS.EEE_ABLE2   3.0x0015  0xa6e.16  31.0xa6ec
>>   AN.EEE_ADV      7.0x003c  0xa5d.10  31.0xa5d0
>>   AN.EEE_LPABLE   7.0x003d  0xa5d.11  31.0xa5d2
>>   AN.EEE_ADV2     7.0x003e  0xa6d.12  31.0xa6d4
>>   AN.EEE_LPABLE2  7.0x003f  0xa6d.10  31.0xa6d0
>>
>> Since the registers are also available at the true MMD addresses where
>> they can be accessed via the indirect mechanism (via registers 13 and
>> 14) we can rework the code to be more generic and allow access to all
>> MMD registers.
>>
Marek and me had a separate communication about the version of these PHY's
used as internal PHY's on RTL8125 MAC/PHY combination.
Depending on the RTL8125 version the PHY's identify as either RTL8226 or
RTL8226B. Problem is that these internal PHY's are crippled and don't
support the indirect MMD access over c22.
In my tests all indirect MMD reads returned 0.
Therefore this patch has to be reworked.

In order not to break handling of the RTL8125-internal PHY's, we have to
keep the access to the vendor-specific registers. What could be done:
Split the PHY driver for e.g. RTL8226B into one for the RTL8125-internal
version and one for the standalone version (using match_phy_device and
maybe using the MMD read result as differentiating criteria).
Then the one for the standalone version could use core c45 functions.

>> Rework the .read_mmd() and .write_mmd() methods for rtlgen and rtl822x
>> PHYs:
>> - use direct clause 45 access if the MDIO bus supports it
>> - use the indirect access via clause 22 registers 13 and 14 for MMDs
>>   1 to 30
>> - use the vendor specific method to access MMD 31 registers
>>
>> Signed-off-by: Marek Behún <kabel@kernel.org>
>> ---
> 
> Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
> 
> Thanks!
>