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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jeff Kirsher , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [iwl-net v1 2/2] igb: Fix missing time sync events Message-ID: References: <20240217010455.58258-1-vinicius.gomes@intel.com> <20240217010455.58258-3-vinicius.gomes@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240217010455.58258-3-vinicius.gomes@intel.com> On Fri, Feb 16, 2024 at 05:04:54PM -0800, Vinicius Costa Gomes wrote: > Fix "double" clearing of interrupts, which can cause external events > or timestamps to be missed. > > The E1000_TSIRC Time Sync Interrupt Cause register can be cleared in two > ways, by either reading it or by writing '1' into the specific cause > bit. This is documented in section 8.16.1. That is not what the doc says. It says this: Note: Once ICR.Time_Sync is set, the internal value of this register should be cleared by writing 1b to *all* bits or cleared by a read to enable receiving an additional ICR.Time_Sync interrupt. - Intel® Ethernet Controller I210 Datasheet, Revision Number: 3.1, June 2017, page 469 It says *all* bits. This implies that the interrupt sources may be cleared individually. Because the non-acked bits are still pending, the level interrupt should still be active, and the "missing" event will be handled at the next invocation of the handler. > The following flow was used: > 1. read E1000_TSIRC into 'tsicr'; > 2. handle the interrupts present into 'tsirc' and mark them in 'ack'; > 3. write 'ack' into E1000_TSICR; > > As both (1) and (3) will clear the interrupt cause, if an interrupt > happens between (1) and (3) it will be ignored, causing events to be > missed. Are you sure? Does setting ICR.Time_Sync[TXTS] also clear ICR.Time_Sync[RXTS] ? That is what you seem to be saying. Thanks, Richard