Re: [PATCH net-next] net: stmmac: dwmac-qcom-ethqos: Add support for 2.5G SGMII

["Russell King (Oracle)" <linux@armlinux.org.uk>]

On Mon, Jun 03, 2024 at 04:57:15PM +0530, Sneh Shah wrote:
> On 5/30/2024 1:39 AM, Russell King (Oracle) wrote:
> > From what you're saying:
> > - if using the dwmac1000 core, then for the registers at GMAC_PCS_BASE
> >   (0xc0 offset)...
> > - if using the dwmac4 core, then for registers at GMAC_PCS_BASE
> >   (0xe0 offset)...
> > ... is it true that only the GMAC_AN_CTRL() register is implemented
> > and none of the other registers listed in stmmac_pcs.h?
> > 
> > In terms of interrupts when the link status changes, how do they
> > present? Are they through the GMAC_INT_RGSMIIS interrupt only?
> > What about GMAC_INT_PCS_LINK or GMAC_INT_PCS_ANE? Or in the case
> > of the other core, is it through the PCS_RGSMIIIS_IRQ interrupt
> > only? Similarly, what about PCS_LINK_IRQ or PCS_ANE_IRQ?
> 
> we only have GMAC_AN_CTRL and GMAC_AN_STATUS register.
> There is no separate IRQ line for PCS link or autoneg. 
> It is notified via MAC interrupt line only.

From the sound of it, this is just the standard PCS that everyone else
would use in DW ETHQoS, with the exception that you can run it at 2.5G
without inband signalling.

Thanks for clarifying that. I think we can just use the phylink PCS
that I'm proposing for your case, with the exception of also adding
support for 2.5G speeds, which I will need to sort out.

So, I think I need to get my patch set that query the inband
capabilities of the PCS and PHY into net-next before we can move
forward with 2.5G speeds here.

Thanks.

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