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From: "Russell King (Oracle)" <linux@armlinux.org.uk>
To: Sky Huang <SkyLake.Huang@mediatek.com>
Cc: Andrew Lunn <andrew@lunn.ch>,
	Heiner Kallweit <hkallweit1@gmail.com>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Daniel Golle <daniel@makrotopia.org>,
	Qingfang Deng <dqfext@gmail.com>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	AngeloGioacchino Del Regno
	<angelogioacchino.delregno@collabora.com>,
	linux-kernel@vger.kernel.org, netdev@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org,
	Steven Liu <Steven.Liu@mediatek.com>
Subject: Re: [PATCH net-next v5 5/5] net: phy: add driver for built-in 2.5G ethernet PHY on MT7988
Date: Thu, 30 May 2024 11:35:42 +0100	[thread overview]
Message-ID: <ZlhWfua01SCOor80@shell.armlinux.org.uk> (raw)
In-Reply-To: <20240530034844.11176-6-SkyLake.Huang@mediatek.com>

On Thu, May 30, 2024 at 11:48:44AM +0800, Sky Huang wrote:
> +static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev)
> +{
> +	bool changed = false;
> +	u32 adv;
> +	int ret;
> +
> +	/* In fact, if we disable autoneg, we can't link up correctly:
> +	 *  2.5G/1G: Need AN to exchange master/slave information.
> +	 *  100M: Without AN, link starts at half duplex(According to IEEE 802.3-2018),
> +	 *        which this phy doesn't support.
> +	 *   10M: Deprecated in this ethernet phy.
> +	 */
> +	if (phydev->autoneg == AUTONEG_DISABLE)
> +		return -EOPNOTSUPP;

We have another driver (stmmac) where a platform driver is wanting to
put a hack in the ksettings_set() ethtool path to error out on
disabling AN for 1G speeds. This sounds like something that is
applicable to more than one hardware (and I've been wondering whether
it is universally true that 1G copper links and faster all require
AN to function.)

Thus, I'm wondering whether this is something that the core code should
be doing.

> +	/* This phy can't handle collision, and neither can (XFI)MAC it's connected to.
> +	 * Although it can do HDX handshake, it doesn't support CSMA/CD that HDX requires.
> +	 */

What the MAC can and can't do really has little bearing on what link
modes the PHY driver should be providing. It is the responsibility of
the MAC driver to appropriately change what is supported when attaching
to the PHY. If using phylink, this is done by phylink via the MAC driver
telling phylink what it is capable of via mac_capabilities.

> +static int mt798x_2p5ge_phy_get_rate_matching(struct phy_device *phydev,
> +					      phy_interface_t iface)
> +{
> +	if (iface == PHY_INTERFACE_MODE_XGMII)
> +		return RATE_MATCH_PAUSE;

You mention above XFI...

XFI is 10GBASE-R protocol to XFP module electrical standards.
SFI is 10GBASE-R protocol to SFP+ module electrical standards.

phy_interface_t is interested in the protocol. So, given that you
mention XFI, why doesn't this test for PHY_INTERFACE_MODE_10GBASER?

> +static int mt798x_2p5ge_phy_probe(struct phy_device *phydev)
> +{
> +	struct mtk_i2p5ge_phy_priv *priv;
> +
> +	priv = devm_kzalloc(&phydev->mdio.dev,
> +			    sizeof(struct mtk_i2p5ge_phy_priv), GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +
> +	switch (phydev->drv->phy_id) {
> +	case MTK_2P5GPHY_ID_MT7988:
> +		/* The original hardware only sets MDIO_DEVS_PMAPMD */
> +		phydev->c45_ids.mmds_present |= (MDIO_DEVS_PCS | MDIO_DEVS_AN |
> +						 MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2);

No need for parens on the RHS. The RHS is an expression in its own
right, and there's no point in putting parens around the expression
to turn it into another expression!

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

  reply	other threads:[~2024-05-30 10:35 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-30  3:48 [PATCH net-next v5 0/5] net: phy: mediatek: Introduce mtk-phy-lib and add 2.5Gphy support Sky Huang
2024-05-30  3:48 ` [PATCH net-next v5 1/5] net: phy: mediatek: Re-organize MediaTek ethernet phy drivers Sky Huang
2024-05-30  3:48 ` [PATCH net-next v5 2/5] net: phy: mediatek: Move LED and read/write page helper functions into mtk phy lib Sky Huang
2024-05-30  3:48 ` [PATCH net-next v5 3/5] net: phy: mediatek: Add token ring access helper functions in mtk-phy-lib Sky Huang
2024-05-30  3:48 ` [PATCH net-next v5 4/5] net: phy: mediatek: Extend 1G TX/RX link pulse time Sky Huang
2024-05-30 10:23   ` Russell King (Oracle)
2024-05-30 16:01     ` SkyLake Huang (黃啟澤)
2024-05-30 16:10       ` Russell King (Oracle)
2024-06-03  3:15         ` SkyLake Huang (黃啟澤)
2024-06-03  8:06           ` Russell King (Oracle)
2024-06-03 11:51             ` SkyLake Huang (黃啟澤)
2024-05-30  3:48 ` [PATCH net-next v5 5/5] net: phy: add driver for built-in 2.5G ethernet PHY on MT7988 Sky Huang
2024-05-30 10:35   ` Russell King (Oracle) [this message]
2024-05-30 16:25     ` SkyLake Huang (黃啟澤)
2024-05-30 16:55       ` Russell King (Oracle)
2024-06-03  7:19         ` SkyLake Huang (黃啟澤)
2024-05-31  1:00   ` kernel test robot
2024-06-01 12:51   ` Simon Horman
2024-06-03  7:41     ` SkyLake Huang (黃啟澤)

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