[PATCH net-next 0/2] Add support for AXI 2.5G ethernet

[PATCH net-next 0/2] Add support for AXI 2.5G ethernet

[Suraj Gupta]

Add AXI 2.5G ethernet support which is an incremental speed upgrade
of AXI 1G of AXI 1G/2.5G IP.

Suraj Gupta (2):
  dt-bindings: net: xlnx,axi-ethernet: Add bindings for AXI 2.5G MAC
  net: axienet: Add support for AXI 2.5G MAC of AXI 1G/2.5G ethernet IP

 .../bindings/net/xlnx,axi-ethernet.yaml       | 44 +++++++++++++++++--
 drivers/net/ethernet/xilinx/xilinx_axienet.h  |  4 +-
 .../net/ethernet/xilinx/xilinx_axienet_main.c | 24 +++++++---
 3 files changed, 62 insertions(+), 10 deletions(-)

-- 
2.25.1

[PATCH net-next 1/2] dt-bindings: net: xlnx,axi-ethernet: Add bindings for AXI 2.5G MAC

[Suraj Gupta]

AXI 1G/2.5G Ethernet subsystem supports 1G and 2.5G speeds. "max-speed"
property is used to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
max-speed is made a required property, and it breaks DT ABI but driver
implementation ensures backward compatibility and assumes 1G when this
property is absent.
Modify existing bindings description for 2.5G MAC.

Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
---
 .../bindings/net/xlnx,axi-ethernet.yaml       | 44 +++++++++++++++++--
 1 file changed, 40 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
index fb02e579463c..69e84e2e2b63 100644
--- a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
+++ b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
@@ -9,10 +9,12 @@ title: AXI 1G/2.5G Ethernet Subsystem
 description: |
   Also called  AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
   provides connectivity to an external ethernet PHY supporting different
-  interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
+  interfaces: MII, GMII, RGMII, SGMII, 1000BaseX and 2500BaseX. It also includes two
   segments of memory for buffering TX and RX, as well as the capability of
   offloading TX/RX checksum calculation off the processor.
 
+  AXI 2.5G MAC is incremental speed upgrade of AXI 1G and supports 2.5G speed.
+
   Management configuration is done through the AXI interface, while payload is
   sent and received through means of an AXI DMA controller. This driver
   includes the DMA driver code, so this driver is incompatible with AXI DMA
@@ -62,6 +64,7 @@ properties:
       - rgmii
       - sgmii
       - 1000base-x
+      - 2500base-x
 
   xlnx,phy-type:
     description:
@@ -118,9 +121,9 @@ properties:
     type: object
 
   pcs-handle:
-    description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
-      modes, where "pcs-handle" should be used to point to the PCS/PMA PHY,
-      and "phy-handle" should point to an external PHY if exists.
+    description: Phandle to the internal PCS/PMA PHY in SGMII or 1000base-x/
+      2500base-x modes, where "pcs-handle" should be used to point to the
+      PCS/PMA PHY, and "phy-handle" should point to an external PHY if exists.
     maxItems: 1
 
   dmas:
@@ -137,12 +140,17 @@ properties:
     minItems: 2
     maxItems: 32
 
+  max-speed:
+    description:
+      Indicates max MAC rate. 1G and 2.5G MACs of AXI 1G/2.5G IP are distinguished using it.
+
 required:
   - compatible
   - interrupts
   - reg
   - xlnx,rxmem
   - phy-handle
+  - max-speed
 
 allOf:
   - $ref: /schemas/net/ethernet-controller.yaml#
@@ -164,6 +172,7 @@ examples:
         xlnx,rxmem = <0x800>;
         xlnx,txcsum = <0x2>;
         phy-handle = <&phy0>;
+        max-speed = <1000>;
 
         mdio {
             #address-cells = <1>;
@@ -188,6 +197,7 @@ examples:
         xlnx,txcsum = <0x2>;
         phy-handle = <&phy1>;
         axistream-connected = <&dma>;
+        max-speed = <1000>;
 
         mdio {
             #address-cells = <1>;
@@ -198,3 +208,29 @@ examples:
             };
         };
     };
+
+# AXI 2.5G MAC
+  - |
+    axi_ethernet_eth2: ethernet@a4000000 {
+        compatible = "xlnx,axi-ethernet-1.00.a";
+        interrupts = <0>;
+        clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
+        clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>;
+        phy-mode = "2500base-x";
+        reg = <0x40000000 0x40000>;
+        xlnx,rxcsum = <0x2>;
+        xlnx,rxmem = <0x800>;
+        xlnx,txcsum = <0x2>;
+        phy-handle = <&phy1>;
+        axistream-connected = <&dma>;
+        max-speed = <2500>;
+
+        mdio {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            phy2: ethernet-phy@1 {
+                device_type = "ethernet-phy";
+                reg = <1>;
+            };
+        };
+    };
-- 
2.25.1

Re: [PATCH net-next 1/2] dt-bindings: net: xlnx,axi-ethernet: Add bindings for AXI 2.5G MAC

[Sean Anderson]

On 11/18/24 03:18, Suraj Gupta wrote:
> AXI 1G/2.5G Ethernet subsystem supports 1G and 2.5G speeds. "max-speed"
> property is used to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
> max-speed is made a required property, and it breaks DT ABI but driver
> implementation ensures backward compatibility and assumes 1G when this
> property is absent.
> Modify existing bindings description for 2.5G MAC.
> 
> Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
> ---
>  .../bindings/net/xlnx,axi-ethernet.yaml       | 44 +++++++++++++++++--
>  1 file changed, 40 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
> index fb02e579463c..69e84e2e2b63 100644
> --- a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
> +++ b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
> @@ -9,10 +9,12 @@ title: AXI 1G/2.5G Ethernet Subsystem
>  description: |
>    Also called  AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
>    provides connectivity to an external ethernet PHY supporting different
> -  interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
> +  interfaces: MII, GMII, RGMII, SGMII, 1000BaseX and 2500BaseX. It also includes two
>    segments of memory for buffering TX and RX, as well as the capability of
>    offloading TX/RX checksum calculation off the processor.
>  
> +  AXI 2.5G MAC is incremental speed upgrade of AXI 1G and supports 2.5G speed.
> +
>    Management configuration is done through the AXI interface, while payload is
>    sent and received through means of an AXI DMA controller. This driver
>    includes the DMA driver code, so this driver is incompatible with AXI DMA
> @@ -62,6 +64,7 @@ properties:
>        - rgmii
>        - sgmii
>        - 1000base-x
> +      - 2500base-x
>  
>    xlnx,phy-type:
>      description:
> @@ -118,9 +121,9 @@ properties:
>      type: object
>  
>    pcs-handle:
> -    description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
> -      modes, where "pcs-handle" should be used to point to the PCS/PMA PHY,
> -      and "phy-handle" should point to an external PHY if exists.
> +    description: Phandle to the internal PCS/PMA PHY in SGMII or 1000base-x/
> +      2500base-x modes, where "pcs-handle" should be used to point to the
> +      PCS/PMA PHY, and "phy-handle" should point to an external PHY if exists.
>      maxItems: 1
>  
>    dmas:
> @@ -137,12 +140,17 @@ properties:
>      minItems: 2
>      maxItems: 32
>  
> +  max-speed:
> +    description:
> +      Indicates max MAC rate. 1G and 2.5G MACs of AXI 1G/2.5G IP are distinguished using it.
> +

Can't you read this from the TEMAC ability register?

--Sean

>  required:
>    - compatible
>    - interrupts
>    - reg
>    - xlnx,rxmem
>    - phy-handle
> +  - max-speed
>  
>  allOf:
>    - $ref: /schemas/net/ethernet-controller.yaml#
> @@ -164,6 +172,7 @@ examples:
>          xlnx,rxmem = <0x800>;
>          xlnx,txcsum = <0x2>;
>          phy-handle = <&phy0>;
> +        max-speed = <1000>;
>  
>          mdio {
>              #address-cells = <1>;
> @@ -188,6 +197,7 @@ examples:
>          xlnx,txcsum = <0x2>;
>          phy-handle = <&phy1>;
>          axistream-connected = <&dma>;
> +        max-speed = <1000>;
>  
>          mdio {
>              #address-cells = <1>;
> @@ -198,3 +208,29 @@ examples:
>              };
>          };
>      };
> +
> +# AXI 2.5G MAC
> +  - |
> +    axi_ethernet_eth2: ethernet@a4000000 {
> +        compatible = "xlnx,axi-ethernet-1.00.a";
> +        interrupts = <0>;
> +        clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
> +        clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>;
> +        phy-mode = "2500base-x";
> +        reg = <0x40000000 0x40000>;
> +        xlnx,rxcsum = <0x2>;
> +        xlnx,rxmem = <0x800>;
> +        xlnx,txcsum = <0x2>;
> +        phy-handle = <&phy1>;
> +        axistream-connected = <&dma>;
> +        max-speed = <2500>;
> +
> +        mdio {
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +            phy2: ethernet-phy@1 {
> +                device_type = "ethernet-phy";
> +                reg = <1>;
> +            };
> +        };
> +    };

Re: [PATCH net-next 1/2] dt-bindings: net: xlnx,axi-ethernet: Add bindings for AXI 2.5G MAC

[Maxime Chevallier]

Hello,

On Mon, 18 Nov 2024 13:48:21 +0530
Suraj Gupta <suraj.gupta2@amd.com> wrote:

> AXI 1G/2.5G Ethernet subsystem supports 1G and 2.5G speeds. "max-speed"
> property is used to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
> max-speed is made a required property, and it breaks DT ABI but driver
> implementation ensures backward compatibility and assumes 1G when this
> property is absent.
> Modify existing bindings description for 2.5G MAC.

That may be a silly question, but as this is another version of the IP
that behaves differently than the 1G version, could you use instead a
dedicated compatible string for the 2.5G variant ?

As the current one is :

compatible = "xlnx,axi-ethernet-1.00.a";

it seems to already contain some version information.

But I might also be missing something :)

Best regards,

Maxime

Re: [PATCH net-next 1/2] dt-bindings: net: xlnx,axi-ethernet: Add bindings for AXI 2.5G MAC

[Sean Anderson]

On 11/18/24 10:54, Maxime Chevallier wrote:
> Hello,
> 
> On Mon, 18 Nov 2024 13:48:21 +0530
> Suraj Gupta <suraj.gupta2@amd.com> wrote:
> 
>> AXI 1G/2.5G Ethernet subsystem supports 1G and 2.5G speeds. "max-speed"
>> property is used to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
>> max-speed is made a required property, and it breaks DT ABI but driver
>> implementation ensures backward compatibility and assumes 1G when this
>> property is absent.
>> Modify existing bindings description for 2.5G MAC.
> 
> That may be a silly question, but as this is another version of the IP
> that behaves differently than the 1G version, could you use instead a
> dedicated compatible string for the 2.5G variant ?
> 
> As the current one is :
> 
> compatible = "xlnx,axi-ethernet-1.00.a";
> 
> it seems to already contain some version information.
> 
> But I might also be missing something :)

As it happens, this is not another version of the same IP but a
different configuration. It's just that no one has bothered to add 2.5G
support yet.

And to my understanding, the device tree should not contain any info
that can be reliably detected from the hardware.

--Sean

Re: [PATCH net-next 1/2] dt-bindings: net: xlnx,axi-ethernet: Add bindings for AXI 2.5G MAC

[Andrew Lunn]

On Mon, Nov 18, 2024 at 10:57:45AM -0500, Sean Anderson wrote:
> On 11/18/24 10:54, Maxime Chevallier wrote:
> > Hello,
> > 
> > On Mon, 18 Nov 2024 13:48:21 +0530
> > Suraj Gupta <suraj.gupta2@amd.com> wrote:
> > 
> >> AXI 1G/2.5G Ethernet subsystem supports 1G and 2.5G speeds. "max-speed"
> >> property is used to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
> >> max-speed is made a required property, and it breaks DT ABI but driver
> >> implementation ensures backward compatibility and assumes 1G when this
> >> property is absent.
> >> Modify existing bindings description for 2.5G MAC.
> > 
> > That may be a silly question, but as this is another version of the IP
> > that behaves differently than the 1G version, could you use instead a
> > dedicated compatible string for the 2.5G variant ?
> > 
> > As the current one is :
> > 
> > compatible = "xlnx,axi-ethernet-1.00.a";
> > 
> > it seems to already contain some version information.
> > 
> > But I might also be missing something :)
> 
> As it happens, this is not another version of the same IP but a
> different configuration. It's just that no one has bothered to add 2.5G
> support yet.

Do you mean 2.5G is a synthesis option? Or are you saying it has
always been able to do 2.5G, but nobody has added the needed code?

This is a pretty unusual use of max-speed, so i would like to fully
understand why it is being used before allowing it.

	Andrew

RE: [PATCH net-next 1/2] dt-bindings: net: xlnx,axi-ethernet: Add bindings for AXI 2.5G MAC

[Gupta, Suraj]

> -----Original Message-----
> From: Andrew Lunn <andrew@lunn.ch>
> Sent: Tuesday, November 19, 2024 7:09 AM
> To: Sean Anderson <sean.anderson@linux.dev>
> Cc: Maxime Chevallier <maxime.chevallier@bootlin.com>; Gupta, Suraj
> <Suraj.Gupta2@amd.com>; andrew+netdev@lunn.ch; davem@davemloft.net;
> edumazet@google.com; kuba@kernel.org; pabeni@redhat.com; Simek, Michal
> <michal.simek@amd.com>; Pandey, Radhey Shyam
> <radhey.shyam.pandey@amd.com>; horms@kernel.org; netdev@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; git (AMD-Xilinx)
> <git@amd.com>; Katakam, Harini <harini.katakam@amd.com>
> Subject: Re: [PATCH net-next 1/2] dt-bindings: net: xlnx,axi-ethernet: Add bindings
> for AXI 2.5G MAC
> 
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
> 
> 
> On Mon, Nov 18, 2024 at 10:57:45AM -0500, Sean Anderson wrote:
> > On 11/18/24 10:54, Maxime Chevallier wrote:
> > > Hello,
> > >
> > > On Mon, 18 Nov 2024 13:48:21 +0530
> > > Suraj Gupta <suraj.gupta2@amd.com> wrote:
> > >
> > >> AXI 1G/2.5G Ethernet subsystem supports 1G and 2.5G speeds. "max-speed"
> > >> property is used to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
> > >> max-speed is made a required property, and it breaks DT ABI but
> > >> driver implementation ensures backward compatibility and assumes 1G
> > >> when this property is absent.
> > >> Modify existing bindings description for 2.5G MAC.
> > >
> > > That may be a silly question, but as this is another version of the
> > > IP that behaves differently than the 1G version, could you use
> > > instead a dedicated compatible string for the 2.5G variant ?
> > >
> > > As the current one is :
> > >
> > > compatible = "xlnx,axi-ethernet-1.00.a";
> > >
> > > it seems to already contain some version information.
> > >
> > > But I might also be missing something :)
> >
> > As it happens, this is not another version of the same IP but a
> > different configuration. It's just that no one has bothered to add
> > 2.5G support yet.
> 
> Do you mean 2.5G is a synthesis option? Or are you saying it has always been able
> to do 2.5G, but nobody has added the needed code?
> 
> This is a pretty unusual use of max-speed, so i would like to fully understand why it
> is being used before allowing it.
> 
>         Andrew

2.5G support was already there in hardware, driver is getting upstream now. 1G or 2.5G configuration needs to be selected before synthesis. In 2.5G configuration it supports only 2.5G speed.
I'm exploring registers to get 1G / 2.5G selections information instead of using max-speed. Will send next series soon.

Just for my understanding, could you please share the use of max-speed DT property if possible?

Re: [PATCH net-next 1/2] dt-bindings: net: xlnx,axi-ethernet: Add bindings for AXI 2.5G MAC

[Andrew Lunn]

> > Do you mean 2.5G is a synthesis option? Or are you saying it has always been able
> > to do 2.5G, but nobody has added the needed code?
> > 
> > This is a pretty unusual use of max-speed, so i would like to fully understand why it
> > is being used before allowing it.
> > 
> >         Andrew
> 

> 2.5G support was already there in hardware, driver is getting
> upstream now. 1G or 2.5G configuration needs to be selected before
> synthesis. In 2.5G configuration it supports only 2.5G speed.

So when the PCS is fixed to 2.5G, are you planning on using rate
adaptation to support lower speeds? There are a few systems doing
this, mostly by using pause frames between the PHY and the MAC.

> I'm exploring registers to get 1G / 2.5G selections information
> instead of using max-speed. Will send next series soon.

That would be best. The PCS might itself report its
capabilities. Sometimes there is the equivalent of the BMSR.

> Just for my understanding, could you please share the use of
> max-speed DT property if possible?

It is generally used to remove higher speed operation because they are
broken for a particular board. It should be considered a board
property, not a SoC property.

	Andrew

Re: [PATCH net-next 1/2] dt-bindings: net: xlnx,axi-ethernet: Add bindings for AXI 2.5G MAC

[Krzysztof Kozlowski]

On 18/11/2024 09:18, Suraj Gupta wrote:
> AXI 1G/2.5G Ethernet subsystem supports 1G and 2.5G speeds. "max-speed"
> property is used to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
> max-speed is made a required property, and it breaks DT ABI but driver
> implementation ensures backward compatibility and assumes 1G when this
> property is absent.
> Modify existing bindings description for 2.5G MAC.
> 
> Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>

Please start using b4. This thread is a mess.

Do not attach (thread) your patchsets to some other threads (unrelated
or older versions). This buries them deep in the mailbox and might
interfere with applying entire sets.

<form letter>
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC. It might happen, that command when run on an older
kernel, gives you outdated entries. Therefore please be sure you base
your patches on recent Linux kernel.

Tools like b4 or scripts/get_maintainer.pl provide you proper list of
people, so fix your workflow. Tools might also fail if you work on some
ancient tree (don't, instead use mainline) or work on fork of kernel
(don't, instead use mainline). Just use b4 and everything should be
fine, although remember about `b4 prep --auto-to-cc` if you added new
patches to the patchset.

You missed at least devicetree list (maybe more), so this won't be
tested by automated tooling. Performing review on untested code might be
a waste of time.

Please kindly resend and include all necessary To/Cc entries.
</form letter>

Best regards,
Krzysztof

[PATCH net-next 2/2] net: axienet: Add support for AXI 2.5G MAC

[Suraj Gupta]

Add AXI 2.5G MAC support, which is an incremental speed upgrade
of AXI 1G MAC and supports 2.5G speed only. "max-speed" DT property
is used in driver to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
If max-speed property is missing, 1G is assumed to support backward
compatibility.

Co-developed-by: Harini Katakam <harini.katakam@amd.com>
Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
---
 drivers/net/ethernet/xilinx/xilinx_axienet.h  |  4 +++-
 .../net/ethernet/xilinx/xilinx_axienet_main.c | 24 +++++++++++++++----
 2 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h
index d64b8abcf018..ebad1c147aa2 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet.h
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h
@@ -274,7 +274,7 @@
 #define XAE_EMMC_RX16BIT	0x01000000 /* 16 bit Rx client enable */
 #define XAE_EMMC_LINKSPD_10	0x00000000 /* Link Speed mask for 10 Mbit */
 #define XAE_EMMC_LINKSPD_100	0x40000000 /* Link Speed mask for 100 Mbit */
-#define XAE_EMMC_LINKSPD_1000	0x80000000 /* Link Speed mask for 1000 Mbit */
+#define XAE_EMMC_LINKSPD_1000_2500	0x80000000 /* Link Speed mask for 1000 or 2500 Mbit */
 
 /* Bit masks for Axi Ethernet PHYC register */
 #define XAE_PHYC_SGMIILINKSPEED_MASK	0xC0000000 /* SGMII link speed mask*/
@@ -542,6 +542,7 @@ struct skbuf_dma_descriptor {
  * @tx_ring_tail: TX skb ring buffer tail index.
  * @rx_ring_head: RX skb ring buffer head index.
  * @rx_ring_tail: RX skb ring buffer tail index.
+ * @max_speed: Maximum possible MAC speed.
  */
 struct axienet_local {
 	struct net_device *ndev;
@@ -620,6 +621,7 @@ struct axienet_local {
 	int tx_ring_tail;
 	int rx_ring_head;
 	int rx_ring_tail;
+	u32 max_speed;
 };
 
 /**
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index 273ec5f70005..52a3703bd604 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -2388,6 +2388,7 @@ static struct phylink_pcs *axienet_mac_select_pcs(struct phylink_config *config,
 	struct axienet_local *lp = netdev_priv(ndev);
 
 	if (interface == PHY_INTERFACE_MODE_1000BASEX ||
+	    interface == PHY_INTERFACE_MODE_2500BASEX ||
 	    interface ==  PHY_INTERFACE_MODE_SGMII)
 		return &lp->pcs;
 
@@ -2421,8 +2422,9 @@ static void axienet_mac_link_up(struct phylink_config *config,
 	emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
 
 	switch (speed) {
+	case SPEED_2500:
 	case SPEED_1000:
-		emmc_reg |= XAE_EMMC_LINKSPD_1000;
+		emmc_reg |= XAE_EMMC_LINKSPD_1000_2500;
 		break;
 	case SPEED_100:
 		emmc_reg |= XAE_EMMC_LINKSPD_100;
@@ -2432,7 +2434,7 @@ static void axienet_mac_link_up(struct phylink_config *config,
 		break;
 	default:
 		dev_err(&ndev->dev,
-			"Speed other than 10, 100 or 1Gbps is not supported\n");
+			"Speed other than 10, 100, 1Gbps or 2.5Gbps is not supported\n");
 		break;
 	}
 
@@ -2681,6 +2683,12 @@ static int axienet_probe(struct platform_device *pdev)
 	lp->switch_x_sgmii = of_property_read_bool(pdev->dev.of_node,
 						   "xlnx,switch-x-sgmii");
 
+	ret = of_property_read_u32(pdev->dev.of_node, "max-speed", &lp->max_speed);
+	if (ret) {
+		lp->max_speed = SPEED_1000;
+		netdev_warn(ndev, "Please upgrade your device tree to use max-speed\n");
+	}
+
 	/* Start with the proprietary, and broken phy_type */
 	ret = of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &value);
 	if (!ret) {
@@ -2854,7 +2862,8 @@ static int axienet_probe(struct platform_device *pdev)
 			 "error registering MDIO bus: %d\n", ret);
 
 	if (lp->phy_mode == PHY_INTERFACE_MODE_SGMII ||
-	    lp->phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
+	    lp->phy_mode == PHY_INTERFACE_MODE_1000BASEX ||
+	    lp->phy_mode == PHY_INTERFACE_MODE_2500BASEX) {
 		np = of_parse_phandle(pdev->dev.of_node, "pcs-handle", 0);
 		if (!np) {
 			/* Deprecated: Always use "pcs-handle" for pcs_phy.
@@ -2882,8 +2891,13 @@ static int axienet_probe(struct platform_device *pdev)
 
 	lp->phylink_config.dev = &ndev->dev;
 	lp->phylink_config.type = PHYLINK_NETDEV;
-	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |
-		MAC_10FD | MAC_100FD | MAC_1000FD;
+	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
+
+	/* Set MAC capabilities based on MAC type */
+	if (lp->max_speed == SPEED_1000)
+		lp->phylink_config.mac_capabilities |= MAC_10FD | MAC_100FD | MAC_1000FD;
+	else
+		lp->phylink_config.mac_capabilities |= MAC_2500FD;
 
 	__set_bit(lp->phy_mode, lp->phylink_config.supported_interfaces);
 	if (lp->switch_x_sgmii) {
-- 
2.25.1

RE: [PATCH net-next 2/2] net: axienet: Add support for AXI 2.5G MAC

[Pandey, Radhey Shyam]

> -----Original Message-----
> From: Suraj Gupta <suraj.gupta2@amd.com>
> Sent: Monday, November 18, 2024 1:48 PM
> To: andrew+netdev@lunn.ch; davem@davemloft.net; edumazet@google.com;
> kuba@kernel.org; pabeni@redhat.com; Simek, Michal <michal.simek@amd.com>;
> sean.anderson@linux.dev; Pandey, Radhey Shyam
> <radhey.shyam.pandey@amd.com>; horms@kernel.org
> Cc: netdev@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; git (AMD-Xilinx) <git@amd.com>; Katakam, Harini
> <harini.katakam@amd.com>
> Subject: [PATCH net-next 2/2] net: axienet: Add support for AXI 2.5G MAC
> 
> Add AXI 2.5G MAC support, which is an incremental speed upgrade
> of AXI 1G MAC and supports 2.5G speed only. "max-speed" DT property
> is used in driver to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
> If max-speed property is missing, 1G is assumed to support backward
> compatibility.
> 
> Co-developed-by: Harini Katakam <harini.katakam@amd.com>
> Signed-off-by: Harini Katakam <harini.katakam@amd.com>
> Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>

Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Thanks!
> ---
>  drivers/net/ethernet/xilinx/xilinx_axienet.h  |  4 +++-
>  .../net/ethernet/xilinx/xilinx_axienet_main.c | 24 +++++++++++++++----
>  2 files changed, 22 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h
> b/drivers/net/ethernet/xilinx/xilinx_axienet.h
> index d64b8abcf018..ebad1c147aa2 100644
> --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h
> +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h
> @@ -274,7 +274,7 @@
>  #define XAE_EMMC_RX16BIT	0x01000000 /* 16 bit Rx client enable */
>  #define XAE_EMMC_LINKSPD_10	0x00000000 /* Link Speed mask for 10 Mbit */
>  #define XAE_EMMC_LINKSPD_100	0x40000000 /* Link Speed mask for
> 100 Mbit */
> -#define XAE_EMMC_LINKSPD_1000	0x80000000 /* Link Speed mask for
> 1000 Mbit */
> +#define XAE_EMMC_LINKSPD_1000_2500	0x80000000 /* Link Speed
> mask for 1000 or 2500 Mbit */
> 
>  /* Bit masks for Axi Ethernet PHYC register */
>  #define XAE_PHYC_SGMIILINKSPEED_MASK	0xC0000000 /* SGMII link
> speed mask*/
> @@ -542,6 +542,7 @@ struct skbuf_dma_descriptor {
>   * @tx_ring_tail: TX skb ring buffer tail index.
>   * @rx_ring_head: RX skb ring buffer head index.
>   * @rx_ring_tail: RX skb ring buffer tail index.
> + * @max_speed: Maximum possible MAC speed.
>   */
>  struct axienet_local {
>  	struct net_device *ndev;
> @@ -620,6 +621,7 @@ struct axienet_local {
>  	int tx_ring_tail;
>  	int rx_ring_head;
>  	int rx_ring_tail;
> +	u32 max_speed;
>  };
> 
>  /**
> diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> index 273ec5f70005..52a3703bd604 100644
> --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> @@ -2388,6 +2388,7 @@ static struct phylink_pcs *axienet_mac_select_pcs(struct
> phylink_config *config,
>  	struct axienet_local *lp = netdev_priv(ndev);
> 
>  	if (interface == PHY_INTERFACE_MODE_1000BASEX ||
> +	    interface == PHY_INTERFACE_MODE_2500BASEX ||
>  	    interface ==  PHY_INTERFACE_MODE_SGMII)
>  		return &lp->pcs;
> 
> @@ -2421,8 +2422,9 @@ static void axienet_mac_link_up(struct phylink_config
> *config,
>  	emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
> 
>  	switch (speed) {
> +	case SPEED_2500:
>  	case SPEED_1000:
> -		emmc_reg |= XAE_EMMC_LINKSPD_1000;
> +		emmc_reg |= XAE_EMMC_LINKSPD_1000_2500;
>  		break;
>  	case SPEED_100:
>  		emmc_reg |= XAE_EMMC_LINKSPD_100;
> @@ -2432,7 +2434,7 @@ static void axienet_mac_link_up(struct phylink_config
> *config,
>  		break;
>  	default:
>  		dev_err(&ndev->dev,
> -			"Speed other than 10, 100 or 1Gbps is not supported\n");
> +			"Speed other than 10, 100, 1Gbps or 2.5Gbps is not
> supported\n");
>  		break;
>  	}
> 
> @@ -2681,6 +2683,12 @@ static int axienet_probe(struct platform_device *pdev)
>  	lp->switch_x_sgmii = of_property_read_bool(pdev->dev.of_node,
>  						   "xlnx,switch-x-sgmii");
> 
> +	ret = of_property_read_u32(pdev->dev.of_node, "max-speed", &lp-
> >max_speed);
> +	if (ret) {
> +		lp->max_speed = SPEED_1000;
> +		netdev_warn(ndev, "Please upgrade your device tree to use max-
> speed\n");
> +	}
> +
>  	/* Start with the proprietary, and broken phy_type */
>  	ret = of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &value);
>  	if (!ret) {
> @@ -2854,7 +2862,8 @@ static int axienet_probe(struct platform_device *pdev)
>  			 "error registering MDIO bus: %d\n", ret);
> 
>  	if (lp->phy_mode == PHY_INTERFACE_MODE_SGMII ||
> -	    lp->phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
> +	    lp->phy_mode == PHY_INTERFACE_MODE_1000BASEX ||
> +	    lp->phy_mode == PHY_INTERFACE_MODE_2500BASEX) {
>  		np = of_parse_phandle(pdev->dev.of_node, "pcs-handle", 0);
>  		if (!np) {
>  			/* Deprecated: Always use "pcs-handle" for pcs_phy.
> @@ -2882,8 +2891,13 @@ static int axienet_probe(struct platform_device *pdev)
> 
>  	lp->phylink_config.dev = &ndev->dev;
>  	lp->phylink_config.type = PHYLINK_NETDEV;
> -	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE |
> MAC_ASYM_PAUSE |
> -		MAC_10FD | MAC_100FD | MAC_1000FD;
> +	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE |
> MAC_ASYM_PAUSE;
> +
> +	/* Set MAC capabilities based on MAC type */
> +	if (lp->max_speed == SPEED_1000)
> +		lp->phylink_config.mac_capabilities |= MAC_10FD | MAC_100FD |
> MAC_1000FD;
> +	else
> +		lp->phylink_config.mac_capabilities |= MAC_2500FD;
> 
>  	__set_bit(lp->phy_mode, lp->phylink_config.supported_interfaces);
>  	if (lp->switch_x_sgmii) {
> --
> 2.25.1

Re: [PATCH net-next 2/2] net: axienet: Add support for AXI 2.5G MAC

[Russell King (Oracle)]

On Mon, Nov 18, 2024 at 01:48:22PM +0530, Suraj Gupta wrote:
> Add AXI 2.5G MAC support, which is an incremental speed upgrade
> of AXI 1G MAC and supports 2.5G speed only. "max-speed" DT property
> is used in driver to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
> If max-speed property is missing, 1G is assumed to support backward
> compatibility.
> 
> Co-developed-by: Harini Katakam <harini.katakam@amd.com>
> Signed-off-by: Harini Katakam <harini.katakam@amd.com>
> Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
> ---

...

> -	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |
> -		MAC_10FD | MAC_100FD | MAC_1000FD;
> +	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
> +
> +	/* Set MAC capabilities based on MAC type */
> +	if (lp->max_speed == SPEED_1000)
> +		lp->phylink_config.mac_capabilities |= MAC_10FD | MAC_100FD | MAC_1000FD;
> +	else
> +		lp->phylink_config.mac_capabilities |= MAC_2500FD;

The MAC can only operate at (10M, 100M, 1G) _or_ 2.5G ?

Normally, max speeds can be limited using phylink_limit_mac_speed()
which will clear any MAC capabilities for speeds faster than the
speed specified.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

Re: [PATCH net-next 2/2] net: axienet: Add support for AXI 2.5G MAC

[Sean Anderson]

On 11/18/24 10:56, Russell King (Oracle) wrote:
> On Mon, Nov 18, 2024 at 01:48:22PM +0530, Suraj Gupta wrote:
>> Add AXI 2.5G MAC support, which is an incremental speed upgrade
>> of AXI 1G MAC and supports 2.5G speed only. "max-speed" DT property
>> is used in driver to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
>> If max-speed property is missing, 1G is assumed to support backward
>> compatibility.
>> 
>> Co-developed-by: Harini Katakam <harini.katakam@amd.com>
>> Signed-off-by: Harini Katakam <harini.katakam@amd.com>
>> Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
>> ---
> 
> ...
> 
>> -	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |
>> -		MAC_10FD | MAC_100FD | MAC_1000FD;
>> +	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
>> +
>> +	/* Set MAC capabilities based on MAC type */
>> +	if (lp->max_speed == SPEED_1000)
>> +		lp->phylink_config.mac_capabilities |= MAC_10FD | MAC_100FD | MAC_1000FD;
>> +	else
>> +		lp->phylink_config.mac_capabilities |= MAC_2500FD;
> 
> The MAC can only operate at (10M, 100M, 1G) _or_ 2.5G ?

It's a PCS limitation. It either does (1000Base-X and/or SGMII) OR
(2500Base-X). The MAC itself doesn't have this limitation AFAIK.

--Sean

> Normally, max speeds can be limited using phylink_limit_mac_speed()
> which will clear any MAC capabilities for speeds faster than the
> speed specified.
> 

Re: [PATCH net-next 2/2] net: axienet: Add support for AXI 2.5G MAC

[Russell King (Oracle)]

On Mon, Nov 18, 2024 at 11:00:22AM -0500, Sean Anderson wrote:
> On 11/18/24 10:56, Russell King (Oracle) wrote:
> > On Mon, Nov 18, 2024 at 01:48:22PM +0530, Suraj Gupta wrote:
> >> Add AXI 2.5G MAC support, which is an incremental speed upgrade
> >> of AXI 1G MAC and supports 2.5G speed only. "max-speed" DT property
> >> is used in driver to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
> >> If max-speed property is missing, 1G is assumed to support backward
> >> compatibility.
> >> 
> >> Co-developed-by: Harini Katakam <harini.katakam@amd.com>
> >> Signed-off-by: Harini Katakam <harini.katakam@amd.com>
> >> Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
> >> ---
> > 
> > ...
> > 
> >> -	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |
> >> -		MAC_10FD | MAC_100FD | MAC_1000FD;
> >> +	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
> >> +
> >> +	/* Set MAC capabilities based on MAC type */
> >> +	if (lp->max_speed == SPEED_1000)
> >> +		lp->phylink_config.mac_capabilities |= MAC_10FD | MAC_100FD | MAC_1000FD;
> >> +	else
> >> +		lp->phylink_config.mac_capabilities |= MAC_2500FD;
> > 
> > The MAC can only operate at (10M, 100M, 1G) _or_ 2.5G ?
> 
> It's a PCS limitation. It either does (1000Base-X and/or SGMII) OR
> (2500Base-X). The MAC itself doesn't have this limitation AFAIK.

That means the patch is definitely wrong, and the proposed DT
change is also wrong.

If it's a limitation of the PCS, that limitation should be applied
via the PCS's .pcs_validate() method, not at the MAC level.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

RE: [PATCH net-next 2/2] net: axienet: Add support for AXI 2.5G MAC

[Gupta, Suraj]

> -----Original Message-----
> From: Russell King <linux@armlinux.org.uk>
> Sent: Monday, November 18, 2024 9:39 PM
> To: Sean Anderson <sean.anderson@linux.dev>
> Cc: Gupta, Suraj <Suraj.Gupta2@amd.com>; andrew+netdev@lunn.ch;
> davem@davemloft.net; edumazet@google.com; kuba@kernel.org;
> pabeni@redhat.com; Simek, Michal <michal.simek@amd.com>; Pandey, Radhey
> Shyam <radhey.shyam.pandey@amd.com>; horms@kernel.org;
> netdev@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; git (AMD-Xilinx) <git@amd.com>; Katakam, Harini
> <harini.katakam@amd.com>
> Subject: Re: [PATCH net-next 2/2] net: axienet: Add support for AXI 2.5G MAC
> 
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
> 
> 
> On Mon, Nov 18, 2024 at 11:00:22AM -0500, Sean Anderson wrote:
> > On 11/18/24 10:56, Russell King (Oracle) wrote:
> > > On Mon, Nov 18, 2024 at 01:48:22PM +0530, Suraj Gupta wrote:
> > >> Add AXI 2.5G MAC support, which is an incremental speed upgrade of
> > >> AXI 1G MAC and supports 2.5G speed only. "max-speed" DT property is
> > >> used in driver to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
> > >> If max-speed property is missing, 1G is assumed to support backward
> > >> compatibility.
> > >>
> > >> Co-developed-by: Harini Katakam <harini.katakam@amd.com>
> > >> Signed-off-by: Harini Katakam <harini.katakam@amd.com>
> > >> Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
> > >> ---
> > >
> > > ...
> > >
> > >> -  lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE |
> MAC_ASYM_PAUSE |
> > >> -          MAC_10FD | MAC_100FD | MAC_1000FD;
> > >> +  lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE |
> > >> + MAC_ASYM_PAUSE;
> > >> +
> > >> +  /* Set MAC capabilities based on MAC type */  if (lp->max_speed
> > >> + == SPEED_1000)
> > >> +          lp->phylink_config.mac_capabilities |= MAC_10FD |
> > >> + MAC_100FD | MAC_1000FD;  else
> > >> +          lp->phylink_config.mac_capabilities |= MAC_2500FD;
> > >
> > > The MAC can only operate at (10M, 100M, 1G) _or_ 2.5G ?
> >
> > It's a PCS limitation. It either does (1000Base-X and/or SGMII) OR
> > (2500Base-X). The MAC itself doesn't have this limitation AFAIK.
> 
> That means the patch is definitely wrong, and the proposed DT change is also
> wrong.
> 
> If it's a limitation of the PCS, that limitation should be applied via the PCS's
> .pcs_validate() method, not at the MAC level.
> 
As mentioned in IP PG (https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/Ethernet-Overview#:~:text=Typical%20Ethernet%20Architecture-,MAC,-For%2010/100), it's limitation in MAC also.

> --
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

Re: [PATCH net-next 2/2] net: axienet: Add support for AXI 2.5G MAC

[Russell King (Oracle)]

On Tue, Nov 19, 2024 at 10:28:48AM +0000, Gupta, Suraj wrote:
> > -----Original Message-----
> > From: Russell King <linux@armlinux.org.uk>
> > 
> > On Mon, Nov 18, 2024 at 11:00:22AM -0500, Sean Anderson wrote:
> > > On 11/18/24 10:56, Russell King (Oracle) wrote:
> > > > On Mon, Nov 18, 2024 at 01:48:22PM +0530, Suraj Gupta wrote:
> > > >> Add AXI 2.5G MAC support, which is an incremental speed upgrade of
> > > >> AXI 1G MAC and supports 2.5G speed only. "max-speed" DT property is
> > > >> used in driver to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
> > > >> If max-speed property is missing, 1G is assumed to support backward
> > > >> compatibility.
> > > >>
> > > >> Co-developed-by: Harini Katakam <harini.katakam@amd.com>
> > > >> Signed-off-by: Harini Katakam <harini.katakam@amd.com>
> > > >> Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
> > > >> ---
> > > >
> > > > ...
> > > >
> > > >> -  lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE |
> > MAC_ASYM_PAUSE |
> > > >> -          MAC_10FD | MAC_100FD | MAC_1000FD;
> > > >> +  lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE |
> > > >> + MAC_ASYM_PAUSE;
> > > >> +
> > > >> +  /* Set MAC capabilities based on MAC type */  if (lp->max_speed
> > > >> + == SPEED_1000)
> > > >> +          lp->phylink_config.mac_capabilities |= MAC_10FD |
> > > >> + MAC_100FD | MAC_1000FD;  else
> > > >> +          lp->phylink_config.mac_capabilities |= MAC_2500FD;
> > > >
> > > > The MAC can only operate at (10M, 100M, 1G) _or_ 2.5G ?
> > >
> > > It's a PCS limitation. It either does (1000Base-X and/or SGMII) OR
> > > (2500Base-X). The MAC itself doesn't have this limitation AFAIK.
> > 
> > That means the patch is definitely wrong, and the proposed DT change is also
> > wrong.
> > 
> > If it's a limitation of the PCS, that limitation should be applied via the PCS's
> > .pcs_validate() method, not at the MAC level.
> > 
> As mentioned in IP PG (https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/Ethernet-Overview#:~:text=Typical%20Ethernet%20Architecture-,MAC,-For%2010/100), it's limitation in MAC also.

I'm not reading it as a limitation of the MAC.

The limitation stated there is that internal mode (GMII) is only
supported for 2.5Gbps speeds. At 2.5Gbps speeds, the clock rate is
increased from 125MHz to 312.5MHz (which makes it non-compliant
with 802.3-2008, because that version doesn't define 2.5Gbps speeds.)

So long as the clock rate and interface can be safely switched, I
don't see any reason to restrict the MAC itself to be either
10/100/1G _or_ 2.5G.

Note that 2.5G will only become available if it is supported by one
of the supported interface modes (e.g. 2500base-X). If the supported
interface modes do not include a mode that supports >1G, then 2.5G
won't be available even if MAC_2500FD is set in mac_capabilities.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

Re: [PATCH net-next 2/2] net: axienet: Add support for AXI 2.5G MAC

[Russell King (Oracle)]

On Tue, Nov 19, 2024 at 01:18:57PM +0000, Russell King (Oracle) wrote:
> On Tue, Nov 19, 2024 at 10:28:48AM +0000, Gupta, Suraj wrote:
> > > -----Original Message-----
> > > From: Russell King <linux@armlinux.org.uk>
> > > 
> > > On Mon, Nov 18, 2024 at 11:00:22AM -0500, Sean Anderson wrote:
> > > > On 11/18/24 10:56, Russell King (Oracle) wrote:
> > > > > On Mon, Nov 18, 2024 at 01:48:22PM +0530, Suraj Gupta wrote:
> > > > >> Add AXI 2.5G MAC support, which is an incremental speed upgrade of
> > > > >> AXI 1G MAC and supports 2.5G speed only. "max-speed" DT property is
> > > > >> used in driver to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
> > > > >> If max-speed property is missing, 1G is assumed to support backward
> > > > >> compatibility.
> > > > >>
> > > > >> Co-developed-by: Harini Katakam <harini.katakam@amd.com>
> > > > >> Signed-off-by: Harini Katakam <harini.katakam@amd.com>
> > > > >> Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
> > > > >> ---
> > > > >
> > > > > ...
> > > > >
> > > > >> -  lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE |
> > > MAC_ASYM_PAUSE |
> > > > >> -          MAC_10FD | MAC_100FD | MAC_1000FD;
> > > > >> +  lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE |
> > > > >> + MAC_ASYM_PAUSE;
> > > > >> +
> > > > >> +  /* Set MAC capabilities based on MAC type */  if (lp->max_speed
> > > > >> + == SPEED_1000)
> > > > >> +          lp->phylink_config.mac_capabilities |= MAC_10FD |
> > > > >> + MAC_100FD | MAC_1000FD;  else
> > > > >> +          lp->phylink_config.mac_capabilities |= MAC_2500FD;
> > > > >
> > > > > The MAC can only operate at (10M, 100M, 1G) _or_ 2.5G ?
> > > >
> > > > It's a PCS limitation. It either does (1000Base-X and/or SGMII) OR
> > > > (2500Base-X). The MAC itself doesn't have this limitation AFAIK.
> > > 
> > > That means the patch is definitely wrong, and the proposed DT change is also
> > > wrong.
> > > 
> > > If it's a limitation of the PCS, that limitation should be applied via the PCS's
> > > .pcs_validate() method, not at the MAC level.
> > > 
> > As mentioned in IP PG (https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/Ethernet-Overview#:~:text=Typical%20Ethernet%20Architecture-,MAC,-For%2010/100), it's limitation in MAC also.
> 
> I'm not reading it as a limitation of the MAC.
> 
> The limitation stated there is that internal mode (GMII) is only
> supported for 2.5Gbps speeds. At 2.5Gbps speeds, the clock rate is
> increased from 125MHz to 312.5MHz (which makes it non-compliant
> with 802.3-2008, because that version doesn't define 2.5Gbps speeds.)
> 
> So long as the clock rate and interface can be safely switched, I
> don't see any reason to restrict the MAC itself to be either
> 10/100/1G _or_ 2.5G.
> 
> Note that 2.5G will only become available if it is supported by one
> of the supported interface modes (e.g. 2500base-X). If the supported
> interface modes do not include a mode that supports >1G, then 2.5G
> won't be available even if MAC_2500FD is set in mac_capabilities.

Reading further, PG047 which is the PCS, suggests that it can operate
at 10, 100, 1G, and 2.5G.

Moreover, what I read there is that where a PCS core supports 2.5G, it
can operate at 10, 100, 1G or 2.5G depending on the clock. Note 2 in
"Transceiver ports".

However, it doesn't support TBI at 2.5Gbps mode, only the 2500BASE-X
PMA/PMD.

Also states "The core operates at 125 MHz for the 1 Gbps data rate
(1.25Gbps line rate) and 312.5 MHz at 2.5 Gbps data rates (3.125 Gbps
line rate) in modes having device transceivers." These differences in
clocking are typical for systems that support 1G and 2.5G.

So, I'm still wondering what the limitation is. If the MAC transmit
clock can only run at 125MHz, or only at 312.5MHz, depending on the
design, then yes, it would be appropriate to limit the MAC to 1G
(and below) or 2.5G speeds.

However, if there's designs that allow the transmit clock to be
configured at run time, then the system supports both speeds.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

Re: [PATCH net-next 2/2] net: axienet: Add support for AXI 2.5G MAC

[Andrew Lunn]

On Mon, Nov 18, 2024 at 11:00:22AM -0500, Sean Anderson wrote:
> On 11/18/24 10:56, Russell King (Oracle) wrote:
> > On Mon, Nov 18, 2024 at 01:48:22PM +0530, Suraj Gupta wrote:
> >> Add AXI 2.5G MAC support, which is an incremental speed upgrade
> >> of AXI 1G MAC and supports 2.5G speed only. "max-speed" DT property
> >> is used in driver to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
> >> If max-speed property is missing, 1G is assumed to support backward
> >> compatibility.
> >> 
> >> Co-developed-by: Harini Katakam <harini.katakam@amd.com>
> >> Signed-off-by: Harini Katakam <harini.katakam@amd.com>
> >> Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
> >> ---
> > 
> > ...
> > 
> >> -	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |
> >> -		MAC_10FD | MAC_100FD | MAC_1000FD;
> >> +	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
> >> +
> >> +	/* Set MAC capabilities based on MAC type */
> >> +	if (lp->max_speed == SPEED_1000)
> >> +		lp->phylink_config.mac_capabilities |= MAC_10FD | MAC_100FD | MAC_1000FD;
> >> +	else
> >> +		lp->phylink_config.mac_capabilities |= MAC_2500FD;
> > 
> > The MAC can only operate at (10M, 100M, 1G) _or_ 2.5G ?
> 
> It's a PCS limitation. It either does (1000Base-X and/or SGMII) OR
> (2500Base-X). The MAC itself doesn't have this limitation AFAIK.


And can the PCS change between these modes? It is pretty typical to
use SGMII for 10/100/1G and then swap to 2500BaseX for 2.5G.

	Andrew

Re: [PATCH net-next 2/2] net: axienet: Add support for AXI 2.5G MAC

[Sean Anderson]

On 11/18/24 20:35, Andrew Lunn wrote:
> On Mon, Nov 18, 2024 at 11:00:22AM -0500, Sean Anderson wrote:
>> On 11/18/24 10:56, Russell King (Oracle) wrote:
>> > On Mon, Nov 18, 2024 at 01:48:22PM +0530, Suraj Gupta wrote:
>> >> Add AXI 2.5G MAC support, which is an incremental speed upgrade
>> >> of AXI 1G MAC and supports 2.5G speed only. "max-speed" DT property
>> >> is used in driver to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
>> >> If max-speed property is missing, 1G is assumed to support backward
>> >> compatibility.
>> >> 
>> >> Co-developed-by: Harini Katakam <harini.katakam@amd.com>
>> >> Signed-off-by: Harini Katakam <harini.katakam@amd.com>
>> >> Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
>> >> ---
>> > 
>> > ...
>> > 
>> >> -	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |
>> >> -		MAC_10FD | MAC_100FD | MAC_1000FD;
>> >> +	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
>> >> +
>> >> +	/* Set MAC capabilities based on MAC type */
>> >> +	if (lp->max_speed == SPEED_1000)
>> >> +		lp->phylink_config.mac_capabilities |= MAC_10FD | MAC_100FD | MAC_1000FD;
>> >> +	else
>> >> +		lp->phylink_config.mac_capabilities |= MAC_2500FD;
>> > 
>> > The MAC can only operate at (10M, 100M, 1G) _or_ 2.5G ?
>> 
>> It's a PCS limitation. It either does (1000Base-X and/or SGMII) OR
>> (2500Base-X). The MAC itself doesn't have this limitation AFAIK.
> 
> 
> And can the PCS change between these modes? It is pretty typical to
> use SGMII for 10/100/1G and then swap to 2500BaseX for 2.5G.

Not AFAIK. There's only a bit for switching between 1000Base-X and
SGMII. 2500Base-X is selected at synthesis time, and AIUI the serdes
settings are different.

--Sean

Re: [PATCH net-next 2/2] net: axienet: Add support for AXI 2.5G MAC

[Russell King (Oracle)]

On Tue, Nov 19, 2024 at 10:26:52AM -0500, Sean Anderson wrote:
> On 11/18/24 20:35, Andrew Lunn wrote:
> > On Mon, Nov 18, 2024 at 11:00:22AM -0500, Sean Anderson wrote:
> >> On 11/18/24 10:56, Russell King (Oracle) wrote:
> >> > On Mon, Nov 18, 2024 at 01:48:22PM +0530, Suraj Gupta wrote:
> >> >> Add AXI 2.5G MAC support, which is an incremental speed upgrade
> >> >> of AXI 1G MAC and supports 2.5G speed only. "max-speed" DT property
> >> >> is used in driver to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
> >> >> If max-speed property is missing, 1G is assumed to support backward
> >> >> compatibility.
> >> >> 
> >> >> Co-developed-by: Harini Katakam <harini.katakam@amd.com>
> >> >> Signed-off-by: Harini Katakam <harini.katakam@amd.com>
> >> >> Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
> >> >> ---
> >> > 
> >> > ...
> >> > 
> >> >> -	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |
> >> >> -		MAC_10FD | MAC_100FD | MAC_1000FD;
> >> >> +	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
> >> >> +
> >> >> +	/* Set MAC capabilities based on MAC type */
> >> >> +	if (lp->max_speed == SPEED_1000)
> >> >> +		lp->phylink_config.mac_capabilities |= MAC_10FD | MAC_100FD | MAC_1000FD;
> >> >> +	else
> >> >> +		lp->phylink_config.mac_capabilities |= MAC_2500FD;
> >> > 
> >> > The MAC can only operate at (10M, 100M, 1G) _or_ 2.5G ?
> >> 
> >> It's a PCS limitation. It either does (1000Base-X and/or SGMII) OR
> >> (2500Base-X). The MAC itself doesn't have this limitation AFAIK.
> > 
> > 
> > And can the PCS change between these modes? It is pretty typical to
> > use SGMII for 10/100/1G and then swap to 2500BaseX for 2.5G.
> 
> Not AFAIK. There's only a bit for switching between 1000Base-X and
> SGMII. 2500Base-X is selected at synthesis time, and AIUI the serdes
> settings are different.

Okay. First it was a PCS limitation. Then it was a MAC limitation. Now
it's a synthesis limitation.

I'm coming to the conclusion that those I'm communicating with don't
actually know, and are just throwing random thoughts out there.

Please do the research, and come back to me with a real and complete
answer, not some hand-wavey "it's a limitation of X, no it's a
limitation of Y, no it's a limitation of Z" which looks like no one
really knows the correct answer.

Just because the PCS doesn't have a bit that selects 2500base-X is
meaningless. 2500base-X is generally implemented by upclocking
1000base-X by 2.5x. Marvell does this at their Serdes, there is
no configuration at the MAC/PCS for 2.5G speeds.

The same is true of 10GBASE-R vs 5GBASE-R in Marvell - 5GBASE-R is
just the serdes clocking the MAC/PCS at half the rate that 10GBASE-R
would run at.

I suspect this Xilinx hardware is just the same - clock the transmit
path it at 62.5MHz, and you get 1G speeds. Clock it at 156.25MHz,
and you get 2.5G speeds.

Thanks.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

Re: [PATCH net-next 2/2] net: axienet: Add support for AXI 2.5G MAC

[Sean Anderson]

On 11/19/24 10:49, Russell King (Oracle) wrote:
> On Tue, Nov 19, 2024 at 10:26:52AM -0500, Sean Anderson wrote:
>> On 11/18/24 20:35, Andrew Lunn wrote:
>> > On Mon, Nov 18, 2024 at 11:00:22AM -0500, Sean Anderson wrote:
>> >> On 11/18/24 10:56, Russell King (Oracle) wrote:
>> >> > On Mon, Nov 18, 2024 at 01:48:22PM +0530, Suraj Gupta wrote:
>> >> >> Add AXI 2.5G MAC support, which is an incremental speed upgrade
>> >> >> of AXI 1G MAC and supports 2.5G speed only. "max-speed" DT property
>> >> >> is used in driver to distinguish 1G and 2.5G MACs of AXI 1G/2.5G IP.
>> >> >> If max-speed property is missing, 1G is assumed to support backward
>> >> >> compatibility.
>> >> >> 
>> >> >> Co-developed-by: Harini Katakam <harini.katakam@amd.com>
>> >> >> Signed-off-by: Harini Katakam <harini.katakam@amd.com>
>> >> >> Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
>> >> >> ---
>> >> > 
>> >> > ...
>> >> > 
>> >> >> -	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |
>> >> >> -		MAC_10FD | MAC_100FD | MAC_1000FD;
>> >> >> +	lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
>> >> >> +
>> >> >> +	/* Set MAC capabilities based on MAC type */
>> >> >> +	if (lp->max_speed == SPEED_1000)
>> >> >> +		lp->phylink_config.mac_capabilities |= MAC_10FD | MAC_100FD | MAC_1000FD;
>> >> >> +	else
>> >> >> +		lp->phylink_config.mac_capabilities |= MAC_2500FD;
>> >> > 
>> >> > The MAC can only operate at (10M, 100M, 1G) _or_ 2.5G ?
>> >> 
>> >> It's a PCS limitation. It either does (1000Base-X and/or SGMII) OR
>> >> (2500Base-X). The MAC itself doesn't have this limitation AFAIK.
>> > 
>> > 
>> > And can the PCS change between these modes? It is pretty typical to
>> > use SGMII for 10/100/1G and then swap to 2500BaseX for 2.5G.
>> 
>> Not AFAIK. There's only a bit for switching between 1000Base-X and
>> SGMII. 2500Base-X is selected at synthesis time, and AIUI the serdes
>> settings are different.
> 
> Okay. First it was a PCS limitation. Then it was a MAC limitation. Now
> it's a synthesis limitation.
> 
> I'm coming to the conclusion that those I'm communicating with don't
> actually know, and are just throwing random thoughts out there.
> 
> Please do the research, and come back to me with a real and complete
> answer, not some hand-wavey "it's a limitation of X, no it's a
> limitation of Y, no it's a limitation of Z" which looks like no one
> really knows the correct answer.
> 
> Just because the PCS doesn't have a bit that selects 2500base-X is
> meaningless. 2500base-X is generally implemented by upclocking
> 1000base-X by 2.5x. Marvell does this at their Serdes, there is
> no configuration at the MAC/PCS for 2.5G speeds.
> 
> The same is true of 10GBASE-R vs 5GBASE-R in Marvell - 5GBASE-R is
> just the serdes clocking the MAC/PCS at half the rate that 10GBASE-R
> would run at.
> 
> I suspect this Xilinx hardware is just the same - clock the transmit
> path it at 62.5MHz, and you get 1G speeds. Clock it at 156.25MHz,
> and you get 2.5G speeds.

Hey, I'm just a l^Huser.

In the synthesis settings for the PCS, you can select

  - 1G
    - 1000BASEX
    - SGMII
    - BOTH
  - 2 5G
    - 2500 BASEX
    - 2.5G SGMII

(all of the above being exclusive choices)

In the synthesis settings for the MAC, you can select

  - 1 Gbps
    - Tri speed
    - 1000 Mbps
  - 2.5 Gbps
    - 2500 Mbps

(ditto)

I can't comment on what happens when you over/underclock the MAC or PCS.

--Sean

RE: [PATCH net-next 2/2] net: axienet: Add support for AXI 2.5G MAC

[Gupta, Suraj]

[AMD Official Use Only - AMD Internal Distribution Only]

> -----Original Message-----
> From: Russell King <linux@armlinux.org.uk>
> Sent: Tuesday, November 19, 2024 9:19 PM
> To: Sean Anderson <sean.anderson@linux.dev>
> Cc: Andrew Lunn <andrew@lunn.ch>; Gupta, Suraj <Suraj.Gupta2@amd.com>;
> andrew+netdev@lunn.ch; davem@davemloft.net; edumazet@google.com;
> kuba@kernel.org; pabeni@redhat.com; Simek, Michal <michal.simek@amd.com>;
> Pandey, Radhey Shyam <radhey.shyam.pandey@amd.com>; horms@kernel.org;
> netdev@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; git (AMD-Xilinx) <git@amd.com>; Katakam, Harini
> <harini.katakam@amd.com>
> Subject: Re: [PATCH net-next 2/2] net: axienet: Add support for AXI 2.5G MAC
>
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> On Tue, Nov 19, 2024 at 10:26:52AM -0500, Sean Anderson wrote:
> > On 11/18/24 20:35, Andrew Lunn wrote:
> > > On Mon, Nov 18, 2024 at 11:00:22AM -0500, Sean Anderson wrote:
> > >> On 11/18/24 10:56, Russell King (Oracle) wrote:
> > >> > On Mon, Nov 18, 2024 at 01:48:22PM +0530, Suraj Gupta wrote:
> > >> >> Add AXI 2.5G MAC support, which is an incremental speed upgrade
> > >> >> of AXI 1G MAC and supports 2.5G speed only. "max-speed" DT
> > >> >> property is used in driver to distinguish 1G and 2.5G MACs of AXI 1G/2.5G
> IP.
> > >> >> If max-speed property is missing, 1G is assumed to support
> > >> >> backward compatibility.
> > >> >>
> > >> >> Co-developed-by: Harini Katakam <harini.katakam@amd.com>
> > >> >> Signed-off-by: Harini Katakam <harini.katakam@amd.com>
> > >> >> Signed-off-by: Suraj Gupta <suraj.gupta2@amd.com>
> > >> >> ---
> > >> >
> > >> > ...
> > >> >
> > >> >> -       lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE |
> MAC_ASYM_PAUSE |
> > >> >> -               MAC_10FD | MAC_100FD | MAC_1000FD;
> > >> >> +       lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE |
> > >> >> + MAC_ASYM_PAUSE;
> > >> >> +
> > >> >> +       /* Set MAC capabilities based on MAC type */
> > >> >> +       if (lp->max_speed == SPEED_1000)
> > >> >> +               lp->phylink_config.mac_capabilities |= MAC_10FD |
> MAC_100FD | MAC_1000FD;
> > >> >> +       else
> > >> >> +               lp->phylink_config.mac_capabilities |=
> > >> >> + MAC_2500FD;
> > >> >
> > >> > The MAC can only operate at (10M, 100M, 1G) _or_ 2.5G ?
> > >>
> > >> It's a PCS limitation. It either does (1000Base-X and/or SGMII) OR
> > >> (2500Base-X). The MAC itself doesn't have this limitation AFAIK.
> > >
> > >
> > > And can the PCS change between these modes? It is pretty typical to
> > > use SGMII for 10/100/1G and then swap to 2500BaseX for 2.5G.
> >
> > Not AFAIK. There's only a bit for switching between 1000Base-X and
> > SGMII. 2500Base-X is selected at synthesis time, and AIUI the serdes
> > settings are different.
>
> Okay. First it was a PCS limitation. Then it was a MAC limitation. Now it's a
> synthesis limitation.
>
> I'm coming to the conclusion that those I'm communicating with don't actually know,
> and are just throwing random thoughts out there.
>
> Please do the research, and come back to me with a real and complete answer, not
> some hand-wavey "it's a limitation of X, no it's a limitation of Y, no it's a limitation of
> Z" which looks like no one really knows the correct answer.
>
> Just because the PCS doesn't have a bit that selects 2500base-X is meaningless.
> 2500base-X is generally implemented by upclocking 1000base-X by 2.5x. Marvell
> does this at their Serdes, there is no configuration at the MAC/PCS for 2.5G speeds.
>
> The same is true of 10GBASE-R vs 5GBASE-R in Marvell - 5GBASE-R is just the
> serdes clocking the MAC/PCS at half the rate that 10GBASE-R would run at.
>
> I suspect this Xilinx hardware is just the same - clock the transmit path it at
> 62.5MHz, and you get 1G speeds. Clock it at 156.25MHz, and you get 2.5G speeds.
>

Sorry for picking up this thread after long time, we checked internally with AMD IP and hardware experts and it is true that you can use this MAC and PCS to operate at 1G and 2.5G both. It is also possible to switch between these two speeds dynamically using external GT and/or if an external RTL logic is implemented in the FPGA. That will include some GPIO or register based selections to change the clock and configurations to switch between the speeds. Our current solution does not support this and is meant for a static speed selection only.
If some user wants to implement dynamic speed switching solution, that will need to be accompanied by additional software changes later.

We'll use MAC ability register to detect if MAC is configured for 2.5G. Will it be fine to advertise both 1G and 2.5G in that case?

> Thanks.
>
> --
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

Re: [PATCH net-next 2/2] net: axienet: Add support for AXI 2.5G MAC

[Russell King (Oracle)]

On Thu, Feb 20, 2025 at 11:30:52AM +0000, Gupta, Suraj wrote:
> Sorry for picking up this thread after long time, we checked
> internally with AMD IP and hardware experts and it is true that you
> can use this MAC and PCS to operate at 1G and 2.5G both. It is also
> possible to switch between these two speeds dynamically using
> external GT and/or if an external RTL logic is implemented in the
> FPGA. That will include some GPIO or register based selections to
> change the clock and configurations to switch between the speeds.
> Our current solution does not support this and is meant for a
> static speed selection only.

Thanks for getting back on this.

Okay, so it's a synthesis option, where that may be one of:

1. SGMII/1000base-X only
2. 2500base-X only
3. dynamically switching between (1) and (2).

> We'll use MAC ability register to detect if MAC is configured for
> 2.5G. Will it be fine to advertise both 1G and 2.5G in that case?

Please document in a comment that the above are synthesis options,
and that dynamically changing between them is possible but not
implemented by the driver. Note that should anyone use axienet for
SFP modules, then (1) is essentially the base functionality, (2) is
very limiting, and (3) would be best.

Not only will one want to limit the MAC capabilities, but also the
supported interface modes. As it's been so long since the patch was
posted, I don't remember whether it did that or not.

Thanks.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

RE: [PATCH net-next 2/2] net: axienet: Add support for AXI 2.5G MAC

[Gupta, Suraj]

[AMD Official Use Only - AMD Internal Distribution Only]

> -----Original Message-----
> From: Russell King <linux@armlinux.org.uk>
> Sent: Thursday, February 20, 2025 5:14 PM
> To: Gupta, Suraj <Suraj.Gupta2@amd.com>
> Cc: Sean Anderson <sean.anderson@linux.dev>; Andrew Lunn <andrew@lunn.ch>;
> andrew+netdev@lunn.ch; davem@davemloft.net; edumazet@google.com;
> kuba@kernel.org; pabeni@redhat.com; Simek, Michal <michal.simek@amd.com>;
> Pandey, Radhey Shyam <radhey.shyam.pandey@amd.com>; horms@kernel.org;
> netdev@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; git (AMD-Xilinx) <git@amd.com>; Katakam, Harini
> <harini.katakam@amd.com>
> Subject: Re: [PATCH net-next 2/2] net: axienet: Add support for AXI 2.5G MAC
>
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> On Thu, Feb 20, 2025 at 11:30:52AM +0000, Gupta, Suraj wrote:
> > Sorry for picking up this thread after long time, we checked
> > internally with AMD IP and hardware experts and it is true that you
> > can use this MAC and PCS to operate at 1G and 2.5G both. It is also
> > possible to switch between these two speeds dynamically using external
> > GT and/or if an external RTL logic is implemented in the FPGA. That
> > will include some GPIO or register based selections to change the
> > clock and configurations to switch between the speeds.
> > Our current solution does not support this and is meant for a static
> > speed selection only.
>
> Thanks for getting back on this.
>
> Okay, so it's a synthesis option, where that may be one of:
>
> 1. SGMII/1000base-X only
> 2. 2500base-X only
> 3. dynamically switching between (1) and (2).
>
> > We'll use MAC ability register to detect if MAC is configured for
> > 2.5G. Will it be fine to advertise both 1G and 2.5G in that case?
>
> Please document in a comment that the above are synthesis options, and that
> dynamically changing between them is possible but not implemented by the driver.
> Note that should anyone use axienet for SFP modules, then (1) is essentially the
> base functionality, (2) is very limiting, and (3) would be best.
>
> Not only will one want to limit the MAC capabilities, but also the supported interface
> modes. As it's been so long since the patch was posted, I don't remember whether it
> did that or not.
>

Sure, will document in the comment and limit both mac capabilities and supported interfaces accordingly.
Thank you for your quick response and guidance. I really appreciate your support!

> Thanks.
>
> --
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

Re: [PATCH net-next 2/2] net: axienet: Add support for AXI 2.5G MAC

[Andrew Lunn]

> > Okay, so it's a synthesis option, where that may be one of:
> >
> > 1. SGMII/1000base-X only
> > 2. 2500base-X only
> > 3. dynamically switching between (1) and (2).
> >
> > > We'll use MAC ability register to detect if MAC is configured for
> > > 2.5G. Will it be fine to advertise both 1G and 2.5G in that case?
> >
> > Please document in a comment that the above are synthesis options, and that
> > dynamically changing between them is possible but not implemented by the driver.
> > Note that should anyone use axienet for SFP modules, then (1) is essentially the
> > base functionality, (2) is very limiting, and (3) would be best.
> >
> > Not only will one want to limit the MAC capabilities, but also the supported interface
> > modes. As it's been so long since the patch was posted, I don't remember whether it
> > did that or not.
> >
> 
> Sure, will document in the comment and limit both mac capabilities and supported interfaces accordingly.
> Thank you for your quick response and guidance. I really appreciate your support!

It is likely somebody will want 3 sometime in the future, since the
current limitation is pretty silly. So please think about this, try
not to put in any roadblocks to that extension.

	Andrew