From: Kyle Hendry <kylehendrydev@gmail.com>
To: Andrew Lunn <andrew@lunn.ch>,
Florian Fainelli <florian.fainelli@broadcom.com>
Cc: Vladimir Oltean <olteanv@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Russell King <linux@armlinux.org.uk>,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/4] net: dsa: b53: Enable internal GPHY on BCM63268
Date: Thu, 6 Feb 2025 17:41:19 -0800 [thread overview]
Message-ID: <a804e0a4-2275-41c3-be3b-7dd79c2418cd@gmail.com> (raw)
In-Reply-To: <9bd9c1e4-2401-46bd-937f-996e97d750c5@lunn.ch>
On 2025-02-06 12:17, Andrew Lunn wrote:
> On Thu, Feb 06, 2025 at 10:15:50AM -0800, Florian Fainelli wrote:
>> Hi Kyle,
>>
>> On 2/5/25 20:30, Kyle Hendry wrote:
>>> Some BCM63268 bootloaders do not enable the internal PHYs by default.
>>> This patch series adds functionality for the switch driver to
>>> configure the gigabit ethernet PHY.
>>>
>>> Signed-off-by: Kyle Hendry <kylehendrydev@gmail.com>
>> So the register address you are manipulating logically belongs in the GPIO
>> block (GPIO_GPHY_CTRL) which has become quite a bit of a sundry here. I
>> don't have a strong objection about the approach picked up here but we will
>> need a Device Tree binding update describing the second (and optional)
>> register range.
> Despite this being internal, is this actually a GPIO? Should it be
> modelled as a GPIO line connected to a reset input on the PHY? It
> would then nicely fit in the existing phylib handling of a PHY with a
> GPIO reset line?
>
> Andrew
The main reason I took this approach is because a SF2 register has
similar bits and I wanted to be consistent with that driver. If it
makes more sense to treat these bits as GPIOs/clocks/resets then it
would make the implementation simpler.
Best Regards,
Kyle
next prev parent reply other threads:[~2025-02-07 1:41 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-06 4:30 [PATCH 0/4] net: dsa: b53: Enable internal GPHY on BCM63268 Kyle Hendry
2025-02-06 4:30 ` [PATCH 1/4] net: dsa: b53: Indicate which BCM63268 port is GPHY Kyle Hendry
2025-02-06 4:30 ` [PATCH 2/4] net: dsa: b53: mmap: Add gphy control register as a resource Kyle Hendry
2025-02-06 4:30 ` [PATCH 3/4] net: dsa: b53: Add phy_enable(), phy_disable() methods Kyle Hendry
2025-02-06 4:30 ` [PATCH 4/4] net: dsa: b53: mmap: Implement phy_enable for BCM63268 gphy Kyle Hendry
2025-02-06 18:15 ` [PATCH 0/4] net: dsa: b53: Enable internal GPHY on BCM63268 Florian Fainelli
2025-02-06 20:17 ` Andrew Lunn
2025-02-07 1:41 ` Kyle Hendry [this message]
2025-02-07 16:44 ` Vladimir Oltean
2025-02-07 16:44 ` Florian Fainelli
2025-02-09 23:30 ` Andrew Lunn
2025-02-10 17:25 ` Florian Fainelli
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