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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72bdbc95e4sm223260366b.12.2025.11.07.03.34.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Nov 2025 03:34:36 -0800 (PST) Message-ID: Date: Fri, 7 Nov 2025 12:34:33 +0100 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next] net: stmmac: qcom-ethqos: remove MAC_CTRL_REG modification To: "Russell King (Oracle)" Cc: Mohd Ayaan Anwar , Alexandre Torgue , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Maxime Coquelin , netdev@vger.kernel.org, Paolo Abeni , Vinod Koul References: <7a774a6d-3f8f-4f77-9752-571eadd599bf@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTA3MDA5NCBTYWx0ZWRfX3itPH6+aD53v YPwYGpYzcA2EscaadcR/W8YbhF5R3d+w/DXaVE+3ySAqQ40MOrnhuOf5ujbS6wB5PmvREgG9rKp NgK/drtYw0Cy97S9S5iDSybLNoHFRMYYEiREI2CHsH09sQHeWNL28Vnri2nze1nlLEWsVtvhlIv yT0AeXjag3+QDLfZFfex31v9hiCD6AxpLli1F46IBnTRiiLIM82fux6dVqWOcuUmVeQ66HZLocR iD8EUPc6E3u9hhPr942C8xpHl0RhmQPYwcl3Pf7dHUGoDMG6Puc7g1aARxy+PjjyTtfJN1vmWMZ /IV/nya4uNAawdU4//6AwYOqHYUKulc0v0rtqsJ0wHFqsM3nkb4ntPK1j/HE65GBV/Ql10sFNSY XR1nHuxzGycAFyObRsY0/HGK5na7Vg== X-Proofpoint-ORIG-GUID: pgrNvEATWiGgJfCRQHqqgiIVJr2ii6A4 X-Authority-Analysis: v=2.4 cv=A+hh/qWG c=1 sm=1 tr=0 ts=690dd94f cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=H4ebBzf8g92K_wxokogA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: pgrNvEATWiGgJfCRQHqqgiIVJr2ii6A4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-07_02,2025-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 spamscore=0 bulkscore=0 malwarescore=0 impostorscore=0 phishscore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511070094 On 10/30/25 3:05 PM, Russell King (Oracle) wrote: > On Thu, Oct 30, 2025 at 02:08:41PM +0100, Konrad Dybcio wrote: >> On 10/30/25 1:17 PM, Russell King (Oracle) wrote: >>> Konrad, Ayaan, >>> >>> Can you shed any light on the manipulation of the RGMII_IO_MACRO_CONFIG >>> and RGMII_IO_MACRO_CONFIG2 registers in ethqos_configure_sgmii()? >>> >>> Specifically: >>> - why would RGMII_CONFIG2_RGMII_CLK_SEL_CFG be set for 2.5G and 1G >>> speeds, but never be cleared for any other speed? >> >> BIT(16) - "enable to transmit delayed clock in RGMII 100/10 ID Mode" > > I guess that means that changing this bit is not relevant for the SGMII > path, and thus can be removed: > > switch (speed) { > case SPEED_2500: > - rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG, > - RGMII_CONFIG2_RGMII_CLK_SEL_CFG, > - RGMII_IO_MACRO_CONFIG2); > ethqos_set_serdes_speed(ethqos, SPEED_2500); > ethqos_pcs_set_inband(priv, false); > break; > case SPEED_1000: > - rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG, > - RGMII_CONFIG2_RGMII_CLK_SEL_CFG, > - RGMII_IO_MACRO_CONFIG2); > ethqos_set_serdes_speed(ethqos, SPEED_1000); > ethqos_pcs_set_inband(priv, true); > >>> - why is RGMII_CONFIG_SGMII_CLK_DVDR set to SGMII_10M_RX_CLK_DVDR >>> for 10M, but never set to any other value for other speeds? >> >> [18:10] - In short, it configures a divider. The expected value is 0x13 >> for 10 Mbps / RMII mode > > This gets confusing. Is the "/" meaning "10Mbps in RMII mode" or "10Mbps > or RMII mode". > >> which seems to have been problematic given: >> >> https://lore.kernel.org/all/20231212092208.22393-1-quic_snehshah@quicinc.com/ >> >> But it didn't say what hardware had this issue.. whether it concerns a >> specific SoC or all of them.. >> >> A programming guide mentions the new 0x31 value for 10 Mbps in a >> SoC-common paragraph so I suppose it's indeed better-er.. Perhaps issues >> could arise if you switch back to a faster mode? > > Could the 0x13 be a typo? Its suspicious that the two values are 0x13 > vs 0x31. 0x13 = 19 vs 0x31 = 49. 0x31 makes more sense than 19. > > The platform glue is required to supply clk_rx_i to the dwmac's MAC > receive path, deriving it from the 125MHz SGMII rx link clock divided > by 1, 5 or 50. Normally, this would be done by hardware signals output > from the dwmac. > > This suggests that the value programmed is one less than the actual > divisor. > > There's two possibilities why this value needs to be programmed: > > 1. the hardware doesn't divide the SGMII rx link clock according to > the hardware signals output from the dwmac, and needs the divisor to > be manually programmed. This would require the divisor to also be > programmed to 4 for 100M (but the driver doesn't do this.) > > 2. the hardware selects the clk_rx_i depending on the hardware > signals, and while 1G and 100M use a fixed divisor of 1 and 5, the > 10M divisor needs to be manually programmed. > > Any ideas what's really going on here? The computer says: RGMII ID mode - speed == 10 ? 0x13 : dontcare? RMII Bypass ID mode - - speed == (10 || 100) ? 0x13 : dontcare? (*the 100 above says "default" but that's again 0x13) RMII mode (100 Mbps) - default (0x13) RMII mode (10 MBps) - 0x13 SGMII mode - speed == 10 ? 0x31 : 0x13 Make of that what you will, I would *guess* there may be something like 2. going on Konrad