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Tue, 13 May 2025 01:32:14 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 13 May 2025 01:32:13 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 13 May 2025 01:32:13 -0700 Received: from 59cc1f87bccd (HY-LT91368.marvell.com [10.29.24.116]) by maili.marvell.com (Postfix) with SMTP id 5EAFA3F7079; Tue, 13 May 2025 01:32:09 -0700 (PDT) Date: Tue, 13 May 2025 08:32:07 +0000 From: Subbaraya Sundeep To: Simon Horman CC: , , , , , , , , , , , Subject: Re: [net-next v2 PATCH 2/2] octeontx2-pf: macsec: Get MACSEC capability flag from AF Message-ID: References: <1746969767-13129-1-git-send-email-sbhatta@marvell.com> <1746969767-13129-3-git-send-email-sbhatta@marvell.com> <20250512163732.GS3339421@horms.kernel.org> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20250512163732.GS3339421@horms.kernel.org> X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTEzMDA4MCBTYWx0ZWRfX/oD8gA7sxM5/ Re563Bjqgw/l37r4tsvG1Z0/mmY8ZBg/FDMh6HWXhol+L65AFDZQ4i5tqduIdYY7g9ECpy+hHtx 0LWKpmh5k3Gtr87zCNn6zTLblNibtEtLA6YOVEVB49yzZ9Gq5AMbJaksCSaSfi7Ig5losASr4gb ZxHfu5TDiGmAu1otiESrxkPTKo71oQf/FB5i9rsL6Z+B/InTKI0+E3d8TVjLboujvRcxZ+73hfu cQm7ypAaMdgBJtsc9AAlKzhI3c/jQmza96Y5h9RH2xXX62CAUdQiuCEilJKntJmik9oWVJjORlb HUGVE3s/3PG/AHg6zSiX4llH9rI3cKm51aX/ZRzEsGsZkX16QmiiPj7OeehbIhu+SGtj4mtbulP A+gsBx+5A5PWQ4ZzEkvf0RhqKLuYGG9VcN5vd8ZtlzGCNP9l8rXZzOWImDpDCUBeB/CSaBVU X-Authority-Analysis: v=2.4 cv=RvXFLDmK c=1 sm=1 tr=0 ts=6823038e cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=kj9zAlcOel0A:10 a=dt9VzEwgFbYA:10 a=VwQbUJbxAAAA:8 a=M5GUcnROAAAA:8 a=WSI0S-zNqxrGslh8q8AA:9 a=CjuIK1q_8ugA:10 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: 3d-PqArv5CTXBuDqOXllmeb-RhWMuRbM X-Proofpoint-ORIG-GUID: 3d-PqArv5CTXBuDqOXllmeb-RhWMuRbM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-12_07,2025-05-09_01,2025-02-21_01 Hi Simon, On 2025-05-12 at 16:37:32, Simon Horman (horms@kernel.org) wrote: > On Sun, May 11, 2025 at 06:52:47PM +0530, Subbaraya Sundeep wrote: > > The presence of MACSEC block is currently figured out based > > on the running silicon variant. This may not be correct all > > the times since the MACSEC block can be fused out. Hence get > > the macsec info from AF via mailbox. > > > > Signed-off-by: Subbaraya Sundeep > > ... > > > diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h > > index 7e3ddb0..7d0e39d 100644 > > --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h > > +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h > > @@ -631,9 +631,6 @@ static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf) > > __set_bit(CN10K_PTP_ONESTEP, &hw->cap_flag); > > __set_bit(QOS_CIR_PIR_SUPPORT, &hw->cap_flag); > > } > > - > > - if (is_dev_cn10kb(pfvf->pdev)) > > - __set_bit(CN10K_HW_MACSEC, &hw->cap_flag); > > } > > > > /* Register read/write APIs */ > > @@ -1043,6 +1040,7 @@ void otx2_disable_napi(struct otx2_nic *pf); > > irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq); > > int otx2_rq_init(struct otx2_nic *pfvf, u16 qidx, u16 lpb_aura); > > int otx2_cq_init(struct otx2_nic *pfvf, u16 qidx); > > +int otx2_set_hw_capabilities(struct otx2_nic *pfvf); > > > > /* RSS configuration APIs*/ > > int otx2_rss_init(struct otx2_nic *pfvf); > > diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c > > index 0aee8e3..a8ad4a2 100644 > > --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c > > +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c > > @@ -3126,6 +3126,8 @@ static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) > > if (err) > > goto err_ptp_destroy; > > > > + otx2_set_hw_capabilities(pf); > > + > > err = cn10k_mcs_init(pf); > > if (err) > > goto err_del_mcam_entries; > > Hi Subbaraya, > > If I read things correctly otx2_setup_dev_hw_settings() is called > for both representors and non-representors, while otx2_probe is > only called for non-representors. > > If so, my question is if this patch changes behaviour for representors. > And, again if so, if that is intentional. I assume you mean VF driver for representors and PF driver for non-representor. Yes this is intentional. We currently do not support macscec offload on VFs hence I changed only PF driver. In case we want to support macsec offload on VFs too then otx2vf_probe also need to be changed like: otx2_set_hw_capabilities(vf); err = cn10k_mcs_init(vf); Thanks, Sundeep