From: "Russell King (Oracle)" <linux@armlinux.org.uk>
To: george.moussalem@outlook.com
Cc: Andrew Lunn <andrew@lunn.ch>,
Heiner Kallweit <hkallweit1@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Florian Fainelli <f.fainelli@gmail.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
netdev@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-clk@vger.kernel.org
Subject: Re: [PATCH v4 3/5] net: phy: qcom: at803x: Add Qualcomm IPQ5018 Internal PHY support
Date: Mon, 9 Jun 2025 15:05:53 +0100 [thread overview]
Message-ID: <aEbqQYDi8_LN7lDj@shell.armlinux.org.uk> (raw)
In-Reply-To: <20250609-ipq5018-ge-phy-v4-3-1d3a125282c3@outlook.com>
On Mon, Jun 09, 2025 at 03:44:36PM +0400, George Moussalem via B4 Relay wrote:
> +static int ipq5018_config_init(struct phy_device *phydev)
> +{
> + struct ipq5018_priv *priv = phydev->priv;
> + u16 val = 0;
Useless initialisation. See the first statement below which immediately
assigns a value to val. I've no idea why people think local variables
need initialising in cases like this, but it seems to have become a
common pattern. I can only guess that someone is teaching this IMHO bad
practice.
> +
> + /*
> + * set LDO efuse: first temporarily store ANA_DAC_FILTER value from
> + * debug register as it will be reset once the ANA_LDO_EFUSE register
> + * is written to
> + */
> + val = at803x_debug_reg_read(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER);
> + at803x_debug_reg_mask(phydev, IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE,
> + IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK,
> + IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT);
> + at803x_debug_reg_write(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER, val);
> +
> + /* set 8023AZ CTRL values */
> + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_AZ_CTRL1,
> + IPQ5018_PHY_PCS_AZ_CTRL1_VAL);
> + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_AZ_CTRL2,
> + IPQ5018_PHY_PCS_AZ_CTRL2_VAL);
The comment doesn't help understand what's going on here, neither do the
register definition names.
Also, what interface modes on the host side does this PHY actually
support?
> + priv->rst = devm_reset_control_array_get_exclusive(dev);
> + if (IS_ERR_OR_NULL(priv->rst))
> + return dev_err_probe(dev, PTR_ERR(priv->rst),
> + "failed to acquire reset\n");
Why IS_ERR_OR_NULL() ? What error do you think will be returned by this
if priv->rst is NULL? (Hint: PTR_ERR(NULL) is 0.)
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
next prev parent reply other threads:[~2025-06-09 14:06 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-09 11:44 [PATCH v4 0/5] Add support for the IPQ5018 Internal GE PHY George Moussalem via B4 Relay
2025-06-09 11:44 ` [PATCH v4 1/5] clk: qcom: gcc-ipq5018: fix GE PHY reset George Moussalem via B4 Relay
2025-06-09 11:44 ` [PATCH v4 2/5] dt-bindings: net: qca,ar803x: Add IPQ5018 Internal GE PHY support George Moussalem via B4 Relay
2025-06-09 12:16 ` Andrew Lunn
2025-06-09 12:20 ` George Moussalem
2025-06-09 12:30 ` Andrew Lunn
2025-06-09 12:38 ` George Moussalem
2025-06-09 11:44 ` [PATCH v4 3/5] net: phy: qcom: at803x: Add Qualcomm IPQ5018 Internal " George Moussalem via B4 Relay
2025-06-09 12:24 ` Andrew Lunn
2025-06-09 12:53 ` George Moussalem
2025-06-09 14:05 ` Russell King (Oracle) [this message]
2025-06-10 7:31 ` George Moussalem
2025-06-09 11:44 ` [PATCH v4 4/5] arm64: dts: qcom: ipq5018: Add MDIO buses George Moussalem via B4 Relay
2025-06-09 11:44 ` [PATCH v4 5/5] arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus George Moussalem via B4 Relay
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