[PATCH v2] net: phy: realtek: convert RTL8226-CG to c45 only

[PATCH v2] net: phy: realtek: convert RTL8226-CG to c45 only

[Markus Stockhausen]

The RTL8226-CG can be found on devices like the Zyxel XGS1210-12. These
are driven by a Realtek RTL9302B SoC that has phy hardware polling
in the background. One must decide if a port is polled via c22 or c45.
Additionally the hardware disables MMD access in c22 mode. For reference
see mdio-realtek-rtl9300 driver. As this PHY is mostly used in Realtek
switches Convert the phy to a c45-only function set.

Because of these limitations the RTL8226 is not working at all in the
current switches. A "hacked" bus that toggles the mode for each c22/c45
access was used to get a "before status". But that is slow and producec
wrong results in the MAC polling status registers.

The RTL8226 seems to support proper MDIO_PMA_EXTABLE flags. So
genphy_c45_pma_read_abilities() can conveniently call
genphy_c45_pma_read_ext_abilities() and 10/100/1000 is populated right.

Outputs before:

Settings for lan9:
        Supported ports: [ TP MII ]
        Supported link modes:   10baseT/Half 10baseT/Full
                                100baseT/Half 100baseT/Full
                                1000baseT/Full
                                2500baseT/Full
        Supported pause frame use: Symmetric Receive-only
        Supports auto-negotiation: Yes
        Supported FEC modes: Not reported
        Advertised link modes:  10baseT/Half 10baseT/Full
                                100baseT/Half 100baseT/Full
                                1000baseT/Full
                                2500baseT/Full
        Advertised pause frame use: Symmetric Receive-only
        Advertised auto-negotiation: Yes
        Advertised FEC modes: Not reported
        Speed: Unknown!
        Duplex: Unknown! (255)
        Port: Twisted Pair
        PHYAD: 24
        Transceiver: external
        Auto-negotiation: on
        MDI-X: Unknown
        Supports Wake-on: d
        Wake-on: d
        Link detected: no

Outputs with this commit:

Settings for lan9:
        Supported ports: [ TP ]
        Supported link modes:   10baseT/Half 10baseT/Full
                                100baseT/Half 100baseT/Full
                                1000baseT/Full
                                2500baseT/Full
        Supported pause frame use: Symmetric Receive-only
        Supports auto-negotiation: Yes
        Supported FEC modes: Not reported
        Advertised link modes:  10baseT/Half 10baseT/Full
                                100baseT/Half 100baseT/Full
                                1000baseT/Full
                                2500baseT/Full
        Advertised pause frame use: Symmetric Receive-only
        Advertised auto-negotiation: Yes
        Advertised FEC modes: Not reported
        Speed: Unknown!
        Duplex: Unknown! (255)
        Port: Twisted Pair
        PHYAD: 24
        Transceiver: external
        Auto-negotiation: on
        MDI-X: Unknown
        Supports Wake-on: d
        Wake-on: d
        Link detected: no

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
---
Changes in v2:
- Added before/after status in commit message

---
 drivers/net/phy/realtek/realtek_main.c | 26 +++++++++++++++++++++-----
 1 file changed, 21 insertions(+), 5 deletions(-)

diff --git a/drivers/net/phy/realtek/realtek_main.c b/drivers/net/phy/realtek/realtek_main.c
index dd0d675149ad..8bc68b31cd31 100644
--- a/drivers/net/phy/realtek/realtek_main.c
+++ b/drivers/net/phy/realtek/realtek_main.c
@@ -1280,6 +1280,21 @@ static int rtl822x_c45_read_status(struct phy_device *phydev)
 	return 0;
 }
 
+static int rtl822x_c45_soft_reset(struct phy_device *phydev)
+{
+	int ret, val;
+
+	ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
+			     MDIO_CTRL1_RESET, MDIO_CTRL1_RESET);
+	if (ret < 0)
+		return ret;
+
+	return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD,
+					 MDIO_CTRL1, val,
+					 !(val & MDIO_CTRL1_RESET),
+					 5000, 100000, true);
+}
+
 static int rtl822xb_c45_read_status(struct phy_device *phydev)
 {
 	int ret;
@@ -1675,11 +1690,12 @@ static struct phy_driver realtek_drvs[] = {
 	}, {
 		PHY_ID_MATCH_EXACT(0x001cc838),
 		.name           = "RTL8226-CG 2.5Gbps PHY",
-		.get_features   = rtl822x_get_features,
-		.config_aneg    = rtl822x_config_aneg,
-		.read_status    = rtl822x_read_status,
-		.suspend        = genphy_suspend,
-		.resume         = rtlgen_resume,
+		.soft_reset     = rtl822x_c45_soft_reset,
+		.get_features   = rtl822x_c45_get_features,
+		.config_aneg    = rtl822x_c45_config_aneg,
+		.read_status    = rtl822x_c45_read_status,
+		.suspend        = genphy_c45_pma_suspend,
+		.resume         = rtlgen_c45_resume,
 		.read_page      = rtl821x_read_page,
 		.write_page     = rtl821x_write_page,
 	}, {
-- 
2.47.0

Re: [PATCH v2] net: phy: realtek: convert RTL8226-CG to c45 only

[Daniel Golle]

On Thu, Jul 31, 2025 at 01:44:45AM -0400, Markus Stockhausen wrote:
> The RTL8226-CG can be found on devices like the Zyxel XGS1210-12. These
> are driven by a Realtek RTL9302B SoC that has phy hardware polling
> in the background. One must decide if a port is polled via c22 or c45.
> Additionally the hardware disables MMD access in c22 mode. For reference
> see mdio-realtek-rtl9300 driver. As this PHY is mostly used in Realtek
> switches Convert the phy to a c45-only function set.
> 
> [...]
> diff --git a/drivers/net/phy/realtek/realtek_main.c b/drivers/net/phy/realtek/realtek_main.c
> index dd0d675149ad..8bc68b31cd31 100644
> --- a/drivers/net/phy/realtek/realtek_main.c
> +++ b/drivers/net/phy/realtek/realtek_main.c
> [...]
> @@ -1675,11 +1690,12 @@ static struct phy_driver realtek_drvs[] = {
>  	}, {
>  		PHY_ID_MATCH_EXACT(0x001cc838),
>  		.name           = "RTL8226-CG 2.5Gbps PHY",
> -		.get_features   = rtl822x_get_features,
> -		.config_aneg    = rtl822x_config_aneg,
> -		.read_status    = rtl822x_read_status,
> -		.suspend        = genphy_suspend,
> -		.resume         = rtlgen_resume,
> +		.soft_reset     = rtl822x_c45_soft_reset,
> +		.get_features   = rtl822x_c45_get_features,
> +		.config_aneg    = rtl822x_c45_config_aneg,
> +		.read_status    = rtl822x_c45_read_status,
> +		.suspend        = genphy_c45_pma_suspend,
> +		.resume         = rtlgen_c45_resume,
>  		.read_page      = rtl821x_read_page,
>  		.write_page     = rtl821x_write_page,

I suppose .read_page and .write_page can then be dropped as well as paged
Clause-22 access is no longer needed, right?

AW: [PATCH v2] net: phy: realtek: convert RTL8226-CG to c45 only

[markus.stockhausen]

Von: Daniel Golle <daniel@makrotopia.org> 
Gesendet: Donnerstag, 31. Juli 2025 11:24

> >  		.read_page      = rtl821x_read_page,
> >  		.write_page     = rtl821x_write_page,
> 
> I suppose .read_page and .write_page can then be dropped as well as paged
> Clause-22 access is no longer needed, right?

Totally ok for me. If no one complains will send a v3.

Markus

Re: [PATCH v2] net: phy: realtek: convert RTL8226-CG to c45 only

[Heiner Kallweit]

On 31.07.2025 07:44, Markus Stockhausen wrote:
> The RTL8226-CG can be found on devices like the Zyxel XGS1210-12. These
> are driven by a Realtek RTL9302B SoC that has phy hardware polling
> in the background. One must decide if a port is polled via c22 or c45.
> Additionally the hardware disables MMD access in c22 mode. For reference

For my understanding: Which hardware disables c22 MMD access on RTL8226 how?
RTL930x configures RTL8226 in a way that is doesn't accept c45 over c22
any longer?

> see mdio-realtek-rtl9300 driver. As this PHY is mostly used in Realtek
> switches Convert the phy to a c45-only function set.
> 
> Because of these limitations the RTL8226 is not working at all in the
> current switches. A "hacked" bus that toggles the mode for each c22/c45
> access was used to get a "before status". But that is slow and producec
> wrong results in the MAC polling status registers.
> 
> The RTL8226 seems to support proper MDIO_PMA_EXTABLE flags. So
> genphy_c45_pma_read_abilities() can conveniently call
> genphy_c45_pma_read_ext_abilities() and 10/100/1000 is populated right.
> 
> Outputs before:
> 
> Settings for lan9:
>         Supported ports: [ TP MII ]
>         Supported link modes:   10baseT/Half 10baseT/Full
>                                 100baseT/Half 100baseT/Full
>                                 1000baseT/Full
>                                 2500baseT/Full
>         Supported pause frame use: Symmetric Receive-only
>         Supports auto-negotiation: Yes
>         Supported FEC modes: Not reported
>         Advertised link modes:  10baseT/Half 10baseT/Full
>                                 100baseT/Half 100baseT/Full
>                                 1000baseT/Full
>                                 2500baseT/Full
>         Advertised pause frame use: Symmetric Receive-only
>         Advertised auto-negotiation: Yes
>         Advertised FEC modes: Not reported
>         Speed: Unknown!
>         Duplex: Unknown! (255)
>         Port: Twisted Pair
>         PHYAD: 24
>         Transceiver: external
>         Auto-negotiation: on
>         MDI-X: Unknown
>         Supports Wake-on: d
>         Wake-on: d
>         Link detected: no
> 
> Outputs with this commit:
> 
> Settings for lan9:
>         Supported ports: [ TP ]
>         Supported link modes:   10baseT/Half 10baseT/Full
>                                 100baseT/Half 100baseT/Full
>                                 1000baseT/Full
>                                 2500baseT/Full
>         Supported pause frame use: Symmetric Receive-only
>         Supports auto-negotiation: Yes
>         Supported FEC modes: Not reported
>         Advertised link modes:  10baseT/Half 10baseT/Full
>                                 100baseT/Half 100baseT/Full
>                                 1000baseT/Full
>                                 2500baseT/Full
>         Advertised pause frame use: Symmetric Receive-only
>         Advertised auto-negotiation: Yes
>         Advertised FEC modes: Not reported
>         Speed: Unknown!
>         Duplex: Unknown! (255)
>         Port: Twisted Pair
>         PHYAD: 24
>         Transceiver: external
>         Auto-negotiation: on
>         MDI-X: Unknown
>         Supports Wake-on: d
>         Wake-on: d
>         Link detected: no
> 
> Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
> ---
> Changes in v2:
> - Added before/after status in commit message
> 
> ---
>  drivers/net/phy/realtek/realtek_main.c | 26 +++++++++++++++++++++-----
>  1 file changed, 21 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/net/phy/realtek/realtek_main.c b/drivers/net/phy/realtek/realtek_main.c
> index dd0d675149ad..8bc68b31cd31 100644
> --- a/drivers/net/phy/realtek/realtek_main.c
> +++ b/drivers/net/phy/realtek/realtek_main.c
> @@ -1280,6 +1280,21 @@ static int rtl822x_c45_read_status(struct phy_device *phydev)
>  	return 0;
>  }
>  
> +static int rtl822x_c45_soft_reset(struct phy_device *phydev)
> +{
> +	int ret, val;
> +
> +	ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1,
> +			     MDIO_CTRL1_RESET, MDIO_CTRL1_RESET);
> +	if (ret < 0)
> +		return ret;
> +
> +	return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PMAPMD,
> +					 MDIO_CTRL1, val,
> +					 !(val & MDIO_CTRL1_RESET),
> +					 5000, 100000, true);
> +}
> +
>  static int rtl822xb_c45_read_status(struct phy_device *phydev)
>  {
>  	int ret;
> @@ -1675,11 +1690,12 @@ static struct phy_driver realtek_drvs[] = {
>  	}, {
>  		PHY_ID_MATCH_EXACT(0x001cc838),
>  		.name           = "RTL8226-CG 2.5Gbps PHY",
> -		.get_features   = rtl822x_get_features,
> -		.config_aneg    = rtl822x_config_aneg,
> -		.read_status    = rtl822x_read_status,
> -		.suspend        = genphy_suspend,
> -		.resume         = rtlgen_resume,
> +		.soft_reset     = rtl822x_c45_soft_reset,
> +		.get_features   = rtl822x_c45_get_features,
> +		.config_aneg    = rtl822x_c45_config_aneg,
> +		.read_status    = rtl822x_c45_read_status,
> +		.suspend        = genphy_c45_pma_suspend,
> +		.resume         = rtlgen_c45_resume,
>  		.read_page      = rtl821x_read_page,
>  		.write_page     = rtl821x_write_page,
>  	}, {

AW: [PATCH v2] net: phy: realtek: convert RTL8226-CG to c45 only

[markus.stockhausen]

Hi Heiner,

> Von: Heiner Kallweit <hkallweit1@gmail.com> 
> Gesendet: Donnerstag, 31. Juli 2025 12:25
>
> On 31.07.2025 07:44, Markus Stockhausen wrote:
> > The RTL8226-CG can be found on devices like the Zyxel XGS1210-12. 
> > These are driven by a Realtek RTL9302B SoC that has phy hardware 
> > polling in the background. One must decide if a port is polled via c22 or c45.
> > Additionally the hardware disables MMD access in c22 mode. For 
> > reference
>
> For my understanding: Which hardware disables c22 MMD access on RTL8226 how?
> RTL930x configures RTL8226 in a way that is doesn't accept c45 over c22 any longer?

sorry to be not clear about this. We have rtl9300 mdio driver
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree
/drivers/net/mdio/mdio-realtek-rtl9300.c?h=v6.16

This must decide how its four smi busses are configured. Either c22 
or c45. https://svanheule.net/realtek/longan/register/smi_glb_ctrl 
So it does.

	/* Put the interfaces into C45 mode if required */
	glb_ctrl_mask = GENMASK(19, 16);
	for (i = 0; i < MAX_SMI_BUSSES; i++)
		if (priv->smi_bus_is_c45[i])
			glb_ctrl_val |= GLB_CTRL_INTF_SEL(i);
	...
	err = regmap_update_bits(regmap, SMI_GLB_CTRL,
				 glb_ctrl_mask, glb_ctrl_val);

As soon as this bit is set to one mode the bus will block most
accesses with the other mode. E.g. In c22 mode registers 13/14
are a dead end. So the only option for the bus is to limit access
like this.

	bus->name = "Realtek Switch MDIO Bus";
	if (priv->smi_bus_is_c45[mdio_bus]) {
		bus->read_c45 = rtl9300_mdio_read_c45;
		bus->write_c45 =  rtl9300_mdio_write_c45;
	} else {
		bus->read = rtl9300_mdio_read_c22;
		bus->write = rtl9300_mdio_write_c22;
	}

Markus

Re: [PATCH v2] net: phy: realtek: convert RTL8226-CG to c45 only

[Andrew Lunn]

> > For my understanding: Which hardware disables c22 MMD access on RTL8226 how?
> > RTL930x configures RTL8226 in a way that is doesn't accept c45 over c22 any longer?
> 
> sorry to be not clear about this. We have rtl9300 mdio driver
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree
> /drivers/net/mdio/mdio-realtek-rtl9300.c?h=v6.16
> 
> This must decide how its four smi busses are configured. Either c22 
> or c45. https://svanheule.net/realtek/longan/register/smi_glb_ctrl 
> So it does.
> 
> 	/* Put the interfaces into C45 mode if required */
> 	glb_ctrl_mask = GENMASK(19, 16);
> 	for (i = 0; i < MAX_SMI_BUSSES; i++)
> 		if (priv->smi_bus_is_c45[i])
> 			glb_ctrl_val |= GLB_CTRL_INTF_SEL(i);
> 	...
> 	err = regmap_update_bits(regmap, SMI_GLB_CTRL,
> 				 glb_ctrl_mask, glb_ctrl_val);
> 
> As soon as this bit is set to one mode the bus will block most
> accesses with the other mode. E.g. In c22 mode registers 13/14
> are a dead end. So the only option for the bus is to limit access
> like this.
> 
> 	bus->name = "Realtek Switch MDIO Bus";
> 	if (priv->smi_bus_is_c45[mdio_bus]) {
> 		bus->read_c45 = rtl9300_mdio_read_c45;
> 		bus->write_c45 =  rtl9300_mdio_write_c45;
> 	} else {
> 		bus->read = rtl9300_mdio_read_c22;
> 		bus->write = rtl9300_mdio_write_c22;
> 	}

Please summaries this for in the commit message. Not using C22 in the
driver is only part of the overall picture. In phylib, there are a
number of places in core where if an op is not provided by the driver,
it will fall back to a genphy_ helper which will do a C22 access. It
would be good if the commit message made is clear this has been
considered, and that such operations will fail because the MDIO driver
itself does not support C22.

	Andrew

Re: AW: [PATCH v2] net: phy: realtek: convert RTL8226-CG to c45 only

[Russell King (Oracle)]

On Thu, Jul 31, 2025 at 12:55:40PM +0200, markus.stockhausen@gmx.de wrote:
> As soon as this bit is set to one mode the bus will block most
> accesses with the other mode. E.g. In c22 mode registers 13/14
> are a dead end. So the only option for the bus is to limit access
> like this.

Why would a bus implementation block access to clause 22 registers
13/14 when operating in clause 22 mode? Or is the above badly phrased?

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

Re: AW: [PATCH v2] net: phy: realtek: convert RTL8226-CG to c45 only

[Daniel Golle]

On Thu, Jul 31, 2025 at 03:01:21PM +0100, Russell King (Oracle) wrote:
> On Thu, Jul 31, 2025 at 12:55:40PM +0200, markus.stockhausen@gmx.de wrote:
> > As soon as this bit is set to one mode the bus will block most
> > accesses with the other mode. E.g. In c22 mode registers 13/14
> > are a dead end. So the only option for the bus is to limit access
> > like this.
> 
> Why would a bus implementation block access to clause 22 registers
> 13/14 when operating in clause 22 mode? Or is the above badly phrased?

No, you understood correctly. Sadly.

RealTek's MDIO controller is a highly abstracted beast, with many
assumptions regarding the meaning of each register. It is NOT a generic
MDIO host controller, but rather quite specific to the way registers are
defined for Ethernet PHYs. As such, it "offloads" things like
MMD-over-C22 as well as C22 register pages (always assuming register 0x1f
is the page selector).
Further down the road it does provide specific calls for MMD-over-C22
which the current driver is not using -- it could, however, be implemented
by intercepting access to registers 13 and 14 in the MDIO controller
driver, storing device and register addresses in the driver's priv struct
and using hardware-assisted MMD-over-C22 API when ever an MMD read or
write operation is requested (ie. the final access to MII_MMD_DATA).

A similar logic is already implemented for page selection and RealTek-specific
PHY package port selection mechanisms, see

https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.c;h=5c6d79d19b598bbb2f5b74c3d25f5cf3ee077096;hb=HEAD#l2084

The same could be implemented in mdio-realtek-rtl9300.c, and similarly also
MMD-over-C22 could be implemented.