Re: Aquantia PHY in OCSGMII mode?

Vladimir Oltean
2025-08-04T10:01:44Z

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On Mon, Aug 04, 2025 at 08:17:47AM +0200, Alexander Wilhelm wrote:
> Am Fri, Aug 01, 2025 at 04:04:20PM +0300 schrieb Vladimir Oltean:
> > On Fri, Aug 01, 2025 at 01:23:44PM +0100, Russell King (Oracle) wrote:
> > > It looks like memac_select_pcs() and memac_prepare() fail to
> > > handle 2500BASEX despite memac_initialization() suggesting the
> > > SGMII PCS supports 2500BASEX.
> >
> > Thanks for pointing this out, it seems to be a regression introduced by
> > commit 5d93cfcf7360 ("net: dpaa: Convert to phylink").
> >
> > If there are no other volunteers, I can offer to submit a patch if
> > Alexander confirms this fixes his setup.
>
> I'd be happy to help by applying the patch on my system and running some tests.
> Please let me know if there are any specific steps or scenarios you'd like me to
> focus on.
>
> Best regards
> Alexander Wilhelm

Please find the attached patch.

You should only need something like below (assuming LS1046A fm1-mac9,
may be different in your case) in your board device tree:

ethernet@f0000 { /* 10GEC1 */
phy-handle = <&aqr115_phy>;
phy-connection-type = "2500base-x";
};

because the pcsphy-handle should have already been added by qoriq-fman3-0-10g-0.dtsi
or fsl-ls1046-post.dtsi.

For debugging, I recommend dumping /proc/device-tree/soc/fman@1a00000/ethernet@f0000/
(node may change for different MAC) to make sure that all the required
properties are there, i.e. phy-handle, phy-connection-type, pcsphy-handle.
Either inspect the device tree through the filesystem, or save it to a
text file using "dtc -I fs -O dts -o running.dts /proc/device-tree/".

I especially recommend instrumenting the live device tree, because I
don't know what bootloader version you are using, and whether it has
device tree fixups enabled (which mainly add status = "disabled" to
unused FMan ports, but also change the phy-connection-type in some cases).

managed = "in-band-status" is not needed and should not be added. The
PCS only supports LINK_INBAND_DISABLE for 2500base-x.

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From 2b4d48c93d317cccafc8128e33f18fab244d5bce Mon Sep 17 00:00:00 2001
From: Vladimir Oltean <vladimir.oltean@nxp.com>
Date: Mon, 4 Aug 2025 11:15:26 +0300
Subject: [PATCH] net: dpaa: fman_memac: complete phylink support with
2500base-x

The DPAA phylink conversion in the following commits partially developed
code for handling the 2500base-x host interface mode (called "2.5G
SGMII" in LS1043A/LS1046A reference manuals).

- 0fc83bd79589 ("net: fman: memac: Add serdes support")
- 5d93cfcf7360 ("net: dpaa: Convert to phylink")

In principle, having phy-interface-mode = "2500base-x" and a pcsphy-handle
(unnamed or with pcs-handle-names = "sgmii") in the MAC device tree node
results in PHY_INTERFACE_MODE_2500BASEX being set in phylink_config ::
supported_interfaces, but this isn't sufficient.

Because memac_select_pcs() returns no PCS for PHY_INTERFACE_MODE_2500BASEX,
the Lynx PCS code never engages. There's a chance the PCS driver doesn't
have any configuration to change for 2500base-x fixed-link (based on
bootloader pre-initialization), but there's an even higher chance that
this is not the case, and the PCS remains misconfigured.

More importantly, memac_if_mode() does not handle
PHY_INTERFACE_MODE_2500BASEX, and it should be telling the mEMAC to
configure itself in GMII mode (which is upclocked by the PCS). Currently
it prints a WARN_ON() and returns zero, aka IF_MODE_10G (incorrect).

The additional case statement in memac_prepare() for calling
phy_set_mode_ext() does not make any difference, because there is no
generic PHY driver for the Lynx 10G SerDes from LS1043A/LS1046A. But we
add it nonetheless, for consistency.

Regarding the question "did 2500base-x ever work with the FMan mEMAC
mainline code prior to the phylink conversion?" - the answer is more
nuanced.

For context, the previous phylib-based implementation was unable to
describe the fixed-link speed as 2500, because the software PHY
implementation is limited to 1G. However, improperly describing the link
as an sgmii fixed-link with speed = <1000> would have resulted in a
functional 2.5G speed, because there is no other difference than the
SerDes lane clock net frequency (3.125 GHz for 2500base-x) - all the
other higher-level settings are the same, and the SerDes lane frequency
is currently handled by the RCW.

But this hack cannot be extended towards a phylib PHY such as Aquantia
operating in OCSGMII, because the latter requires phy-mode = "2500base-x",
which the mEMAC driver did not support prior to the phylink conversion.
So I do not really consider this a regression, just completing support
for a missing feature.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
drivers/net/ethernet/freescale/fman/fman_memac.c | 3 +++
1 file changed, 3 insertions(+)

diff --git a/drivers/net/ethernet/freescale/fman/fman_memac.c b/drivers/net/ethernet/freescale/fman/fman_memac.c
index 0291093f2e4e..b3e25234512e 100644
--- a/drivers/net/ethernet/freescale/fman/fman_memac.c
+++ b/drivers/net/ethernet/freescale/fman/fman_memac.c
@@ -649,6 +649,7 @@ static u32 memac_if_mode(phy_interface_t interface)
return IF_MODE_GMII | IF_MODE_RGMII;
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
case PHY_INTERFACE_MODE_QSGMII:
return IF_MODE_GMII;
case PHY_INTERFACE_MODE_10GBASER:
@@ -667,6 +668,7 @@ static struct phylink_pcs *memac_select_pcs(struct phylink_config *config,
switch (iface) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
return memac->sgmii_pcs;
case PHY_INTERFACE_MODE_QSGMII:
return memac->qsgmii_pcs;
@@ -685,6 +687,7 @@ static int memac_prepare(struct phylink_config *config, unsigned int mode,
switch (iface) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
case PHY_INTERFACE_MODE_QSGMII:
case PHY_INTERFACE_MODE_10GBASER:
return phy_set_mode_ext(memac->serdes, PHY_MODE_ETHERNET,
--
2.43.0