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Tue, 12 Aug 2025 15:42:20 +0000 Date: Tue, 12 Aug 2025 17:42:10 +0200 From: Maciej Fijalkowski To: Jason Xing CC: , , , , , , , , , , , , Jason Xing Subject: Re: [PATCH iwl-net v2 3/3] ixgbe: xsk: support batched xsk Tx interfaces to increase performance Message-ID: References: <20250812075504.60498-1-kerneljasonxing@gmail.com> <20250812075504.60498-4-kerneljasonxing@gmail.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20250812075504.60498-4-kerneljasonxing@gmail.com> X-ClientProxiedBy: DU2PR04CA0271.eurprd04.prod.outlook.com (2603:10a6:10:28c::6) To DM4PR11MB6117.namprd11.prod.outlook.com (2603:10b6:8:b3::19) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM4PR11MB6117:EE_|SJ0PR11MB7155:EE_ X-MS-Office365-Filtering-Correlation-Id: f6b979fa-25db-4c2e-669b-08ddd9b6d319 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|7416014|376014; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?jbF8x8nSlON4eRzaSGO6G2gtRVpuI1F5BhIHkZPaZj+b8vW+IOCr099I3kW6?= =?us-ascii?Q?uT7ByFKpwCTCTunnZdPM4KopzRWsVksivonnBlf5dtMIGKxGkR6uVyjr3tHN?= =?us-ascii?Q?fjQzuKhOF40iukkpCkAmGnrdwOSUb1o0ROrCii3L0zaOfY/ho6tX3Bla/TXv?= =?us-ascii?Q?wo8R0M5uWMIcrPifGdEleMwEByfWIJu4XxovrIM38fCKr7hP3WFbbTuQjxgA?= =?us-ascii?Q?VTsqk6pF7wur4ogzcYLpFo6lfxAPsd8R0rW2hDwZaipQCjso8a+yeHNjbfJw?= =?us-ascii?Q?ZwfYGb0o+BVCQUb2x6orwvAgIHmeuapJIyol2zymg+U1byg15+XwoQnlQkVL?= =?us-ascii?Q?zd2BKx7O9j5LJ7U2EZr74OoRgU495xl949zzH3FqnJmh0uI/zclgm7xX5Pec?= =?us-ascii?Q?1JJvk9eN8cBkr6Rz9TwS9yVPCDCre74yEJec+c75XQdPXj71y4caoDEsZZDx?= =?us-ascii?Q?NaDDZh0pFIZtPdJwtl5PLTCRmMO2ztectlIR8I1Sxy4SZC43F1O9tE35VaCf?= =?us-ascii?Q?YaVx9A5IGVclcoJrz321zGeIxxInMF0Xku4FddMoxzcrowrk2DrpSInrdwr3?= =?us-ascii?Q?Wb0uml1OxJKlWepdVWCMmK2t2tkMQ1mMNvW9R4RfeniyPSAxiuBg/Z8bXFyF?= =?us-ascii?Q?8YOcsrcYcmBUzlg6MY5c1y7SrGbqMKwsujtHW8lXScwEEkJoPDMqrf2Twn0P?= =?us-ascii?Q?gTLX32NwTdLGAm5O6dAAOqUegalXVErqmkll1mvzecO0ImuXYPpkOYvTm/je?= =?us-ascii?Q?lgX5bGHr+s8teyd+q8ZOe8/4MqoIb8TKVRacCJ9cyhl03KL6Jo9dORENo8z2?= =?us-ascii?Q?7319TlStUC4l6oBChVVAuKNff/dolSzkJdUShd7K29302+8aWoYQjJD2M+vl?= =?us-ascii?Q?cX2GJtIjgE15wqz59hHA4hILUk2aLLIb0sahWCRhJl+7a5GoPMdc2V85owmB?= =?us-ascii?Q?j1DmQ9HOz578n66HH6gh4NZuefy/jFcuLsFA+CSI/3Ayh58lH2ror9wNMOV8?= =?us-ascii?Q?hO4H2SXLXuJ9ZiuYHG7O2v6RRkw4wAEqN2ddUqrR8YRjixipXLsXQJQrnpRT?= =?us-ascii?Q?erDL3XG5r317LfTBItsQqQT8b4sPfOXIrrtTJ1hktbxZfV5ul9gxcbcWyZvX?= =?us-ascii?Q?CYzAg4stlA+tZVy6AQr6HgbVIYnSiGX+nTdmF7oLjtUR+nmOZNw3sTvLfg58?= =?us-ascii?Q?vK+8U9J3ZVyPXilM/G914b0ztSKPLWim1vdy9vCud69WBNpn5t6p7220E3NQ?= =?us-ascii?Q?Eehvw65zbivcoq1fQdXTA5j5n3816E6hak/803y7exVN19j5OCfVr5U/8f+k?= =?us-ascii?Q?TmHYS1P+OChbFbyN1BEWTMXAo7QXwujLl3bUyK6mN6eSEF196uwiLKMzGgpc?= =?us-ascii?Q?kBhBENZ57KvpT0M2WwoyaRoHgAjTAUeAXcYe+cBZyA9kMa9xtK9v0Yv4feI5?= =?us-ascii?Q?XlK+xT26Txx39ypr43c0dBII9epbmlZU3Rt0PerfJLnDjXH+qtPbgeBY4WF8?= =?us-ascii?Q?X9EioTSB+8I3QmH78viTXOrGcf0dOYlbeuoIohLTutlgFg6gybvwlMoSEElT?= =?us-ascii?Q?CtRxnV1yytkTfrVxnvUzVcZ6N5erOWPWekLWfPih6jPRgtkPWC/YBy3sZl14?= =?us-ascii?Q?QA=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: f6b979fa-25db-4c2e-669b-08ddd9b6d319 X-MS-Exchange-CrossTenant-AuthSource: DM4PR11MB6117.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Aug 2025 15:42:20.7604 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: YmXls5PM3ztGDPQxFhuWeEdBgy1K9aZ9PIb3buQKvXPMVJD5VhIZmxgt/WXyPxqoJNZZtlxBNsOEyyZKEtoRmKfDrugChP5Ms8C+QPo+0BY= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR11MB7155 X-OriginatorOrg: intel.com On Tue, Aug 12, 2025 at 03:55:04PM +0800, Jason Xing wrote: > From: Jason Xing > Hi Jason, patches should be targetted at iwl-next as these are improvements, not fixes. > Like what i40e driver initially did in commit 3106c580fb7cf > ("i40e: Use batched xsk Tx interfaces to increase performance"), use > the batched xsk feature to transmit packets. > > Signed-off-by: Jason Xing > --- > In this version, I still choose use the current implementation. Last > time at the first glance, I agreed 'i' is useless but it is not. > https://lore.kernel.org/intel-wired-lan/CAL+tcoADu-ZZewsZzGDaL7NugxFTWO_Q+7WsLHs3Mx-XHjJnyg@mail.gmail.com/ dare to share the performance improvement (if any, in the current form)? also you have not mentioned in v1->v2 that you dropped the setting of xdp_zc_max_segs, which is a step in a correct path. > --- > drivers/net/ethernet/intel/ixgbe/ixgbe_xsk.c | 106 +++++++++++++------ > 1 file changed, 72 insertions(+), 34 deletions(-) > > diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_xsk.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_xsk.c > index f3d3f5c1cdc7..9fe2c4bf8bc5 100644 > --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_xsk.c > +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_xsk.c > @@ -2,12 +2,15 @@ > /* Copyright(c) 2018 Intel Corporation. */ > > #include > +#include > #include > #include > > #include "ixgbe.h" > #include "ixgbe_txrx_common.h" > > +#define PKTS_PER_BATCH 4 > + > struct xsk_buff_pool *ixgbe_xsk_pool(struct ixgbe_adapter *adapter, > struct ixgbe_ring *ring) > { > @@ -388,58 +391,93 @@ void ixgbe_xsk_clean_rx_ring(struct ixgbe_ring *rx_ring) > } > } > > -static bool ixgbe_xmit_zc(struct ixgbe_ring *xdp_ring, unsigned int budget) > +static void ixgbe_set_rs_bit(struct ixgbe_ring *xdp_ring) > +{ > + u16 ntu = xdp_ring->next_to_use ? xdp_ring->next_to_use - 1 : xdp_ring->count - 1; > + union ixgbe_adv_tx_desc *tx_desc; > + > + tx_desc = IXGBE_TX_DESC(xdp_ring, ntu); > + tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD_RS); you have not addressed the descriptor cleaning path which makes this change rather pointless or even the driver behavior is broken. point of such change is to limit the interrupts raised by HW once it is done with sending the descriptor. you still walk the descs one-by-one in ixgbe_clean_xdp_tx_irq(). > +} > + > +static void ixgbe_xmit_pkt(struct ixgbe_ring *xdp_ring, struct xdp_desc *desc, > + int i) > + > { > struct xsk_buff_pool *pool = xdp_ring->xsk_pool; > union ixgbe_adv_tx_desc *tx_desc = NULL; > struct ixgbe_tx_buffer *tx_bi; > - struct xdp_desc desc; > dma_addr_t dma; > u32 cmd_type; > > - if (!budget) > - return true; > + dma = xsk_buff_raw_get_dma(pool, desc[i].addr); > + xsk_buff_raw_dma_sync_for_device(pool, dma, desc[i].len); > > - while (likely(budget)) { > - if (!netif_carrier_ok(xdp_ring->netdev)) > - break; > + tx_bi = &xdp_ring->tx_buffer_info[xdp_ring->next_to_use]; > + tx_bi->bytecount = desc[i].len; > + tx_bi->xdpf = NULL; > + tx_bi->gso_segs = 1; > > - if (!xsk_tx_peek_desc(pool, &desc)) > - break; > + tx_desc = IXGBE_TX_DESC(xdp_ring, xdp_ring->next_to_use); > + tx_desc->read.buffer_addr = cpu_to_le64(dma); > > - dma = xsk_buff_raw_get_dma(pool, desc.addr); > - xsk_buff_raw_dma_sync_for_device(pool, dma, desc.len); > + cmd_type = IXGBE_ADVTXD_DTYP_DATA | > + IXGBE_ADVTXD_DCMD_DEXT | > + IXGBE_ADVTXD_DCMD_IFCS; > + cmd_type |= desc[i].len | IXGBE_TXD_CMD_EOP; > + tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); > + tx_desc->read.olinfo_status = > + cpu_to_le32(desc[i].len << IXGBE_ADVTXD_PAYLEN_SHIFT); > > - tx_bi = &xdp_ring->tx_buffer_info[xdp_ring->next_to_use]; > - tx_bi->bytecount = desc.len; > - tx_bi->xdpf = NULL; > - tx_bi->gso_segs = 1; > + xdp_ring->next_to_use++; > +} > > - tx_desc = IXGBE_TX_DESC(xdp_ring, xdp_ring->next_to_use); > - tx_desc->read.buffer_addr = cpu_to_le64(dma); > +static void ixgbe_xmit_pkt_batch(struct ixgbe_ring *xdp_ring, struct xdp_desc *desc) > +{ > + u32 i; > > - /* put descriptor type bits */ > - cmd_type = IXGBE_ADVTXD_DTYP_DATA | > - IXGBE_ADVTXD_DCMD_DEXT | > - IXGBE_ADVTXD_DCMD_IFCS; > - cmd_type |= desc.len | IXGBE_TXD_CMD; > - tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); > - tx_desc->read.olinfo_status = > - cpu_to_le32(desc.len << IXGBE_ADVTXD_PAYLEN_SHIFT); > + unrolled_count(PKTS_PER_BATCH) > + for (i = 0; i < PKTS_PER_BATCH; i++) > + ixgbe_xmit_pkt(xdp_ring, desc, i); > +} > > - xdp_ring->next_to_use++; > - if (xdp_ring->next_to_use == xdp_ring->count) > - xdp_ring->next_to_use = 0; > +static void ixgbe_fill_tx_hw_ring(struct ixgbe_ring *xdp_ring, > + struct xdp_desc *descs, u32 nb_pkts) > +{ > + u32 batched, leftover, i; > + > + batched = nb_pkts & ~(PKTS_PER_BATCH - 1); > + leftover = nb_pkts & (PKTS_PER_BATCH - 1); > + for (i = 0; i < batched; i += PKTS_PER_BATCH) > + ixgbe_xmit_pkt_batch(xdp_ring, &descs[i]); > + for (i = batched; i < batched + leftover; i++) > + ixgbe_xmit_pkt(xdp_ring, &descs[i], 0); > +} > > - budget--; > - } > +static bool ixgbe_xmit_zc(struct ixgbe_ring *xdp_ring, unsigned int budget) > +{ > + struct xdp_desc *descs = xdp_ring->xsk_pool->tx_descs; > + u32 nb_pkts, nb_processed = 0; > > - if (tx_desc) { > - ixgbe_xdp_ring_update_tail(xdp_ring); > - xsk_tx_release(pool); > + if (!netif_carrier_ok(xdp_ring->netdev)) > + return true; > + > + nb_pkts = xsk_tx_peek_release_desc_batch(xdp_ring->xsk_pool, budget); > + if (!nb_pkts) > + return true; > + > + if (xdp_ring->next_to_use + nb_pkts >= xdp_ring->count) { > + nb_processed = xdp_ring->count - xdp_ring->next_to_use; > + ixgbe_fill_tx_hw_ring(xdp_ring, descs, nb_processed); > + xdp_ring->next_to_use = 0; > } > > - return !!budget; > + ixgbe_fill_tx_hw_ring(xdp_ring, &descs[nb_processed], nb_pkts - nb_processed); > + > + ixgbe_set_rs_bit(xdp_ring); > + ixgbe_xdp_ring_update_tail(xdp_ring); > + > + return nb_pkts < budget; > } > > static void ixgbe_clean_xdp_tx_buffer(struct ixgbe_ring *tx_ring, > -- > 2.41.3 >