* [PATCH net-next 1/4] net: stmmac: rk: replace HIWORD_UPDATE() with GRF_FIELD()
2025-11-13 17:46 [PATCH net-next 0/4] net: stmmac: rk: use PHY_INTF_SEL_x Russell King (Oracle)
@ 2025-11-13 17:46 ` Russell King (Oracle)
2025-11-14 8:19 ` Maxime Chevallier
2025-11-13 17:46 ` [PATCH net-next 2/4] net: stmmac: rk: convert all bitfields to GRF_FIELD*() Russell King (Oracle)
` (3 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Russell King (Oracle) @ 2025-11-13 17:46 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, Maxime Coquelin, netdev, Paolo Abeni
Provide GRF_FIELD() which takes the high/low bit numbers of the field
and field value, generates the mask and passes it to FIELD_PREP_WM16.
Replace all HIWORD_UPDATE() instances with this.
No change to produced code on aarch64.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 64 +++++++++----------
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index a5c7e03ebc63..794a7ed71451 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -149,11 +149,11 @@ static int rk_set_clk_mac_speed(struct rk_priv_data *bsp_priv,
return clk_set_rate(clk_mac_speed, rate);
}
-#define HIWORD_UPDATE(val, mask, shift) \
- (FIELD_PREP_WM16((mask) << (shift), (val)))
+#define GRF_FIELD(hi, lo, val) \
+ FIELD_PREP_WM16(GENMASK_U16(hi, lo), val)
-#define GRF_BIT(nr) (BIT(nr) | BIT(nr+16))
-#define GRF_CLR_BIT(nr) (BIT(nr+16))
+#define GRF_BIT(nr) (BIT(nr) | BIT(nr+16))
+#define GRF_CLR_BIT(nr) (BIT(nr+16))
#define DELAY_ENABLE(soc, tx, rx) \
(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
@@ -168,8 +168,8 @@ static int rk_set_clk_mac_speed(struct rk_priv_data *bsp_priv,
#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
-#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
-#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
+#define RK_GRF_CON2_MACPHY_ID GRF_FIELD(15, 0, 0x1234)
+#define RK_GRF_CON3_MACPHY_ID GRF_FIELD(5, 0, 0x35)
static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv)
{
@@ -285,8 +285,8 @@ static const struct rk_gmac_ops px30_ops = {
#define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
#define RK3128_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
#define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
-#define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
-#define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+#define RK3128_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(13, 7, val)
+#define RK3128_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
/* RK3128_GRF_MAC_CON1 */
#define RK3128_GMAC_PHY_INTF_SEL_RGMII \
@@ -350,8 +350,8 @@ static const struct rk_gmac_ops rk3128_ops = {
#define RK3228_GRF_CON_MUX 0x50
/* RK3228_GRF_MAC_CON0 */
-#define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
-#define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+#define RK3228_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(13, 7, val)
+#define RK3228_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
/* RK3228_GRF_MAC_CON1 */
#define RK3228_GMAC_PHY_INTF_SEL_RGMII \
@@ -456,8 +456,8 @@ static const struct rk_gmac_ops rk3228_ops = {
#define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
#define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
#define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
-#define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
-#define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+#define RK3288_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(13, 7, val)
+#define RK3288_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
@@ -537,8 +537,8 @@ static const struct rk_gmac_ops rk3308_ops = {
#define RK3328_GRF_MACPHY_CON1 0xb04
/* RK3328_GRF_MAC_CON0 */
-#define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
-#define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+#define RK3328_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(13, 7, val)
+#define RK3328_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
/* RK3328_GRF_MAC_CON1 */
#define RK3328_GMAC_PHY_INTF_SEL_RGMII \
@@ -651,8 +651,8 @@ static const struct rk_gmac_ops rk3328_ops = {
#define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
#define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
#define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
-#define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
-#define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+#define RK3366_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val)
+#define RK3366_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
@@ -718,8 +718,8 @@ static const struct rk_gmac_ops rk3366_ops = {
#define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
#define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
#define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
-#define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
-#define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+#define RK3368_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val)
+#define RK3368_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
@@ -785,8 +785,8 @@ static const struct rk_gmac_ops rk3368_ops = {
#define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
#define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
#define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
-#define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
-#define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+#define RK3399_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val)
+#define RK3399_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
@@ -901,8 +901,8 @@ static const struct rk_gmac_ops rk3506_ops = {
#define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
#define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
-#define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
-#define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
+#define RK3528_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(15, 8, val)
+#define RK3528_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(7, 0, val)
#define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1)
#define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8)
@@ -1041,8 +1041,8 @@ static const struct rk_gmac_ops rk3528_ops = {
#define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
/* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
-#define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
-#define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+#define RK3568_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val)
+#define RK3568_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
@@ -1096,8 +1096,8 @@ static const struct rk_gmac_ops rk3568_ops = {
#define RK3576_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
#define RK3576_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
-#define RK3576_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
-#define RK3576_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+#define RK3576_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val)
+#define RK3576_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
/* SDGMAC_GRF */
#define RK3576_GRF_GMAC_CON0 0X0020
@@ -1220,8 +1220,8 @@ static const struct rk_gmac_ops rk3576_ops = {
#define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2)
#define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2)
-#define RK3588_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
-#define RK3588_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
+#define RK3588_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(15, 8, val)
+#define RK3588_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(7, 0, val)
/* php_grf */
#define RK3588_GRF_GMAC_CON0 0X0008
@@ -1400,11 +1400,11 @@ static const struct rk_gmac_ops rv1108_ops = {
#define RV1126_GMAC_M1_TXCLK_DLY_DISABLE GRF_CLR_BIT(2)
/* RV1126_GRF_GMAC_CON1 */
-#define RV1126_GMAC_M0_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
-#define RV1126_GMAC_M0_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+#define RV1126_GMAC_M0_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val)
+#define RV1126_GMAC_M0_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
/* RV1126_GRF_GMAC_CON2 */
-#define RV1126_GMAC_M1_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
-#define RV1126_GMAC_M1_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+#define RV1126_GMAC_M1_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val)
+#define RV1126_GMAC_M1_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
--
2.47.3
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH net-next 1/4] net: stmmac: rk: replace HIWORD_UPDATE() with GRF_FIELD()
2025-11-13 17:46 ` [PATCH net-next 1/4] net: stmmac: rk: replace HIWORD_UPDATE() with GRF_FIELD() Russell King (Oracle)
@ 2025-11-14 8:19 ` Maxime Chevallier
0 siblings, 0 replies; 9+ messages in thread
From: Maxime Chevallier @ 2025-11-14 8:19 UTC (permalink / raw)
To: Russell King (Oracle), Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, Maxime Coquelin, netdev, Paolo Abeni
Hi,
On 13/11/2025 18:46, Russell King (Oracle) wrote:
> Provide GRF_FIELD() which takes the high/low bit numbers of the field
> and field value, generates the mask and passes it to FIELD_PREP_WM16.
> Replace all HIWORD_UPDATE() instances with this.
>
> No change to produced code on aarch64.
>
> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Maxime
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH net-next 2/4] net: stmmac: rk: convert all bitfields to GRF_FIELD*()
2025-11-13 17:46 [PATCH net-next 0/4] net: stmmac: rk: use PHY_INTF_SEL_x Russell King (Oracle)
2025-11-13 17:46 ` [PATCH net-next 1/4] net: stmmac: rk: replace HIWORD_UPDATE() with GRF_FIELD() Russell King (Oracle)
@ 2025-11-13 17:46 ` Russell King (Oracle)
2025-11-13 17:46 ` [PATCH net-next 3/4] net: stmmac: rk: use PHY_INTF_SEL_x constants Russell King (Oracle)
` (2 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Russell King (Oracle) @ 2025-11-13 17:46 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, Maxime Coquelin, netdev, Paolo Abeni
Convert all bitfields to GRF_FIELD() or GRF_FIELD_CONST(), which makes
the bitfield values more readable, and also allows the aarch64 compiler
to produce better code.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 136 ++++++++----------
1 file changed, 57 insertions(+), 79 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 794a7ed71451..4257cc1f66e9 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -151,6 +151,8 @@ static int rk_set_clk_mac_speed(struct rk_priv_data *bsp_priv,
#define GRF_FIELD(hi, lo, val) \
FIELD_PREP_WM16(GENMASK_U16(hi, lo), val)
+#define GRF_FIELD_CONST(hi, lo, val) \
+ FIELD_PREP_WM16_CONST(GENMASK_U16(hi, lo), val)
#define GRF_BIT(nr) (BIT(nr) | BIT(nr+16))
#define GRF_CLR_BIT(nr) (BIT(nr+16))
@@ -167,7 +169,7 @@ static int rk_set_clk_mac_speed(struct rk_priv_data *bsp_priv,
#define RK_MACPHY_ENABLE GRF_BIT(0)
#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
-#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
+#define RK_GMAC2PHY_RMII_MODE GRF_FIELD(7, 6, 1)
#define RK_GRF_CON2_MACPHY_ID GRF_FIELD(15, 0, 0x1234)
#define RK_GRF_CON3_MACPHY_ID GRF_FIELD(5, 0, 0x35)
@@ -203,7 +205,7 @@ static void rk_gmac_integrated_ephy_powerdown(struct rk_priv_data *priv)
#define RK_FEPHY_SHUTDOWN GRF_BIT(1)
#define RK_FEPHY_POWERUP GRF_CLR_BIT(1)
#define RK_FEPHY_INTERNAL_RMII_SEL GRF_BIT(6)
-#define RK_FEPHY_24M_CLK_SEL (GRF_BIT(8) | GRF_BIT(9))
+#define RK_FEPHY_24M_CLK_SEL GRF_FIELD(9, 8, 3)
#define RK_FEPHY_PHY_ID GRF_BIT(11)
static void rk_gmac_integrated_fephy_powerup(struct rk_priv_data *priv,
@@ -232,8 +234,7 @@ static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv,
#define PX30_GRF_GMAC_CON1 0x0904
/* PX30_GRF_GMAC_CON1 */
-#define PX30_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
- GRF_BIT(6))
+#define PX30_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, 4)
#define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2)
#define PX30_GMAC_SPEED_100M GRF_BIT(2)
@@ -289,19 +290,17 @@ static const struct rk_gmac_ops px30_ops = {
#define RK3128_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
/* RK3128_GRF_MAC_CON1 */
-#define RK3128_GMAC_PHY_INTF_SEL_RGMII \
- (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8))
-#define RK3128_GMAC_PHY_INTF_SEL_RMII \
- (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8))
+#define RK3128_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(8, 6, 1)
+#define RK3128_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(8, 6, 4)
#define RK3128_GMAC_FLOW_CTRL GRF_BIT(9)
#define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
#define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10)
#define RK3128_GMAC_SPEED_100M GRF_BIT(10)
#define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11)
#define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
-#define RK3128_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
-#define RK3128_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13))
-#define RK3128_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13))
+#define RK3128_GMAC_CLK_125M GRF_FIELD_CONST(13, 12, 0)
+#define RK3128_GMAC_CLK_25M GRF_FIELD_CONST(13, 12, 3)
+#define RK3128_GMAC_CLK_2_5M GRF_FIELD_CONST(13, 12, 2)
#define RK3128_GMAC_RMII_MODE GRF_BIT(14)
#define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
@@ -354,19 +353,17 @@ static const struct rk_gmac_ops rk3128_ops = {
#define RK3228_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
/* RK3228_GRF_MAC_CON1 */
-#define RK3228_GMAC_PHY_INTF_SEL_RGMII \
- (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
-#define RK3228_GMAC_PHY_INTF_SEL_RMII \
- (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
+#define RK3228_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, 1)
+#define RK3228_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, 4)
#define RK3228_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
#define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2)
#define RK3228_GMAC_SPEED_100M GRF_BIT(2)
#define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7)
#define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
-#define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9))
-#define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9))
-#define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9))
+#define RK3228_GMAC_CLK_125M GRF_FIELD_CONST(9, 8, 0)
+#define RK3228_GMAC_CLK_25M GRF_FIELD_CONST(9, 8, 3)
+#define RK3228_GMAC_CLK_2_5M GRF_FIELD_CONST(9, 8, 2)
#define RK3228_GMAC_RMII_MODE GRF_BIT(10)
#define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10)
#define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
@@ -435,19 +432,17 @@ static const struct rk_gmac_ops rk3228_ops = {
#define RK3288_GRF_SOC_CON3 0x0250
/*RK3288_GRF_SOC_CON1*/
-#define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \
- GRF_CLR_BIT(8))
-#define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \
- GRF_BIT(8))
+#define RK3288_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(8, 6, 1)
+#define RK3288_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(8, 6, 4)
#define RK3288_GMAC_FLOW_CTRL GRF_BIT(9)
#define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
#define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10)
#define RK3288_GMAC_SPEED_100M GRF_BIT(10)
#define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11)
#define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
-#define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
-#define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13))
-#define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13))
+#define RK3288_GMAC_CLK_125M GRF_FIELD_CONST(13, 12, 0)
+#define RK3288_GMAC_CLK_25M GRF_FIELD_CONST(13, 12, 3)
+#define RK3288_GMAC_CLK_2_5M GRF_FIELD_CONST(13, 12, 2)
#define RK3288_GMAC_RMII_MODE GRF_BIT(14)
#define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
@@ -501,8 +496,7 @@ static const struct rk_gmac_ops rk3288_ops = {
#define RK3308_GRF_MAC_CON0 0x04a0
/* RK3308_GRF_MAC_CON0 */
-#define RK3308_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(2) | GRF_CLR_BIT(3) | \
- GRF_BIT(4))
+#define RK3308_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(4, 2, 4)
#define RK3308_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
#define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0)
@@ -541,19 +535,17 @@ static const struct rk_gmac_ops rk3308_ops = {
#define RK3328_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
/* RK3328_GRF_MAC_CON1 */
-#define RK3328_GMAC_PHY_INTF_SEL_RGMII \
- (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
-#define RK3328_GMAC_PHY_INTF_SEL_RMII \
- (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
+#define RK3328_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, 1)
+#define RK3328_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, 4)
#define RK3328_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
#define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2)
#define RK3328_GMAC_SPEED_100M GRF_BIT(2)
#define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7)
#define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
-#define RK3328_GMAC_CLK_125M (GRF_CLR_BIT(11) | GRF_CLR_BIT(12))
-#define RK3328_GMAC_CLK_25M (GRF_BIT(11) | GRF_BIT(12))
-#define RK3328_GMAC_CLK_2_5M (GRF_CLR_BIT(11) | GRF_BIT(12))
+#define RK3328_GMAC_CLK_125M GRF_FIELD_CONST(12, 11, 0)
+#define RK3328_GMAC_CLK_25M GRF_FIELD_CONST(12, 11, 3)
+#define RK3328_GMAC_CLK_2_5M GRF_FIELD_CONST(12, 11, 2)
#define RK3328_GMAC_RMII_MODE GRF_BIT(9)
#define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9)
#define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
@@ -630,19 +622,17 @@ static const struct rk_gmac_ops rk3328_ops = {
#define RK3366_GRF_SOC_CON7 0x041c
/* RK3366_GRF_SOC_CON6 */
-#define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
- GRF_CLR_BIT(11))
-#define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
- GRF_BIT(11))
+#define RK3366_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, 1)
+#define RK3366_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, 4)
#define RK3366_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
#define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7)
#define RK3366_GMAC_SPEED_100M GRF_BIT(7)
#define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3)
#define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
-#define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
-#define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
-#define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
+#define RK3366_GMAC_CLK_125M GRF_FIELD_CONST(5, 4, 0)
+#define RK3366_GMAC_CLK_25M GRF_FIELD_CONST(5, 4, 3)
+#define RK3366_GMAC_CLK_2_5M GRF_FIELD_CONST(5, 4, 2)
#define RK3366_GMAC_RMII_MODE GRF_BIT(6)
#define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
@@ -697,19 +687,17 @@ static const struct rk_gmac_ops rk3366_ops = {
#define RK3368_GRF_SOC_CON16 0x0440
/* RK3368_GRF_SOC_CON15 */
-#define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
- GRF_CLR_BIT(11))
-#define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
- GRF_BIT(11))
+#define RK3368_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, 1)
+#define RK3368_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, 4)
#define RK3368_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
#define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7)
#define RK3368_GMAC_SPEED_100M GRF_BIT(7)
#define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3)
#define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
-#define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
-#define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
-#define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
+#define RK3368_GMAC_CLK_125M GRF_FIELD_CONST(5, 4, 0)
+#define RK3368_GMAC_CLK_25M GRF_FIELD_CONST(5, 4, 3)
+#define RK3368_GMAC_CLK_2_5M GRF_FIELD_CONST(5, 4, 2)
#define RK3368_GMAC_RMII_MODE GRF_BIT(6)
#define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
@@ -764,19 +752,17 @@ static const struct rk_gmac_ops rk3368_ops = {
#define RK3399_GRF_SOC_CON6 0xc218
/* RK3399_GRF_SOC_CON5 */
-#define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
- GRF_CLR_BIT(11))
-#define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
- GRF_BIT(11))
+#define RK3399_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, 1)
+#define RK3399_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, 4)
#define RK3399_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
#define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7)
#define RK3399_GMAC_SPEED_100M GRF_BIT(7)
#define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3)
#define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
-#define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
-#define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
-#define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
+#define RK3399_GMAC_CLK_125M GRF_FIELD_CONST(5, 4, 0)
+#define RK3399_GMAC_CLK_25M GRF_FIELD_CONST(5, 4, 3)
+#define RK3399_GMAC_CLK_2_5M GRF_FIELD_CONST(5, 4, 2)
#define RK3399_GMAC_RMII_MODE GRF_BIT(6)
#define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
@@ -916,9 +902,9 @@ static const struct rk_gmac_ops rk3506_ops = {
#define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10)
#define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10)
-#define RK3528_GMAC1_CLK_RGMII_DIV1 (GRF_CLR_BIT(11) | GRF_CLR_BIT(10))
-#define RK3528_GMAC1_CLK_RGMII_DIV5 (GRF_BIT(11) | GRF_BIT(10))
-#define RK3528_GMAC1_CLK_RGMII_DIV50 (GRF_BIT(11) | GRF_CLR_BIT(10))
+#define RK3528_GMAC1_CLK_RGMII_DIV1 GRF_FIELD_CONST(11, 10, 0)
+#define RK3528_GMAC1_CLK_RGMII_DIV5 GRF_FIELD_CONST(11, 10, 3)
+#define RK3528_GMAC1_CLK_RGMII_DIV50 GRF_FIELD_CONST(11, 10, 2)
#define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2)
#define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2)
@@ -1029,10 +1015,8 @@ static const struct rk_gmac_ops rk3528_ops = {
#define RK3568_GRF_GMAC1_CON1 0x038c
/* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
-#define RK3568_GMAC_PHY_INTF_SEL_RGMII \
- (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
-#define RK3568_GMAC_PHY_INTF_SEL_RMII \
- (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
+#define RK3568_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, 1)
+#define RK3568_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, 4)
#define RK3568_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
#define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
@@ -1112,12 +1096,9 @@ static const struct rk_gmac_ops rk3568_ops = {
#define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5)
#define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5)
-#define RK3576_GMAC_CLK_RGMII_DIV1 \
- (GRF_CLR_BIT(6) | GRF_CLR_BIT(5))
-#define RK3576_GMAC_CLK_RGMII_DIV5 \
- (GRF_BIT(6) | GRF_BIT(5))
-#define RK3576_GMAC_CLK_RGMII_DIV50 \
- (GRF_BIT(6) | GRF_CLR_BIT(5))
+#define RK3576_GMAC_CLK_RGMII_DIV1 GRF_FIELD_CONST(6, 5, 0)
+#define RK3576_GMAC_CLK_RGMII_DIV5 GRF_FIELD_CONST(6, 5, 3)
+#define RK3576_GMAC_CLK_RGMII_DIV50 GRF_FIELD_CONST(6, 5, 2)
#define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4)
#define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4)
@@ -1228,9 +1209,9 @@ static const struct rk_gmac_ops rk3576_ops = {
#define RK3588_GRF_CLK_CON1 0X0070
#define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \
- (GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6))
+ (GRF_FIELD(5, 3, 1) << ((id) * 6))
#define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \
- (GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6))
+ (GRF_FIELD(5, 3, 4) << ((id) * 6))
#define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id))
#define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id))
@@ -1242,11 +1223,11 @@ static const struct rk_gmac_ops rk3576_ops = {
#define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2)
#define RK3588_GMAC_CLK_RGMII_DIV1(id) \
- (GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3))
+ (GRF_FIELD_CONST(3, 2, 0) << ((id) * 5))
#define RK3588_GMAC_CLK_RGMII_DIV5(id) \
- (GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
+ (GRF_FIELD_CONST(3, 2, 3) << ((id) * 5))
#define RK3588_GMAC_CLK_RGMII_DIV50(id) \
- (GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
+ (GRF_FIELD_CONST(3, 2, 2) << ((id) * 5))
#define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1)
#define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1)
@@ -1347,8 +1328,7 @@ static const struct rk_gmac_ops rk3588_ops = {
#define RV1108_GRF_GMAC_CON0 0X0900
/* RV1108_GRF_GMAC_CON0 */
-#define RV1108_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
- GRF_BIT(6))
+#define RV1108_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, 4)
#define RV1108_GMAC_FLOW_CTRL GRF_BIT(3)
#define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
#define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2)
@@ -1384,10 +1364,8 @@ static const struct rk_gmac_ops rv1108_ops = {
#define RV1126_GRF_GMAC_CON2 0X0078
/* RV1126_GRF_GMAC_CON0 */
-#define RV1126_GMAC_PHY_INTF_SEL_RGMII \
- (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
-#define RV1126_GMAC_PHY_INTF_SEL_RMII \
- (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
+#define RV1126_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, 1)
+#define RV1126_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, 4)
#define RV1126_GMAC_FLOW_CTRL GRF_BIT(7)
#define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7)
#define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1)
--
2.47.3
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH net-next 3/4] net: stmmac: rk: use PHY_INTF_SEL_x constants
2025-11-13 17:46 [PATCH net-next 0/4] net: stmmac: rk: use PHY_INTF_SEL_x Russell King (Oracle)
2025-11-13 17:46 ` [PATCH net-next 1/4] net: stmmac: rk: replace HIWORD_UPDATE() with GRF_FIELD() Russell King (Oracle)
2025-11-13 17:46 ` [PATCH net-next 2/4] net: stmmac: rk: convert all bitfields to GRF_FIELD*() Russell King (Oracle)
@ 2025-11-13 17:46 ` Russell King (Oracle)
2025-11-14 8:29 ` Maxime Chevallier
2025-11-13 17:46 ` [PATCH net-next 4/4] net: stmmac: rk: use PHY_INTF_SEL_x in functions Russell King (Oracle)
2025-11-15 2:40 ` [PATCH net-next 0/4] net: stmmac: rk: use PHY_INTF_SEL_x patchwork-bot+netdevbpf
4 siblings, 1 reply; 9+ messages in thread
From: Russell King (Oracle) @ 2025-11-13 17:46 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, Maxime Coquelin, netdev, Paolo Abeni
The values used in the xxx_GMAC_PHY_INTF_SEL_xxx() macros are the
phy_intf_sel values used for the dwmac core. Use these to define these
constants.
No change to produced code on aarch64.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 46 +++++++++----------
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 4257cc1f66e9..49076ee00877 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -234,7 +234,7 @@ static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv,
#define PX30_GRF_GMAC_CON1 0x0904
/* PX30_GRF_GMAC_CON1 */
-#define PX30_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, 4)
+#define PX30_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
#define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2)
#define PX30_GMAC_SPEED_100M GRF_BIT(2)
@@ -290,8 +290,8 @@ static const struct rk_gmac_ops px30_ops = {
#define RK3128_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
/* RK3128_GRF_MAC_CON1 */
-#define RK3128_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(8, 6, 1)
-#define RK3128_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(8, 6, 4)
+#define RK3128_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(8, 6, PHY_INTF_SEL_RGMII)
+#define RK3128_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(8, 6, PHY_INTF_SEL_RMII)
#define RK3128_GMAC_FLOW_CTRL GRF_BIT(9)
#define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
#define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10)
@@ -353,8 +353,8 @@ static const struct rk_gmac_ops rk3128_ops = {
#define RK3228_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
/* RK3228_GRF_MAC_CON1 */
-#define RK3228_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, 1)
-#define RK3228_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, 4)
+#define RK3228_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, PHY_INTF_SEL_RGMII)
+#define RK3228_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
#define RK3228_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
#define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2)
@@ -432,8 +432,8 @@ static const struct rk_gmac_ops rk3228_ops = {
#define RK3288_GRF_SOC_CON3 0x0250
/*RK3288_GRF_SOC_CON1*/
-#define RK3288_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(8, 6, 1)
-#define RK3288_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(8, 6, 4)
+#define RK3288_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(8, 6, PHY_INTF_SEL_RGMII)
+#define RK3288_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(8, 6, PHY_INTF_SEL_RMII)
#define RK3288_GMAC_FLOW_CTRL GRF_BIT(9)
#define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
#define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10)
@@ -496,7 +496,7 @@ static const struct rk_gmac_ops rk3288_ops = {
#define RK3308_GRF_MAC_CON0 0x04a0
/* RK3308_GRF_MAC_CON0 */
-#define RK3308_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(4, 2, 4)
+#define RK3308_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(4, 2, PHY_INTF_SEL_RMII)
#define RK3308_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
#define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0)
@@ -535,8 +535,8 @@ static const struct rk_gmac_ops rk3308_ops = {
#define RK3328_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
/* RK3328_GRF_MAC_CON1 */
-#define RK3328_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, 1)
-#define RK3328_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, 4)
+#define RK3328_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, PHY_INTF_SEL_RGMII)
+#define RK3328_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
#define RK3328_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
#define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2)
@@ -622,8 +622,8 @@ static const struct rk_gmac_ops rk3328_ops = {
#define RK3366_GRF_SOC_CON7 0x041c
/* RK3366_GRF_SOC_CON6 */
-#define RK3366_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, 1)
-#define RK3366_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, 4)
+#define RK3366_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, PHY_INTF_SEL_RGMII)
+#define RK3366_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, PHY_INTF_SEL_RMII)
#define RK3366_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
#define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7)
@@ -687,8 +687,8 @@ static const struct rk_gmac_ops rk3366_ops = {
#define RK3368_GRF_SOC_CON16 0x0440
/* RK3368_GRF_SOC_CON15 */
-#define RK3368_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, 1)
-#define RK3368_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, 4)
+#define RK3368_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, PHY_INTF_SEL_RGMII)
+#define RK3368_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, PHY_INTF_SEL_RMII)
#define RK3368_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
#define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7)
@@ -752,8 +752,8 @@ static const struct rk_gmac_ops rk3368_ops = {
#define RK3399_GRF_SOC_CON6 0xc218
/* RK3399_GRF_SOC_CON5 */
-#define RK3399_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, 1)
-#define RK3399_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, 4)
+#define RK3399_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, PHY_INTF_SEL_RGMII)
+#define RK3399_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, PHY_INTF_SEL_RMII)
#define RK3399_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
#define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7)
@@ -1015,8 +1015,8 @@ static const struct rk_gmac_ops rk3528_ops = {
#define RK3568_GRF_GMAC1_CON1 0x038c
/* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
-#define RK3568_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, 1)
-#define RK3568_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, 4)
+#define RK3568_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, PHY_INTF_SEL_RGMII)
+#define RK3568_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
#define RK3568_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
#define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
@@ -1209,9 +1209,9 @@ static const struct rk_gmac_ops rk3576_ops = {
#define RK3588_GRF_CLK_CON1 0X0070
#define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \
- (GRF_FIELD(5, 3, 1) << ((id) * 6))
+ (GRF_FIELD(5, 3, PHY_INTF_SEL_RGMII) << ((id) * 6))
#define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \
- (GRF_FIELD(5, 3, 4) << ((id) * 6))
+ (GRF_FIELD(5, 3, PHY_INTF_SEL_RMII) << ((id) * 6))
#define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id))
#define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id))
@@ -1328,7 +1328,7 @@ static const struct rk_gmac_ops rk3588_ops = {
#define RV1108_GRF_GMAC_CON0 0X0900
/* RV1108_GRF_GMAC_CON0 */
-#define RV1108_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, 4)
+#define RV1108_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
#define RV1108_GMAC_FLOW_CTRL GRF_BIT(3)
#define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
#define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2)
@@ -1364,8 +1364,8 @@ static const struct rk_gmac_ops rv1108_ops = {
#define RV1126_GRF_GMAC_CON2 0X0078
/* RV1126_GRF_GMAC_CON0 */
-#define RV1126_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, 1)
-#define RV1126_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, 4)
+#define RV1126_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, PHY_INTF_SEL_RGMII)
+#define RV1126_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
#define RV1126_GMAC_FLOW_CTRL GRF_BIT(7)
#define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7)
#define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1)
--
2.47.3
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH net-next 3/4] net: stmmac: rk: use PHY_INTF_SEL_x constants
2025-11-13 17:46 ` [PATCH net-next 3/4] net: stmmac: rk: use PHY_INTF_SEL_x constants Russell King (Oracle)
@ 2025-11-14 8:29 ` Maxime Chevallier
0 siblings, 0 replies; 9+ messages in thread
From: Maxime Chevallier @ 2025-11-14 8:29 UTC (permalink / raw)
To: Russell King (Oracle), Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, Maxime Coquelin, netdev, Paolo Abeni
On 13/11/2025 18:46, Russell King (Oracle) wrote:
> The values used in the xxx_GMAC_PHY_INTF_SEL_xxx() macros are the
> phy_intf_sel values used for the dwmac core. Use these to define these
> constants.
>
> No change to produced code on aarch64.
>
> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Maxime
> ---
> .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 46 +++++++++----------
> 1 file changed, 23 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> index 4257cc1f66e9..49076ee00877 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> @@ -234,7 +234,7 @@ static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv,
> #define PX30_GRF_GMAC_CON1 0x0904
>
> /* PX30_GRF_GMAC_CON1 */
> -#define PX30_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, 4)
> +#define PX30_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
> #define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2)
> #define PX30_GMAC_SPEED_100M GRF_BIT(2)
>
> @@ -290,8 +290,8 @@ static const struct rk_gmac_ops px30_ops = {
> #define RK3128_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
>
> /* RK3128_GRF_MAC_CON1 */
> -#define RK3128_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(8, 6, 1)
> -#define RK3128_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(8, 6, 4)
> +#define RK3128_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(8, 6, PHY_INTF_SEL_RGMII)
> +#define RK3128_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(8, 6, PHY_INTF_SEL_RMII)
> #define RK3128_GMAC_FLOW_CTRL GRF_BIT(9)
> #define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
> #define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10)
> @@ -353,8 +353,8 @@ static const struct rk_gmac_ops rk3128_ops = {
> #define RK3228_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
>
> /* RK3228_GRF_MAC_CON1 */
> -#define RK3228_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, 1)
> -#define RK3228_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, 4)
> +#define RK3228_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, PHY_INTF_SEL_RGMII)
> +#define RK3228_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
> #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3)
> #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
> #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2)
> @@ -432,8 +432,8 @@ static const struct rk_gmac_ops rk3228_ops = {
> #define RK3288_GRF_SOC_CON3 0x0250
>
> /*RK3288_GRF_SOC_CON1*/
> -#define RK3288_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(8, 6, 1)
> -#define RK3288_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(8, 6, 4)
> +#define RK3288_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(8, 6, PHY_INTF_SEL_RGMII)
> +#define RK3288_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(8, 6, PHY_INTF_SEL_RMII)
> #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9)
> #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
> #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10)
> @@ -496,7 +496,7 @@ static const struct rk_gmac_ops rk3288_ops = {
> #define RK3308_GRF_MAC_CON0 0x04a0
>
> /* RK3308_GRF_MAC_CON0 */
> -#define RK3308_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(4, 2, 4)
> +#define RK3308_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(4, 2, PHY_INTF_SEL_RMII)
> #define RK3308_GMAC_FLOW_CTRL GRF_BIT(3)
> #define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
> #define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0)
> @@ -535,8 +535,8 @@ static const struct rk_gmac_ops rk3308_ops = {
> #define RK3328_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
>
> /* RK3328_GRF_MAC_CON1 */
> -#define RK3328_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, 1)
> -#define RK3328_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, 4)
> +#define RK3328_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, PHY_INTF_SEL_RGMII)
> +#define RK3328_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
> #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3)
> #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
> #define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2)
> @@ -622,8 +622,8 @@ static const struct rk_gmac_ops rk3328_ops = {
> #define RK3366_GRF_SOC_CON7 0x041c
>
> /* RK3366_GRF_SOC_CON6 */
> -#define RK3366_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, 1)
> -#define RK3366_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, 4)
> +#define RK3366_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, PHY_INTF_SEL_RGMII)
> +#define RK3366_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, PHY_INTF_SEL_RMII)
> #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8)
> #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
> #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7)
> @@ -687,8 +687,8 @@ static const struct rk_gmac_ops rk3366_ops = {
> #define RK3368_GRF_SOC_CON16 0x0440
>
> /* RK3368_GRF_SOC_CON15 */
> -#define RK3368_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, 1)
> -#define RK3368_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, 4)
> +#define RK3368_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, PHY_INTF_SEL_RGMII)
> +#define RK3368_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, PHY_INTF_SEL_RMII)
> #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8)
> #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
> #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7)
> @@ -752,8 +752,8 @@ static const struct rk_gmac_ops rk3368_ops = {
> #define RK3399_GRF_SOC_CON6 0xc218
>
> /* RK3399_GRF_SOC_CON5 */
> -#define RK3399_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, 1)
> -#define RK3399_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, 4)
> +#define RK3399_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, PHY_INTF_SEL_RGMII)
> +#define RK3399_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, PHY_INTF_SEL_RMII)
> #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8)
> #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
> #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7)
> @@ -1015,8 +1015,8 @@ static const struct rk_gmac_ops rk3528_ops = {
> #define RK3568_GRF_GMAC1_CON1 0x038c
>
> /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
> -#define RK3568_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, 1)
> -#define RK3568_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, 4)
> +#define RK3568_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, PHY_INTF_SEL_RGMII)
> +#define RK3568_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
> #define RK3568_GMAC_FLOW_CTRL GRF_BIT(3)
> #define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
> #define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
> @@ -1209,9 +1209,9 @@ static const struct rk_gmac_ops rk3576_ops = {
> #define RK3588_GRF_CLK_CON1 0X0070
>
> #define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \
> - (GRF_FIELD(5, 3, 1) << ((id) * 6))
> + (GRF_FIELD(5, 3, PHY_INTF_SEL_RGMII) << ((id) * 6))
> #define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \
> - (GRF_FIELD(5, 3, 4) << ((id) * 6))
> + (GRF_FIELD(5, 3, PHY_INTF_SEL_RMII) << ((id) * 6))
>
> #define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id))
> #define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id))
> @@ -1328,7 +1328,7 @@ static const struct rk_gmac_ops rk3588_ops = {
> #define RV1108_GRF_GMAC_CON0 0X0900
>
> /* RV1108_GRF_GMAC_CON0 */
> -#define RV1108_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, 4)
> +#define RV1108_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
> #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3)
> #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
> #define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2)
> @@ -1364,8 +1364,8 @@ static const struct rk_gmac_ops rv1108_ops = {
> #define RV1126_GRF_GMAC_CON2 0X0078
>
> /* RV1126_GRF_GMAC_CON0 */
> -#define RV1126_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, 1)
> -#define RV1126_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, 4)
> +#define RV1126_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, PHY_INTF_SEL_RGMII)
> +#define RV1126_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
> #define RV1126_GMAC_FLOW_CTRL GRF_BIT(7)
> #define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7)
> #define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1)
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH net-next 4/4] net: stmmac: rk: use PHY_INTF_SEL_x in functions
2025-11-13 17:46 [PATCH net-next 0/4] net: stmmac: rk: use PHY_INTF_SEL_x Russell King (Oracle)
` (2 preceding siblings ...)
2025-11-13 17:46 ` [PATCH net-next 3/4] net: stmmac: rk: use PHY_INTF_SEL_x constants Russell King (Oracle)
@ 2025-11-13 17:46 ` Russell King (Oracle)
2025-11-14 8:29 ` Maxime Chevallier
2025-11-15 2:40 ` [PATCH net-next 0/4] net: stmmac: rk: use PHY_INTF_SEL_x patchwork-bot+netdevbpf
4 siblings, 1 reply; 9+ messages in thread
From: Russell King (Oracle) @ 2025-11-13 17:46 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, Maxime Coquelin, netdev, Paolo Abeni
Rather than defining one xxx_GMAC_PHY_INTF_SEL_xxx() for each mode,
define xxx_GMAC_PHY_INTF_SEL() which takes the phy_intf_sel value.
Pass the appropriate value into these new macros in the set_to_xxx()
methods.
No change to produced code on aarch64.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 91 +++++++++----------
1 file changed, 43 insertions(+), 48 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 49076ee00877..6e75da577af5 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -234,14 +234,14 @@ static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv,
#define PX30_GRF_GMAC_CON1 0x0904
/* PX30_GRF_GMAC_CON1 */
-#define PX30_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
+#define PX30_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val)
#define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2)
#define PX30_GMAC_SPEED_100M GRF_BIT(2)
static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)
{
regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
- PX30_GMAC_PHY_INTF_SEL_RMII);
+ PX30_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII));
}
static int px30_set_speed(struct rk_priv_data *bsp_priv,
@@ -290,8 +290,7 @@ static const struct rk_gmac_ops px30_ops = {
#define RK3128_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
/* RK3128_GRF_MAC_CON1 */
-#define RK3128_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(8, 6, PHY_INTF_SEL_RGMII)
-#define RK3128_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(8, 6, PHY_INTF_SEL_RMII)
+#define RK3128_GMAC_PHY_INTF_SEL(val) GRF_FIELD(8, 6, val)
#define RK3128_GMAC_FLOW_CTRL GRF_BIT(9)
#define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
#define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10)
@@ -308,7 +307,7 @@ static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
- RK3128_GMAC_PHY_INTF_SEL_RGMII |
+ RK3128_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
RK3128_GMAC_RMII_MODE_CLR);
regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
DELAY_ENABLE(RK3128, tx_delay, rx_delay) |
@@ -319,7 +318,8 @@ static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
{
regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
- RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE);
+ RK3128_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
+ RK3128_GMAC_RMII_MODE);
}
static const struct rk_reg_speed_data rk3128_reg_speed_data = {
@@ -353,8 +353,7 @@ static const struct rk_gmac_ops rk3128_ops = {
#define RK3228_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
/* RK3228_GRF_MAC_CON1 */
-#define RK3228_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, PHY_INTF_SEL_RGMII)
-#define RK3228_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
+#define RK3228_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val)
#define RK3228_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
#define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2)
@@ -378,7 +377,7 @@ static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
- RK3228_GMAC_PHY_INTF_SEL_RGMII |
+ RK3228_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
RK3228_GMAC_RMII_MODE_CLR |
DELAY_ENABLE(RK3228, tx_delay, rx_delay));
@@ -390,7 +389,7 @@ static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
{
regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
- RK3228_GMAC_PHY_INTF_SEL_RMII |
+ RK3228_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
RK3228_GMAC_RMII_MODE);
/* set MAC to RMII mode */
@@ -432,8 +431,7 @@ static const struct rk_gmac_ops rk3228_ops = {
#define RK3288_GRF_SOC_CON3 0x0250
/*RK3288_GRF_SOC_CON1*/
-#define RK3288_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(8, 6, PHY_INTF_SEL_RGMII)
-#define RK3288_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(8, 6, PHY_INTF_SEL_RMII)
+#define RK3288_GMAC_PHY_INTF_SEL(val) GRF_FIELD(8, 6, val)
#define RK3288_GMAC_FLOW_CTRL GRF_BIT(9)
#define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
#define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10)
@@ -458,7 +456,7 @@ static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
- RK3288_GMAC_PHY_INTF_SEL_RGMII |
+ RK3288_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
RK3288_GMAC_RMII_MODE_CLR);
regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
@@ -469,7 +467,8 @@ static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
{
regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
- RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE);
+ RK3288_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
+ RK3288_GMAC_RMII_MODE);
}
static const struct rk_reg_speed_data rk3288_reg_speed_data = {
@@ -496,7 +495,7 @@ static const struct rk_gmac_ops rk3288_ops = {
#define RK3308_GRF_MAC_CON0 0x04a0
/* RK3308_GRF_MAC_CON0 */
-#define RK3308_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(4, 2, PHY_INTF_SEL_RMII)
+#define RK3308_GMAC_PHY_INTF_SEL(val) GRF_FIELD(4, 2, val)
#define RK3308_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
#define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0)
@@ -505,7 +504,7 @@ static const struct rk_gmac_ops rk3288_ops = {
static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
{
regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
- RK3308_GMAC_PHY_INTF_SEL_RMII);
+ RK3308_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII));
}
static const struct rk_reg_speed_data rk3308_reg_speed_data = {
@@ -535,8 +534,7 @@ static const struct rk_gmac_ops rk3308_ops = {
#define RK3328_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
/* RK3328_GRF_MAC_CON1 */
-#define RK3328_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, PHY_INTF_SEL_RGMII)
-#define RK3328_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
+#define RK3328_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val)
#define RK3328_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
#define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2)
@@ -558,7 +556,7 @@ static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
- RK3328_GMAC_PHY_INTF_SEL_RGMII |
+ RK3328_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
RK3328_GMAC_RMII_MODE_CLR |
RK3328_GMAC_RXCLK_DLY_ENABLE |
RK3328_GMAC_TXCLK_DLY_ENABLE);
@@ -576,7 +574,7 @@ static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
RK3328_GRF_MAC_CON1;
regmap_write(bsp_priv->grf, reg,
- RK3328_GMAC_PHY_INTF_SEL_RMII |
+ RK3328_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
RK3328_GMAC_RMII_MODE);
}
@@ -622,8 +620,7 @@ static const struct rk_gmac_ops rk3328_ops = {
#define RK3366_GRF_SOC_CON7 0x041c
/* RK3366_GRF_SOC_CON6 */
-#define RK3366_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, PHY_INTF_SEL_RGMII)
-#define RK3366_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, PHY_INTF_SEL_RMII)
+#define RK3366_GMAC_PHY_INTF_SEL(val) GRF_FIELD(11, 9, val)
#define RK3366_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
#define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7)
@@ -648,7 +645,7 @@ static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
- RK3366_GMAC_PHY_INTF_SEL_RGMII |
+ RK3366_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
RK3366_GMAC_RMII_MODE_CLR);
regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
@@ -659,7 +656,8 @@ static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
{
regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
- RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE);
+ RK3366_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
+ RK3366_GMAC_RMII_MODE);
}
static const struct rk_reg_speed_data rk3366_reg_speed_data = {
@@ -687,8 +685,7 @@ static const struct rk_gmac_ops rk3366_ops = {
#define RK3368_GRF_SOC_CON16 0x0440
/* RK3368_GRF_SOC_CON15 */
-#define RK3368_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, PHY_INTF_SEL_RGMII)
-#define RK3368_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, PHY_INTF_SEL_RMII)
+#define RK3368_GMAC_PHY_INTF_SEL(val) GRF_FIELD(11, 9, val)
#define RK3368_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
#define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7)
@@ -713,7 +710,7 @@ static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
- RK3368_GMAC_PHY_INTF_SEL_RGMII |
+ RK3368_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
RK3368_GMAC_RMII_MODE_CLR);
regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
@@ -724,7 +721,8 @@ static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
{
regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
- RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE);
+ RK3368_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
+ RK3368_GMAC_RMII_MODE);
}
static const struct rk_reg_speed_data rk3368_reg_speed_data = {
@@ -752,8 +750,7 @@ static const struct rk_gmac_ops rk3368_ops = {
#define RK3399_GRF_SOC_CON6 0xc218
/* RK3399_GRF_SOC_CON5 */
-#define RK3399_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, PHY_INTF_SEL_RGMII)
-#define RK3399_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, PHY_INTF_SEL_RMII)
+#define RK3399_GMAC_PHY_INTF_SEL(val) GRF_FIELD(11, 9, val)
#define RK3399_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
#define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7)
@@ -778,7 +775,7 @@ static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
- RK3399_GMAC_PHY_INTF_SEL_RGMII |
+ RK3399_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
RK3399_GMAC_RMII_MODE_CLR);
regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
@@ -789,7 +786,8 @@ static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
{
regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
- RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE);
+ RK3399_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
+ RK3399_GMAC_RMII_MODE);
}
static const struct rk_reg_speed_data rk3399_reg_speed_data = {
@@ -1015,8 +1013,7 @@ static const struct rk_gmac_ops rk3528_ops = {
#define RK3568_GRF_GMAC1_CON1 0x038c
/* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
-#define RK3568_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, PHY_INTF_SEL_RGMII)
-#define RK3568_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
+#define RK3568_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val)
#define RK3568_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
#define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
@@ -1043,7 +1040,7 @@ static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
regmap_write(bsp_priv->grf, con1,
- RK3568_GMAC_PHY_INTF_SEL_RGMII |
+ RK3568_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
RK3568_GMAC_RXCLK_DLY_ENABLE |
RK3568_GMAC_TXCLK_DLY_ENABLE);
}
@@ -1054,7 +1051,8 @@ static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)
con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
RK3568_GRF_GMAC0_CON1;
- regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII);
+ regmap_write(bsp_priv->grf, con1,
+ RK3568_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII));
}
static const struct rk_gmac_ops rk3568_ops = {
@@ -1208,10 +1206,8 @@ static const struct rk_gmac_ops rk3576_ops = {
#define RK3588_GRF_GMAC_CON0 0X0008
#define RK3588_GRF_CLK_CON1 0X0070
-#define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \
- (GRF_FIELD(5, 3, PHY_INTF_SEL_RGMII) << ((id) * 6))
-#define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \
- (GRF_FIELD(5, 3, PHY_INTF_SEL_RMII) << ((id) * 6))
+#define RK3588_GMAC_PHY_INTF_SEL(id, val) \
+ (GRF_FIELD(5, 3, val) << ((id) * 6))
#define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id))
#define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id))
@@ -1241,7 +1237,7 @@ static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
RK3588_GRF_GMAC_CON8;
regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
- RK3588_GMAC_PHY_INTF_SEL_RGMII(id));
+ RK3588_GMAC_PHY_INTF_SEL(id, PHY_INTF_SEL_RGMII));
regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
RK3588_GMAC_CLK_RGMII_MODE(id));
@@ -1258,7 +1254,7 @@ static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
{
regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
- RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->id));
+ RK3588_GMAC_PHY_INTF_SEL(bsp_priv->id, PHY_INTF_SEL_RMII));
regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id));
@@ -1328,7 +1324,7 @@ static const struct rk_gmac_ops rk3588_ops = {
#define RV1108_GRF_GMAC_CON0 0X0900
/* RV1108_GRF_GMAC_CON0 */
-#define RV1108_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
+#define RV1108_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val)
#define RV1108_GMAC_FLOW_CTRL GRF_BIT(3)
#define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
#define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2)
@@ -1339,7 +1335,7 @@ static const struct rk_gmac_ops rk3588_ops = {
static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
{
regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
- RV1108_GMAC_PHY_INTF_SEL_RMII);
+ RV1108_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII));
}
static const struct rk_reg_speed_data rv1108_reg_speed_data = {
@@ -1364,8 +1360,7 @@ static const struct rk_gmac_ops rv1108_ops = {
#define RV1126_GRF_GMAC_CON2 0X0078
/* RV1126_GRF_GMAC_CON0 */
-#define RV1126_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, PHY_INTF_SEL_RGMII)
-#define RV1126_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
+#define RV1126_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val)
#define RV1126_GMAC_FLOW_CTRL GRF_BIT(7)
#define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7)
#define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1)
@@ -1388,7 +1383,7 @@ static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
- RV1126_GMAC_PHY_INTF_SEL_RGMII |
+ RV1126_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
RV1126_GMAC_M0_RXCLK_DLY_ENABLE |
RV1126_GMAC_M0_TXCLK_DLY_ENABLE |
RV1126_GMAC_M1_RXCLK_DLY_ENABLE |
@@ -1406,7 +1401,7 @@ static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv)
{
regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
- RV1126_GMAC_PHY_INTF_SEL_RMII);
+ RV1126_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII));
}
static const struct rk_gmac_ops rv1126_ops = {
--
2.47.3
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH net-next 4/4] net: stmmac: rk: use PHY_INTF_SEL_x in functions
2025-11-13 17:46 ` [PATCH net-next 4/4] net: stmmac: rk: use PHY_INTF_SEL_x in functions Russell King (Oracle)
@ 2025-11-14 8:29 ` Maxime Chevallier
0 siblings, 0 replies; 9+ messages in thread
From: Maxime Chevallier @ 2025-11-14 8:29 UTC (permalink / raw)
To: Russell King (Oracle), Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, Maxime Coquelin, netdev, Paolo Abeni
On 13/11/2025 18:46, Russell King (Oracle) wrote:
> Rather than defining one xxx_GMAC_PHY_INTF_SEL_xxx() for each mode,
> define xxx_GMAC_PHY_INTF_SEL() which takes the phy_intf_sel value.
> Pass the appropriate value into these new macros in the set_to_xxx()
> methods.
>
> No change to produced code on aarch64.
>
> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
> ---
> .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 91 +++++++++----------
> 1 file changed, 43 insertions(+), 48 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> index 49076ee00877..6e75da577af5 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> @@ -234,14 +234,14 @@ static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv,
> #define PX30_GRF_GMAC_CON1 0x0904
>
> /* PX30_GRF_GMAC_CON1 */
> -#define PX30_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
> +#define PX30_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val)
> #define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2)
> #define PX30_GMAC_SPEED_100M GRF_BIT(2)
>
> static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)
> {
> regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
> - PX30_GMAC_PHY_INTF_SEL_RMII);
> + PX30_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII));
> }
>
> static int px30_set_speed(struct rk_priv_data *bsp_priv,
> @@ -290,8 +290,7 @@ static const struct rk_gmac_ops px30_ops = {
> #define RK3128_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
>
> /* RK3128_GRF_MAC_CON1 */
> -#define RK3128_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(8, 6, PHY_INTF_SEL_RGMII)
> -#define RK3128_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(8, 6, PHY_INTF_SEL_RMII)
> +#define RK3128_GMAC_PHY_INTF_SEL(val) GRF_FIELD(8, 6, val)
> #define RK3128_GMAC_FLOW_CTRL GRF_BIT(9)
> #define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
> #define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10)
> @@ -308,7 +307,7 @@ static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
> int tx_delay, int rx_delay)
> {
> regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
> - RK3128_GMAC_PHY_INTF_SEL_RGMII |
> + RK3128_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
> RK3128_GMAC_RMII_MODE_CLR);
> regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
> DELAY_ENABLE(RK3128, tx_delay, rx_delay) |
> @@ -319,7 +318,8 @@ static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
> static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
> {
> regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
> - RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE);
> + RK3128_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
> + RK3128_GMAC_RMII_MODE);
> }
>
> static const struct rk_reg_speed_data rk3128_reg_speed_data = {
> @@ -353,8 +353,7 @@ static const struct rk_gmac_ops rk3128_ops = {
> #define RK3228_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
>
> /* RK3228_GRF_MAC_CON1 */
> -#define RK3228_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, PHY_INTF_SEL_RGMII)
> -#define RK3228_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
> +#define RK3228_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val)
> #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3)
> #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
> #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2)
> @@ -378,7 +377,7 @@ static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
> int tx_delay, int rx_delay)
> {
> regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
> - RK3228_GMAC_PHY_INTF_SEL_RGMII |
> + RK3228_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
> RK3228_GMAC_RMII_MODE_CLR |
> DELAY_ENABLE(RK3228, tx_delay, rx_delay));
>
> @@ -390,7 +389,7 @@ static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
> static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
> {
> regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
> - RK3228_GMAC_PHY_INTF_SEL_RMII |
> + RK3228_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
> RK3228_GMAC_RMII_MODE);
>
> /* set MAC to RMII mode */
> @@ -432,8 +431,7 @@ static const struct rk_gmac_ops rk3228_ops = {
> #define RK3288_GRF_SOC_CON3 0x0250
>
> /*RK3288_GRF_SOC_CON1*/
> -#define RK3288_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(8, 6, PHY_INTF_SEL_RGMII)
> -#define RK3288_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(8, 6, PHY_INTF_SEL_RMII)
> +#define RK3288_GMAC_PHY_INTF_SEL(val) GRF_FIELD(8, 6, val)
> #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9)
> #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
> #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10)
> @@ -458,7 +456,7 @@ static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
> int tx_delay, int rx_delay)
> {
> regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
> - RK3288_GMAC_PHY_INTF_SEL_RGMII |
> + RK3288_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
> RK3288_GMAC_RMII_MODE_CLR);
> regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
> DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
> @@ -469,7 +467,8 @@ static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
> static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
> {
> regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
> - RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE);
> + RK3288_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
> + RK3288_GMAC_RMII_MODE);
> }
>
> static const struct rk_reg_speed_data rk3288_reg_speed_data = {
> @@ -496,7 +495,7 @@ static const struct rk_gmac_ops rk3288_ops = {
> #define RK3308_GRF_MAC_CON0 0x04a0
>
> /* RK3308_GRF_MAC_CON0 */
> -#define RK3308_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(4, 2, PHY_INTF_SEL_RMII)
> +#define RK3308_GMAC_PHY_INTF_SEL(val) GRF_FIELD(4, 2, val)
> #define RK3308_GMAC_FLOW_CTRL GRF_BIT(3)
> #define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
> #define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0)
> @@ -505,7 +504,7 @@ static const struct rk_gmac_ops rk3288_ops = {
> static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
> {
> regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
> - RK3308_GMAC_PHY_INTF_SEL_RMII);
> + RK3308_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII));
> }
>
> static const struct rk_reg_speed_data rk3308_reg_speed_data = {
> @@ -535,8 +534,7 @@ static const struct rk_gmac_ops rk3308_ops = {
> #define RK3328_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
>
> /* RK3328_GRF_MAC_CON1 */
> -#define RK3328_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, PHY_INTF_SEL_RGMII)
> -#define RK3328_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
> +#define RK3328_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val)
> #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3)
> #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
> #define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2)
> @@ -558,7 +556,7 @@ static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
> int tx_delay, int rx_delay)
> {
> regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
> - RK3328_GMAC_PHY_INTF_SEL_RGMII |
> + RK3328_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
> RK3328_GMAC_RMII_MODE_CLR |
> RK3328_GMAC_RXCLK_DLY_ENABLE |
> RK3328_GMAC_TXCLK_DLY_ENABLE);
> @@ -576,7 +574,7 @@ static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
> RK3328_GRF_MAC_CON1;
>
> regmap_write(bsp_priv->grf, reg,
> - RK3328_GMAC_PHY_INTF_SEL_RMII |
> + RK3328_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
> RK3328_GMAC_RMII_MODE);
> }
>
> @@ -622,8 +620,7 @@ static const struct rk_gmac_ops rk3328_ops = {
> #define RK3366_GRF_SOC_CON7 0x041c
>
> /* RK3366_GRF_SOC_CON6 */
> -#define RK3366_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, PHY_INTF_SEL_RGMII)
> -#define RK3366_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, PHY_INTF_SEL_RMII)
> +#define RK3366_GMAC_PHY_INTF_SEL(val) GRF_FIELD(11, 9, val)
> #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8)
> #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
> #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7)
> @@ -648,7 +645,7 @@ static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
> int tx_delay, int rx_delay)
> {
> regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
> - RK3366_GMAC_PHY_INTF_SEL_RGMII |
> + RK3366_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
> RK3366_GMAC_RMII_MODE_CLR);
> regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
> DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
> @@ -659,7 +656,8 @@ static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
> static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
> {
> regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
> - RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE);
> + RK3366_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
> + RK3366_GMAC_RMII_MODE);
> }
>
> static const struct rk_reg_speed_data rk3366_reg_speed_data = {
> @@ -687,8 +685,7 @@ static const struct rk_gmac_ops rk3366_ops = {
> #define RK3368_GRF_SOC_CON16 0x0440
>
> /* RK3368_GRF_SOC_CON15 */
> -#define RK3368_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, PHY_INTF_SEL_RGMII)
> -#define RK3368_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, PHY_INTF_SEL_RMII)
> +#define RK3368_GMAC_PHY_INTF_SEL(val) GRF_FIELD(11, 9, val)
> #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8)
> #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
> #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7)
> @@ -713,7 +710,7 @@ static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
> int tx_delay, int rx_delay)
> {
> regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
> - RK3368_GMAC_PHY_INTF_SEL_RGMII |
> + RK3368_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
> RK3368_GMAC_RMII_MODE_CLR);
> regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
> DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
> @@ -724,7 +721,8 @@ static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
> static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
> {
> regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
> - RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE);
> + RK3368_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
> + RK3368_GMAC_RMII_MODE);
> }
>
> static const struct rk_reg_speed_data rk3368_reg_speed_data = {
> @@ -752,8 +750,7 @@ static const struct rk_gmac_ops rk3368_ops = {
> #define RK3399_GRF_SOC_CON6 0xc218
>
> /* RK3399_GRF_SOC_CON5 */
> -#define RK3399_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(11, 9, PHY_INTF_SEL_RGMII)
> -#define RK3399_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(11, 9, PHY_INTF_SEL_RMII)
> +#define RK3399_GMAC_PHY_INTF_SEL(val) GRF_FIELD(11, 9, val)
> #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8)
> #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
> #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7)
> @@ -778,7 +775,7 @@ static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
> int tx_delay, int rx_delay)
> {
> regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
> - RK3399_GMAC_PHY_INTF_SEL_RGMII |
> + RK3399_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
> RK3399_GMAC_RMII_MODE_CLR);
> regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
> DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
> @@ -789,7 +786,8 @@ static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
> static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
> {
> regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
> - RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE);
> + RK3399_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
> + RK3399_GMAC_RMII_MODE);
> }
>
> static const struct rk_reg_speed_data rk3399_reg_speed_data = {
> @@ -1015,8 +1013,7 @@ static const struct rk_gmac_ops rk3528_ops = {
> #define RK3568_GRF_GMAC1_CON1 0x038c
>
> /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
> -#define RK3568_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, PHY_INTF_SEL_RGMII)
> -#define RK3568_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
> +#define RK3568_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val)
> #define RK3568_GMAC_FLOW_CTRL GRF_BIT(3)
> #define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
> #define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
> @@ -1043,7 +1040,7 @@ static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
> RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
>
> regmap_write(bsp_priv->grf, con1,
> - RK3568_GMAC_PHY_INTF_SEL_RGMII |
> + RK3568_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
> RK3568_GMAC_RXCLK_DLY_ENABLE |
> RK3568_GMAC_TXCLK_DLY_ENABLE);
> }
> @@ -1054,7 +1051,8 @@ static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)
>
> con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
> RK3568_GRF_GMAC0_CON1;
> - regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII);
> + regmap_write(bsp_priv->grf, con1,
> + RK3568_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII));
> }
>
> static const struct rk_gmac_ops rk3568_ops = {
> @@ -1208,10 +1206,8 @@ static const struct rk_gmac_ops rk3576_ops = {
> #define RK3588_GRF_GMAC_CON0 0X0008
> #define RK3588_GRF_CLK_CON1 0X0070
>
> -#define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \
> - (GRF_FIELD(5, 3, PHY_INTF_SEL_RGMII) << ((id) * 6))
> -#define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \
> - (GRF_FIELD(5, 3, PHY_INTF_SEL_RMII) << ((id) * 6))
> +#define RK3588_GMAC_PHY_INTF_SEL(id, val) \
> + (GRF_FIELD(5, 3, val) << ((id) * 6))
>
> #define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id))
> #define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id))
> @@ -1241,7 +1237,7 @@ static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
> RK3588_GRF_GMAC_CON8;
>
> regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
> - RK3588_GMAC_PHY_INTF_SEL_RGMII(id));
> + RK3588_GMAC_PHY_INTF_SEL(id, PHY_INTF_SEL_RGMII));
>
> regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
> RK3588_GMAC_CLK_RGMII_MODE(id));
> @@ -1258,7 +1254,7 @@ static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
> static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
> {
> regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
> - RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->id));
> + RK3588_GMAC_PHY_INTF_SEL(bsp_priv->id, PHY_INTF_SEL_RMII));
>
> regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
> RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id));
> @@ -1328,7 +1324,7 @@ static const struct rk_gmac_ops rk3588_ops = {
> #define RV1108_GRF_GMAC_CON0 0X0900
>
> /* RV1108_GRF_GMAC_CON0 */
> -#define RV1108_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
> +#define RV1108_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val)
> #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3)
> #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
> #define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2)
> @@ -1339,7 +1335,7 @@ static const struct rk_gmac_ops rk3588_ops = {
> static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
> {
> regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
> - RV1108_GMAC_PHY_INTF_SEL_RMII);
> + RV1108_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII));
> }
>
> static const struct rk_reg_speed_data rv1108_reg_speed_data = {
> @@ -1364,8 +1360,7 @@ static const struct rk_gmac_ops rv1108_ops = {
> #define RV1126_GRF_GMAC_CON2 0X0078
>
> /* RV1126_GRF_GMAC_CON0 */
> -#define RV1126_GMAC_PHY_INTF_SEL_RGMII GRF_FIELD(6, 4, PHY_INTF_SEL_RGMII)
> -#define RV1126_GMAC_PHY_INTF_SEL_RMII GRF_FIELD(6, 4, PHY_INTF_SEL_RMII)
> +#define RV1126_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val)
> #define RV1126_GMAC_FLOW_CTRL GRF_BIT(7)
> #define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7)
> #define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1)
> @@ -1388,7 +1383,7 @@ static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
> int tx_delay, int rx_delay)
> {
> regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
> - RV1126_GMAC_PHY_INTF_SEL_RGMII |
> + RV1126_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
> RV1126_GMAC_M0_RXCLK_DLY_ENABLE |
> RV1126_GMAC_M0_TXCLK_DLY_ENABLE |
> RV1126_GMAC_M1_RXCLK_DLY_ENABLE |
> @@ -1406,7 +1401,7 @@ static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
> static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv)
> {
> regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
> - RV1126_GMAC_PHY_INTF_SEL_RMII);
> + RV1126_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII));
> }
>
> static const struct rk_gmac_ops rv1126_ops = {
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH net-next 0/4] net: stmmac: rk: use PHY_INTF_SEL_x
2025-11-13 17:46 [PATCH net-next 0/4] net: stmmac: rk: use PHY_INTF_SEL_x Russell King (Oracle)
` (3 preceding siblings ...)
2025-11-13 17:46 ` [PATCH net-next 4/4] net: stmmac: rk: use PHY_INTF_SEL_x in functions Russell King (Oracle)
@ 2025-11-15 2:40 ` patchwork-bot+netdevbpf
4 siblings, 0 replies; 9+ messages in thread
From: patchwork-bot+netdevbpf @ 2025-11-15 2:40 UTC (permalink / raw)
To: Russell King
Cc: andrew, hkallweit1, alexandre.torgue, andrew+netdev, davem,
edumazet, heiko, kuba, linux-arm-kernel, linux-rockchip,
linux-stm32, mcoquelin.stm32, netdev, pabeni
Hello:
This series was applied to netdev/net-next.git (main)
by Jakub Kicinski <kuba@kernel.org>:
On Thu, 13 Nov 2025 17:46:16 +0000 you wrote:
> This series is a minimal conversion of the dwmac-rk huge driver to use
> PHY_INTF_SEL_x constants.
>
> Patch 2 appears to reorder the output functions making diffing the
> generated code impossible.
>
> drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 245 +++++++++++--------------
> 1 file changed, 109 insertions(+), 136 deletions(-)
Here is the summary with links:
- [net-next,1/4] net: stmmac: rk: replace HIWORD_UPDATE() with GRF_FIELD()
https://git.kernel.org/netdev/net-next/c/ebb07edf9738
- [net-next,2/4] net: stmmac: rk: convert all bitfields to GRF_FIELD*()
https://git.kernel.org/netdev/net-next/c/764ebe423ef9
- [net-next,3/4] net: stmmac: rk: use PHY_INTF_SEL_x constants
https://git.kernel.org/netdev/net-next/c/5e37047f745b
- [net-next,4/4] net: stmmac: rk: use PHY_INTF_SEL_x in functions
https://git.kernel.org/netdev/net-next/c/1188741cb5a2
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply [flat|nested] 9+ messages in thread