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From: Daniel Golle <daniel@makrotopia.org>
To: Andrew Lunn <andrew@lunn.ch>
Cc: Hauke Mehrtens <hauke@hauke-m.de>,
	Vladimir Oltean <olteanv@gmail.com>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Russell King <linux@armlinux.org.uk>,
	netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
	Rasmus Villemoes <ravi@prevas.dk>,
	"Benny (Ying-Tsan) Weng" <yweng@maxlinear.com>,
	John Crispin <john@phrozen.org>
Subject: Re: [PATCH net] net: dsa: mxl-gsw1xx: manually clear RANEG bit
Date: Fri, 5 Dec 2025 13:56:39 +0000	[thread overview]
Message-ID: <aTLkl0Zey4u4P8x6@makrotopia.org> (raw)
In-Reply-To: <97389f24-d900-4ff0-8a80-f75e44163499@lunn.ch>

On Fri, Dec 05, 2025 at 02:45:35PM +0100, Andrew Lunn wrote:
> On Fri, Dec 05, 2025 at 01:32:20AM +0000, Daniel Golle wrote:
> > Despite being documented as self-clearing, the RANEG bit sometimes
> > remains set, preventing auto-negotiation from happening.
> > 
> > Manually clear the RANEG bit after 10ms as advised by MaxLinear, using
> > delayed_work emulating the asynchronous self-clearing behavior.
> 
> Maybe add some text why the complexity of delayed work is used, rather
> than just a msleep(10)?
> 
> Calling regmap_read_poll_timeout() to see if it clears itself could
> optimise this, and still be simpler.

Is the restart_an() operation allowed to sleep? Looking at other
drivers I only ever see that it sets a self-clearing AN RESTART bit,
never waiting for that bit to clear. Hence I wanted to immitate
that behavior by clearing the bit asynchronously. If that's not needed
and msleep(10) or usleep_range(10000, 20000) can be used instead that'd
be much easier, of course.

  reply	other threads:[~2025-12-05 13:56 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-12-05  1:32 [PATCH net] net: dsa: mxl-gsw1xx: manually clear RANEG bit Daniel Golle
2025-12-05 13:45 ` Andrew Lunn
2025-12-05 13:56   ` Daniel Golle [this message]
2025-12-05 14:06     ` Andrew Lunn
2025-12-05 14:06     ` Vladimir Oltean
2025-12-05 15:17     ` Russell King (Oracle)
2025-12-05 15:40       ` Daniel Golle
2025-12-05 15:52         ` Russell King (Oracle)
2025-12-05 19:06           ` Daniel Golle
2025-12-05 15:58         ` Andrew Lunn

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