From: Dan Carpenter <dan.carpenter@linaro.org>
To: Frank Li <Frank.li@nxp.com>
Cc: Chester Lin <chester62515@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Andrew Lunn <andrew+netdev@lunn.ch>,
Conor Dooley <conor+dt@kernel.org>,
"David S. Miller" <davem@davemloft.net>,
devicetree@vger.kernel.org, Eric Dumazet <edumazet@google.com>,
Fabio Estevam <festevam@gmail.com>,
Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>,
imx@lists.linux.dev, Jakub Kicinski <kuba@kernel.org>,
Jan Petrous <jan.petrous@oss.nxp.com>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Lee Jones <lee@kernel.org>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
Matthias Brugger <mbrugger@suse.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
netdev@vger.kernel.org, NXP S32 Linux Team <s32@nxp.com>,
Paolo Abeni <pabeni@redhat.com>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Rob Herring <robh@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Shawn Guo <shawnguo@kernel.org>,
linaro-s32@linaro.org
Subject: Re: [PATCH v2 0/4] s32g: Use a syscon for GPR
Date: Mon, 15 Dec 2025 21:33:54 +0300 [thread overview]
Message-ID: <aUBUkuLf7NHtLSl1@stanley.mountain> (raw)
In-Reply-To: <aUAvwRmIZBC0W6ql@lizhi-Precision-Tower-5810>
On Mon, Dec 15, 2025 at 10:56:49AM -0500, Frank Li wrote:
> On Mon, Dec 15, 2025 at 05:41:43PM +0300, Dan Carpenter wrote:
> > The s32g devices have a GPR register region which holds a number of
> > miscellaneous registers. Currently only the stmmac/dwmac-s32.c uses
> > anything from there and we just add a line to the device tree to
> > access that GMAC_0_CTRL_STS register:
> >
> > reg = <0x4033c000 0x2000>, /* gmac IP */
> > <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */
> >
> > We still have to maintain backwards compatibility to this format,
> > of course, but it would be better to access these through a syscon.
> > First of all, putting all the registers together is more organized
> > and shows how the hardware actually is implemented. Secondly, in
> > some versions of this chipset those registers can only be accessed
> > via SCMI, if the registers aren't grouped together each driver will
> > have to create a whole lot of if then statements to access it via
> > IOMEM or via SCMI,
>
> Does SCMI work as regmap? syscon look likes simple, but missed abstract
> in overall.
>
The SCMI part of this is pretty complicated and needs discussion. It
might be that it requires a vendor extension. Right now, the out of
tree code uses a nvmem vendor extension but that probably won't get
merged upstream.
But in theory, it's fairly simple, you can write a regmap driver and
register it as a syscon and everything that was accessing nxp,phy-sel
accesses the same register but over SCMI.
> You still use regmap by use MMIO. /* GMAC_0_CTRL_STS */
>
> regmap = devm_regmap_init_mmio(dev, sts_offset, ®map_config);
>
You can use have an MMIO syscon, or you can create a custom driver
and register it as a syscon using of_syscon_register_regmap().
> So all code can use regmap function without if-then statements if SCMI work
> as regmap.
>
regards,
dan carpenter
next prev parent reply other threads:[~2025-12-15 18:34 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-15 14:41 [PATCH v2 0/4] s32g: Use a syscon for GPR Dan Carpenter
2025-12-15 14:41 ` [PATCH v2 1/4] net: stmmac: s32: use a syscon for S32_PHY_INTF_SEL_RGMII Dan Carpenter
2025-12-15 14:41 ` [PATCH v2 3/4] dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon Dan Carpenter
2025-12-17 8:37 ` Krzysztof Kozlowski
2025-12-15 15:56 ` [PATCH v2 0/4] s32g: Use a syscon for GPR Frank Li
2025-12-15 18:33 ` Dan Carpenter [this message]
2025-12-15 19:28 ` Frank Li
2025-12-15 20:11 ` Dan Carpenter
2025-12-15 21:07 ` Frank Li
2025-12-16 7:56 ` Dan Carpenter
2025-12-16 14:42 ` Frank Li
2025-12-16 18:30 ` Dan Carpenter
2025-12-17 19:19 ` Frank Li
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