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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yanteng Si , Yao Zi , Vladimir Oltean , Lad Prabhakar , Choong Yong Liang , Maxime Chevallier , Chen-Yu Tsai , Shangjuan Wei , Boon Khai Ng , Quentin Schulz , Giuseppe Cavallaro , Jose Abreu , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Longbin Li Subject: Re: [PATCH net-next 3/3] net: stmmac: Add glue layer for Spacemit K3 SoC Message-ID: References: <20260120043609.910302-1-inochiama@gmail.com> <20260120043609.910302-4-inochiama@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, Jan 20, 2026 at 04:56:32AM +0000, Russell King (Oracle) wrote: > On Tue, Jan 20, 2026 at 12:36:08PM +0800, Inochi Amaoto wrote: > > Adds Spacemit dwmac driver support on the Spacemit K3 SoC. > > Some more information would be useful. E.g. describing why you need to > fix the RGMII mode. > OK. I will add this. > > +/* ctrl register bits */ > > +#define PHY_INTF_RGMII BIT(3) > > +#define PHY_INTF_MII BIT(4) > > + > > +#define WAKE_IRQ_EN BIT(9) > > +#define PHY_IRQ_EN BIT(12) > > + > > +/* dline register bits */ > > +#define RGMII_RX_DLINE_EN BIT(0) > > +#define RGMII_RX_DLINE_STEP GENMASK(5, 4) > > +#define RGMII_RX_DLINE_CODE GENMASK(15, 8) > > +#define RGMII_TX_DLINE_EN BIT(16) > > +#define RGMII_TX_DLINE_STEP GENMASK(21, 20) > > +#define RGMII_TX_DLINE_CODE GENMASK(31, 24) > > + > > +#define MAX_DLINE_DELAY_CODE 0xff > > + > > +struct spacemit_dwmac { > > + struct device *dev; > > + struct clk *tx; > > +}; > > This structure seems unused. > Yeah, I forgot this, will remove in the next version. > > + > > +/* Note: the delay step value is at 0.1ps */ > > +static const unsigned int k3_delay_step_10x[4] = { > > + 367, 493, 559, 685 > > +}; > > + > > +static int spacemit_dwmac_set_delay(struct regmap *apmu, > > + unsigned int dline_offset, > > + unsigned int tx_code, unsigned int tx_config, > > + unsigned int rx_code, unsigned int rx_config) > > +{ > > + unsigned int mask, val; > > + > > + mask = RGMII_RX_DLINE_STEP | RGMII_TX_DLINE_CODE | RGMII_TX_DLINE_EN | > > + RGMII_TX_DLINE_STEP | RGMII_RX_DLINE_CODE | RGMII_RX_DLINE_EN; > > + val = FIELD_PREP(RGMII_TX_DLINE_CODE, tx_config) | > > + FIELD_PREP(RGMII_TX_DLINE_CODE, tx_code) | RGMII_TX_DLINE_EN | > > + FIELD_PREP(RGMII_TX_DLINE_CODE, rx_config) | > > + FIELD_PREP(RGMII_RX_DLINE_CODE, rx_code) | RGMII_RX_DLINE_EN; > > These FIELD_PREP() fields look wrong. Did you mean to use DLINE_CODE > both tx_config and tx_code, and did you mean to use TX_DLINE_CODE for > rx_config ? > This should be RGMII_TX_DLINE_CODE. This is a copy paste error, I will fix it. > > + plat_dat->clk_tx_i = devm_clk_get_enabled(&pdev->dev, "tx"); > > + if (IS_ERR(plat_dat->clk_tx_i)) > > + return dev_err_probe(&pdev->dev, PTR_ERR(plat_dat->clk_tx_i), > > + "failed to get tx clock\n"); > > You set plat_dat->clk_tx_i, but you don't point > plat_dat->set_clk_tx_rate at anything, which means the stmmac core > does nothing with this. > Yes, the vendor told me that the internal tx clock rate will be auto changed when the speed rate is changed. So no software interaction is needed. > Given the last two points, has RGMII mode been tested on this > hardware? > In fact I only tested the rgmii-id, which does not change the internal id. I will try the rgmii mode. Regards, Inochi