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From: "Russell King (Oracle)" <linux@armlinux.org.uk>
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: "Clément Léger" <clement.leger@bootlin.com>,
	"Andrew Lunn" <andrew+netdev@lunn.ch>,
	"David S. Miller" <davem@davemloft.net>,
	"Eric Dumazet" <edumazet@google.com>,
	"Jakub Kicinski" <kuba@kernel.org>,
	"Paolo Abeni" <pabeni@redhat.com>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Heiner Kallweit" <hkallweit1@gmail.com>,
	"Geert Uytterhoeven" <geert+renesas@glider.be>,
	"Magnus Damm" <magnus.damm@gmail.com>,
	linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	"Biju Das" <biju.das.jz@bp.renesas.com>,
	"Fabrizio Castro" <fabrizio.castro.jz@renesas.com>,
	"Lad Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH net-next v2 2/2] net: pcs: rzn1-miic: Add support for PHY link active-level configuration
Date: Fri, 9 Jan 2026 14:46:21 +0000	[thread overview]
Message-ID: <aWEUvef4eDlmuOic@shell.armlinux.org.uk> (raw)
In-Reply-To: <20260109142250.3313448-3-prabhakar.mahadev-lad.rj@bp.renesas.com>

On Fri, Jan 09, 2026 at 02:22:50PM +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Add support to configure the PHY link signal active level per converter
> using the DT property "renesas,miic-phylink-active-low".
> 
> Introduce the MIIC_PHYLINK register definition and extend the MIIC driver
> with a new `phylink` structure to store the mask and value for PHY link
> configuration. Implement `miic_configure_phylink()` to determine the bit
> position and polarity for each port based on the SoC type, such as RZ/N1
> or RZ/T2H/N2H.
> 
> The accumulated configuration is stored during DT parsing and applied
> later in `miic_probe()` after hardware initialization, since the MIIC
> registers can only be modified safely once the hardware setup is complete.

Please do not re-use "phylink", we have a subsystem in the kernel named
as such, and, for example, it too defines "struct phylink".

> +/**
> + * struct phylink - Phylink configuration
> + * @mask: Mask of phylink bits
> + * @val: Value of phylink bits
> + */
> +struct phylink {
> +	u32 mask;
> +	u32 val;
> +};
> +

You don't get a warning for this, because, although you have:

#include <linux/phylink.h>

which delares "struct phylink" as:

struct phylink;

The definition of this structure is entirely private to
drivers/net/phy/phylink.c and is intentionally not exposed.

By redefining "struct phylink" here, it means that anyone using gdb
is going to run into problems - which version of this struct is the
right one for any particular pointer.

You describe this feature as "PHY-link" and "PHY link" in your commit
and cover messages. Please use "phy_link" and "PHY_LINK" as identifies
for this so that grep can distinguish between your PHY link feature
and the phylink infrastructure.

Thanks.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

  reply	other threads:[~2026-01-09 14:46 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-09 14:22 [PATCH net-next v2 0/2] Add support for PHY link active-level configuration in RZN1 MIIC driver Prabhakar
2026-01-09 14:22 ` [PATCH net-next v2 1/2] dt-bindings: net: pcs: renesas,rzn1-miic: Add renesas,miic-phylink-active-low property Prabhakar
2026-01-15 17:22   ` Rob Herring (Arm)
2026-01-09 14:22 ` [PATCH net-next v2 2/2] net: pcs: rzn1-miic: Add support for PHY link active-level configuration Prabhakar
2026-01-09 14:46   ` Russell King (Oracle) [this message]
2026-01-12 12:03     ` Lad, Prabhakar
2026-01-09 15:50   ` Russell King (Oracle)
2026-01-12 12:12     ` Lad, Prabhakar

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