* [PATCH net-next 00/21] net: stmmac: rk: simplify per-SoC configuration
@ 2026-01-23 10:59 Russell King (Oracle)
2026-01-23 11:00 ` [PATCH net-next 01/21] net: stmmac: rk: avoid phy_power_on() Russell King (Oracle)
` (20 more replies)
0 siblings, 21 replies; 31+ messages in thread
From: Russell King (Oracle) @ 2026-01-23 10:59 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, netdev, Paolo Abeni
[Please note: due to google's spam filtering, I can no longer send
patch series to @gmail.com addresses, and thus, to save being spammed
with failed deliveries, I'm dropping such addresses from my patch
series. Stop giving google so much power, use other email services.]
dwmac-rk has an excessive variability between each individual SoCs
which makes this file extremely large.
This series reworks the per-SoC handling, moving the majority of it
out of code and into data in a way that greatly reduces the lines of
code necessary for each SoC, moving the code into the higher level
functions in this file.
In order to do this, we need a version of FIELD_PREP_WM16() that works
with non-constant masks, so we introduce rk_encode_wm16().
We change the definitions to reveal the fact that in all of this
variability, there is a lot of commonality in terms of the values of
the bitfields, even though these bitfields appear to be randomly
placed within registers.
Both of these allow us to progressively move to a situation where
the SoC independent code can, in the mojority of cases, program these
RGMII clocks, RMII clocks and RMII speed without calling any SoC
specific code.
Further cleanup may be possible with the (actually incorrect) handling
of RGMII delays, but this is not addressed in this already large
series.
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 1220 ++++++++++--------------
1 file changed, 491 insertions(+), 729 deletions(-)
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH net-next 01/21] net: stmmac: rk: avoid phy_power_on()
2026-01-23 10:59 [PATCH net-next 00/21] net: stmmac: rk: simplify per-SoC configuration Russell King (Oracle)
@ 2026-01-23 11:00 ` Russell King (Oracle)
2026-01-23 11:00 ` [PATCH net-next 02/21] net: stmmac: rk: get rid of rk_phy_power_ctl() Russell King (Oracle)
` (19 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Russell King (Oracle) @ 2026-01-23 11:00 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, netdev, Paolo Abeni
In https://lore.kernel.org/netdev/aDne1Ybuvbk0AwG0@shell.armlinux.org.uk/
I requested that a follow-up patch to change the name of dwmac-rk's
phy_power_on() function, which clashes with the drivers/phy function
of the same name. This can cause confusion when grepping for this
function name, or when reviewing code. Thankfully, stmmac doesn't make
use of drivers/phy which saves this from compile errors.
However, as is the usual case when a request is made as part of a
review, if the review leads to successful application of the patch the
author doesn't bother following up with any such requests, and so the
problem falls back onto the reviewer to address... so here is the
solution.
Rename dwmac-rk's function to rk_phy_power_ctl(), as the function both
powers up and down.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 0a95f54e725e..de420997e21f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -1498,7 +1498,7 @@ static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
return 0;
}
-static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
+static int rk_phy_power_ctl(struct rk_priv_data *bsp_priv, bool enable)
{
struct regulator *ldo = bsp_priv->regulator;
struct device *dev = bsp_priv->dev;
@@ -1692,7 +1692,7 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
dev_err(dev, "NO interface defined!\n");
}
- ret = phy_power_on(bsp_priv, true);
+ ret = rk_phy_power_ctl(bsp_priv, true);
if (ret) {
gmac_clk_enable(bsp_priv, false);
return ret;
@@ -1713,7 +1713,7 @@ static void rk_gmac_powerdown(struct rk_priv_data *gmac)
pm_runtime_put_sync(gmac->dev);
- phy_power_on(gmac, false);
+ rk_phy_power_ctl(gmac, false);
gmac_clk_enable(gmac, false);
}
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH net-next 02/21] net: stmmac: rk: get rid of rk_phy_power_ctl()
2026-01-23 10:59 [PATCH net-next 00/21] net: stmmac: rk: simplify per-SoC configuration Russell King (Oracle)
2026-01-23 11:00 ` [PATCH net-next 01/21] net: stmmac: rk: avoid phy_power_on() Russell King (Oracle)
@ 2026-01-23 11:00 ` Russell King (Oracle)
2026-01-23 11:00 ` [PATCH net-next 03/21] net: stmmac: rk: convert rk3328 to use bsp_priv->id Russell King (Oracle)
` (18 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Russell King (Oracle) @ 2026-01-23 11:00 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, netdev, Paolo Abeni
It is not worth having a common rk_phy_power_ctl() when the only
difference is which regulator function is called. Also, passing
true/false is non-descriptive. Split this function, moving the code
appropriately into rk_phy_powerup() and rk_phy_powerdown().
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 31 ++++++++++---------
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index de420997e21f..0e66252eb5ae 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -1498,23 +1498,26 @@ static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
return 0;
}
-static int rk_phy_power_ctl(struct rk_priv_data *bsp_priv, bool enable)
+static int rk_phy_powerup(struct rk_priv_data *bsp_priv)
{
struct regulator *ldo = bsp_priv->regulator;
- struct device *dev = bsp_priv->dev;
int ret;
- if (enable) {
- ret = regulator_enable(ldo);
- if (ret)
- dev_err(dev, "fail to enable phy-supply\n");
- } else {
- ret = regulator_disable(ldo);
- if (ret)
- dev_err(dev, "fail to disable phy-supply\n");
- }
+ ret = regulator_enable(ldo);
+ if (ret)
+ dev_err(bsp_priv->dev, "fail to enable phy-supply\n");
- return 0;
+ return ret;
+}
+
+static void rk_phy_powerdown(struct rk_priv_data *bsp_priv)
+{
+ struct regulator *ldo = bsp_priv->regulator;
+ int ret;
+
+ ret = regulator_disable(ldo);
+ if (ret)
+ dev_err(bsp_priv->dev, "fail to disable phy-supply\n");
}
static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
@@ -1692,7 +1695,7 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
dev_err(dev, "NO interface defined!\n");
}
- ret = rk_phy_power_ctl(bsp_priv, true);
+ ret = rk_phy_powerup(bsp_priv);
if (ret) {
gmac_clk_enable(bsp_priv, false);
return ret;
@@ -1713,7 +1716,7 @@ static void rk_gmac_powerdown(struct rk_priv_data *gmac)
pm_runtime_put_sync(gmac->dev);
- rk_phy_power_ctl(gmac, false);
+ rk_phy_powerdown(gmac);
gmac_clk_enable(gmac, false);
}
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH net-next 03/21] net: stmmac: rk: convert rk3328 to use bsp_priv->id
2026-01-23 10:59 [PATCH net-next 00/21] net: stmmac: rk: simplify per-SoC configuration Russell King (Oracle)
2026-01-23 11:00 ` [PATCH net-next 01/21] net: stmmac: rk: avoid phy_power_on() Russell King (Oracle)
2026-01-23 11:00 ` [PATCH net-next 02/21] net: stmmac: rk: get rid of rk_phy_power_ctl() Russell King (Oracle)
@ 2026-01-23 11:00 ` Russell King (Oracle)
2026-01-25 22:16 ` [net-next,03/21] " Jakub Kicinski
2026-01-23 11:00 ` [PATCH net-next 04/21] net: stmmac: rk: group MACPHY register offset and fields together Russell King (Oracle)
` (17 subsequent siblings)
20 siblings, 1 reply; 31+ messages in thread
From: Russell King (Oracle) @ 2026-01-23 11:00 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, netdev, Paolo Abeni
rk3328 contains two GMAC instances - gmac2io and gmac2phy. While the
gmac2io instance may be connected to an external PHY, the gmac2phy
instance is permanently connected via RMII to an on-SoC integrated PHY.
The driver currently tests for the gmac2phy instance by checking
bsp_priv->integrated_phy (determined from the PHY's phy-is-integrated
property) and sometimes that the interface mode is RMII. This works
because the rk3328.dtsi has:
gmac2phy: ethernet@ff550000 {
compatible = "rockchip,rk3328-gmac";
phy-mode = "rmii";
phy-handle = <&phy>;
mdio {
phy: ethernet-phy@0 {
phy-is-integrated;
};
};
};
The driver contains a mechanism to look up the MMIO address in a table
to determine bsp_priv->id, which is used for every other Rockchip
device. Switch rk3328 to use this mechanism to determine bsp_priv->id
and use that to select which GRF register is used for configuration,
similarly to how the other Rockchip SoCs handle such differences.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 0e66252eb5ae..c8b49ed2064a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -570,8 +570,7 @@ static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
{
unsigned int reg;
- reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
- RK3328_GRF_MAC_CON1;
+ reg = bsp_priv->id ? RK3328_GRF_MAC_CON2 : RK3328_GRF_MAC_CON1;
regmap_write(bsp_priv->grf, reg,
RK3328_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
@@ -591,10 +590,7 @@ static int rk3328_set_speed(struct rk_priv_data *bsp_priv,
{
unsigned int reg;
- if (interface == PHY_INTERFACE_MODE_RMII && bsp_priv->integrated_phy)
- reg = RK3328_GRF_MAC_CON2;
- else
- reg = RK3328_GRF_MAC_CON1;
+ reg = bsp_priv->id ? RK3328_GRF_MAC_CON2 : RK3328_GRF_MAC_CON1;
return rk_set_reg_speed(bsp_priv, &rk3328_reg_speed_data, reg,
interface, speed);
@@ -614,6 +610,13 @@ static const struct rk_gmac_ops rk3328_ops = {
.set_speed = rk3328_set_speed,
.integrated_phy_powerup = rk3328_integrated_phy_powerup,
.integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,
+
+ .regs_valid = true,
+ .regs = {
+ 0xff540000, /* gmac2io */
+ 0xff550000, /* gmac2phy */
+ 0, /* sentinel */
+ },
};
#define RK3366_GRF_SOC_CON6 0x0418
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH net-next 04/21] net: stmmac: rk: group MACPHY register offset and fields together
2026-01-23 10:59 [PATCH net-next 00/21] net: stmmac: rk: simplify per-SoC configuration Russell King (Oracle)
` (2 preceding siblings ...)
2026-01-23 11:00 ` [PATCH net-next 03/21] net: stmmac: rk: convert rk3328 to use bsp_priv->id Russell King (Oracle)
@ 2026-01-23 11:00 ` Russell King (Oracle)
2026-01-23 11:00 ` [PATCH net-next 05/21] net: stmmac: rk: add GMAC_CLK_xx constants, simplify RGMII definitions Russell King (Oracle)
` (16 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Russell King (Oracle) @ 2026-01-23 11:00 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, netdev, Paolo Abeni
Group the MACPHY register offsets and associated bitfields together
to become self-documenting which definitions are associated with
which register.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index c8b49ed2064a..5f8d2031b97c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -162,15 +162,17 @@ static int rk_set_clk_mac_speed(struct rk_priv_data *bsp_priv,
((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
#define RK_GRF_MACPHY_CON0 0xb00
-#define RK_GRF_MACPHY_CON1 0xb04
-#define RK_GRF_MACPHY_CON2 0xb08
-#define RK_GRF_MACPHY_CON3 0xb0c
-
#define RK_MACPHY_ENABLE GRF_BIT(0)
#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
#define RK_GMAC2PHY_RMII_MODE GRF_FIELD(7, 6, 1)
+
+#define RK_GRF_MACPHY_CON1 0xb04
+
+#define RK_GRF_MACPHY_CON2 0xb08
#define RK_GRF_CON2_MACPHY_ID GRF_FIELD(15, 0, 0x1234)
+
+#define RK_GRF_MACPHY_CON3 0xb0c
#define RK_GRF_CON3_MACPHY_ID GRF_FIELD(5, 0, 0x35)
static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv)
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH net-next 05/21] net: stmmac: rk: add GMAC_CLK_xx constants, simplify RGMII definitions
2026-01-23 10:59 [PATCH net-next 00/21] net: stmmac: rk: simplify per-SoC configuration Russell King (Oracle)
` (3 preceding siblings ...)
2026-01-23 11:00 ` [PATCH net-next 04/21] net: stmmac: rk: group MACPHY register offset and fields together Russell King (Oracle)
@ 2026-01-23 11:00 ` Russell King (Oracle)
2026-01-23 11:00 ` [PATCH net-next 06/21] net: stmmac: rk: add SoC specific ->init() method Russell King (Oracle)
` (15 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Russell King (Oracle) @ 2026-01-23 11:00 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, netdev, Paolo Abeni
All the definitions of the RGMII related xxx_GMAC_CLK_xxx definitions
use the same field values to select the clock rate. Provide common
defintions for these field values, passing them in to a single macro
for each variant that generates the appropriate values for the speed
register.
No change to produced code on aarch64.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 108 ++++++++----------
1 file changed, 45 insertions(+), 63 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 5f8d2031b97c..7f8ffd1549bc 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -91,6 +91,10 @@ struct rk_priv_data {
struct regmap *php_grf;
};
+#define GMAC_CLK_DIV1_125M 0
+#define GMAC_CLK_DIV50_2_5M 2
+#define GMAC_CLK_DIV5_25M 3
+
static int rk_set_reg_speed(struct rk_priv_data *bsp_priv,
const struct rk_reg_speed_data *rsd,
unsigned int reg, phy_interface_t interface,
@@ -299,9 +303,7 @@ static const struct rk_gmac_ops px30_ops = {
#define RK3128_GMAC_SPEED_100M GRF_BIT(10)
#define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11)
#define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
-#define RK3128_GMAC_CLK_125M GRF_FIELD_CONST(13, 12, 0)
-#define RK3128_GMAC_CLK_25M GRF_FIELD_CONST(13, 12, 3)
-#define RK3128_GMAC_CLK_2_5M GRF_FIELD_CONST(13, 12, 2)
+#define RK3128_GMAC_CLK(val) GRF_FIELD_CONST(13, 12, val)
#define RK3128_GMAC_RMII_MODE GRF_BIT(14)
#define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
@@ -325,9 +327,9 @@ static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3128_reg_speed_data = {
- .rgmii_10 = RK3128_GMAC_CLK_2_5M,
- .rgmii_100 = RK3128_GMAC_CLK_25M,
- .rgmii_1000 = RK3128_GMAC_CLK_125M,
+ .rgmii_10 = RK3128_GMAC_CLK(GMAC_CLK_DIV50_2_5M),
+ .rgmii_100 = RK3128_GMAC_CLK(GMAC_CLK_DIV5_25M),
+ .rgmii_1000 = RK3128_GMAC_CLK(GMAC_CLK_DIV1_125M),
.rmii_10 = RK3128_GMAC_RMII_CLK_2_5M | RK3128_GMAC_SPEED_10M,
.rmii_100 = RK3128_GMAC_RMII_CLK_25M | RK3128_GMAC_SPEED_100M,
};
@@ -362,9 +364,7 @@ static const struct rk_gmac_ops rk3128_ops = {
#define RK3228_GMAC_SPEED_100M GRF_BIT(2)
#define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7)
#define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
-#define RK3228_GMAC_CLK_125M GRF_FIELD_CONST(9, 8, 0)
-#define RK3228_GMAC_CLK_25M GRF_FIELD_CONST(9, 8, 3)
-#define RK3228_GMAC_CLK_2_5M GRF_FIELD_CONST(9, 8, 2)
+#define RK3228_GMAC_CLK(val) GRF_FIELD_CONST(9, 8, val)
#define RK3228_GMAC_RMII_MODE GRF_BIT(10)
#define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10)
#define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
@@ -399,9 +399,9 @@ static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3228_reg_speed_data = {
- .rgmii_10 = RK3228_GMAC_CLK_2_5M,
- .rgmii_100 = RK3228_GMAC_CLK_25M,
- .rgmii_1000 = RK3228_GMAC_CLK_125M,
+ .rgmii_10 = RK3228_GMAC_CLK(GMAC_CLK_DIV50_2_5M),
+ .rgmii_100 = RK3228_GMAC_CLK(GMAC_CLK_DIV5_25M),
+ .rgmii_1000 = RK3228_GMAC_CLK(GMAC_CLK_DIV1_125M),
.rmii_10 = RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_SPEED_10M,
.rmii_100 = RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_SPEED_100M,
};
@@ -440,9 +440,7 @@ static const struct rk_gmac_ops rk3228_ops = {
#define RK3288_GMAC_SPEED_100M GRF_BIT(10)
#define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11)
#define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
-#define RK3288_GMAC_CLK_125M GRF_FIELD_CONST(13, 12, 0)
-#define RK3288_GMAC_CLK_25M GRF_FIELD_CONST(13, 12, 3)
-#define RK3288_GMAC_CLK_2_5M GRF_FIELD_CONST(13, 12, 2)
+#define RK3288_GMAC_CLK(val) GRF_FIELD_CONST(13, 12, val)
#define RK3288_GMAC_RMII_MODE GRF_BIT(14)
#define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
@@ -474,9 +472,9 @@ static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3288_reg_speed_data = {
- .rgmii_10 = RK3288_GMAC_CLK_2_5M,
- .rgmii_100 = RK3288_GMAC_CLK_25M,
- .rgmii_1000 = RK3288_GMAC_CLK_125M,
+ .rgmii_10 = RK3288_GMAC_CLK(GMAC_CLK_DIV50_2_5M),
+ .rgmii_100 = RK3288_GMAC_CLK(GMAC_CLK_DIV5_25M),
+ .rgmii_1000 = RK3288_GMAC_CLK(GMAC_CLK_DIV1_125M),
.rmii_10 = RK3288_GMAC_RMII_CLK_2_5M | RK3288_GMAC_SPEED_10M,
.rmii_100 = RK3288_GMAC_RMII_CLK_25M | RK3288_GMAC_SPEED_100M,
};
@@ -543,9 +541,7 @@ static const struct rk_gmac_ops rk3308_ops = {
#define RK3328_GMAC_SPEED_100M GRF_BIT(2)
#define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7)
#define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
-#define RK3328_GMAC_CLK_125M GRF_FIELD_CONST(12, 11, 0)
-#define RK3328_GMAC_CLK_25M GRF_FIELD_CONST(12, 11, 3)
-#define RK3328_GMAC_CLK_2_5M GRF_FIELD_CONST(12, 11, 2)
+#define RK3328_GMAC_CLK(val) GRF_FIELD_CONST(12, 11, val)
#define RK3328_GMAC_RMII_MODE GRF_BIT(9)
#define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9)
#define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
@@ -580,9 +576,9 @@ static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3328_reg_speed_data = {
- .rgmii_10 = RK3328_GMAC_CLK_2_5M,
- .rgmii_100 = RK3328_GMAC_CLK_25M,
- .rgmii_1000 = RK3328_GMAC_CLK_125M,
+ .rgmii_10 = RK3328_GMAC_CLK(GMAC_CLK_DIV50_2_5M),
+ .rgmii_100 = RK3328_GMAC_CLK(GMAC_CLK_DIV5_25M),
+ .rgmii_1000 = RK3328_GMAC_CLK(GMAC_CLK_DIV1_125M),
.rmii_10 = RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_SPEED_10M,
.rmii_100 = RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_SPEED_100M,
};
@@ -632,9 +628,7 @@ static const struct rk_gmac_ops rk3328_ops = {
#define RK3366_GMAC_SPEED_100M GRF_BIT(7)
#define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3)
#define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
-#define RK3366_GMAC_CLK_125M GRF_FIELD_CONST(5, 4, 0)
-#define RK3366_GMAC_CLK_25M GRF_FIELD_CONST(5, 4, 3)
-#define RK3366_GMAC_CLK_2_5M GRF_FIELD_CONST(5, 4, 2)
+#define RK3366_GMAC_CLK(val) GRF_FIELD_CONST(5, 4, val)
#define RK3366_GMAC_RMII_MODE GRF_BIT(6)
#define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
@@ -666,9 +660,9 @@ static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3366_reg_speed_data = {
- .rgmii_10 = RK3366_GMAC_CLK_2_5M,
- .rgmii_100 = RK3366_GMAC_CLK_25M,
- .rgmii_1000 = RK3366_GMAC_CLK_125M,
+ .rgmii_10 = RK3366_GMAC_CLK(GMAC_CLK_DIV50_2_5M),
+ .rgmii_100 = RK3366_GMAC_CLK(GMAC_CLK_DIV5_25M),
+ .rgmii_1000 = RK3366_GMAC_CLK(GMAC_CLK_DIV1_125M),
.rmii_10 = RK3366_GMAC_RMII_CLK_2_5M | RK3366_GMAC_SPEED_10M,
.rmii_100 = RK3366_GMAC_RMII_CLK_25M | RK3366_GMAC_SPEED_100M,
};
@@ -697,9 +691,7 @@ static const struct rk_gmac_ops rk3366_ops = {
#define RK3368_GMAC_SPEED_100M GRF_BIT(7)
#define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3)
#define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
-#define RK3368_GMAC_CLK_125M GRF_FIELD_CONST(5, 4, 0)
-#define RK3368_GMAC_CLK_25M GRF_FIELD_CONST(5, 4, 3)
-#define RK3368_GMAC_CLK_2_5M GRF_FIELD_CONST(5, 4, 2)
+#define RK3368_GMAC_CLK(val) GRF_FIELD_CONST(5, 4, val)
#define RK3368_GMAC_RMII_MODE GRF_BIT(6)
#define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
@@ -731,9 +723,9 @@ static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3368_reg_speed_data = {
- .rgmii_10 = RK3368_GMAC_CLK_2_5M,
- .rgmii_100 = RK3368_GMAC_CLK_25M,
- .rgmii_1000 = RK3368_GMAC_CLK_125M,
+ .rgmii_10 = RK3368_GMAC_CLK(GMAC_CLK_DIV50_2_5M),
+ .rgmii_100 = RK3368_GMAC_CLK(GMAC_CLK_DIV5_25M),
+ .rgmii_1000 = RK3368_GMAC_CLK(GMAC_CLK_DIV1_125M),
.rmii_10 = RK3368_GMAC_RMII_CLK_2_5M | RK3368_GMAC_SPEED_10M,
.rmii_100 = RK3368_GMAC_RMII_CLK_25M | RK3368_GMAC_SPEED_100M,
};
@@ -762,9 +754,7 @@ static const struct rk_gmac_ops rk3368_ops = {
#define RK3399_GMAC_SPEED_100M GRF_BIT(7)
#define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3)
#define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
-#define RK3399_GMAC_CLK_125M GRF_FIELD_CONST(5, 4, 0)
-#define RK3399_GMAC_CLK_25M GRF_FIELD_CONST(5, 4, 3)
-#define RK3399_GMAC_CLK_2_5M GRF_FIELD_CONST(5, 4, 2)
+#define RK3399_GMAC_CLK(val) GRF_FIELD_CONST(5, 4, val)
#define RK3399_GMAC_RMII_MODE GRF_BIT(6)
#define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
@@ -796,9 +786,9 @@ static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3399_reg_speed_data = {
- .rgmii_10 = RK3399_GMAC_CLK_2_5M,
- .rgmii_100 = RK3399_GMAC_CLK_25M,
- .rgmii_1000 = RK3399_GMAC_CLK_125M,
+ .rgmii_10 = RK3399_GMAC_CLK(GMAC_CLK_DIV50_2_5M),
+ .rgmii_100 = RK3399_GMAC_CLK(GMAC_CLK_DIV5_25M),
+ .rgmii_1000 = RK3399_GMAC_CLK(GMAC_CLK_DIV1_125M),
.rmii_10 = RK3399_GMAC_RMII_CLK_2_5M | RK3399_GMAC_SPEED_10M,
.rmii_100 = RK3399_GMAC_RMII_CLK_25M | RK3399_GMAC_SPEED_100M,
};
@@ -905,9 +895,7 @@ static const struct rk_gmac_ops rk3506_ops = {
#define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10)
#define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10)
-#define RK3528_GMAC1_CLK_RGMII_DIV1 GRF_FIELD_CONST(11, 10, 0)
-#define RK3528_GMAC1_CLK_RGMII_DIV5 GRF_FIELD_CONST(11, 10, 3)
-#define RK3528_GMAC1_CLK_RGMII_DIV50 GRF_FIELD_CONST(11, 10, 2)
+#define RK3528_GMAC1_CLK_RGMII(val) GRF_FIELD_CONST(11, 10, val)
#define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2)
#define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2)
@@ -945,9 +933,9 @@ static const struct rk_reg_speed_data rk3528_gmac0_reg_speed_data = {
};
static const struct rk_reg_speed_data rk3528_gmac1_reg_speed_data = {
- .rgmii_10 = RK3528_GMAC1_CLK_RGMII_DIV50,
- .rgmii_100 = RK3528_GMAC1_CLK_RGMII_DIV5,
- .rgmii_1000 = RK3528_GMAC1_CLK_RGMII_DIV1,
+ .rgmii_10 = RK3528_GMAC1_CLK_RGMII(GMAC_CLK_DIV50_2_5M),
+ .rgmii_100 = RK3528_GMAC1_CLK_RGMII(GMAC_CLK_DIV5_25M),
+ .rgmii_1000 = RK3528_GMAC1_CLK_RGMII(GMAC_CLK_DIV1_125M),
.rmii_10 = RK3528_GMAC1_CLK_RMII_DIV20,
.rmii_100 = RK3528_GMAC1_CLK_RMII_DIV2,
};
@@ -1099,9 +1087,7 @@ static const struct rk_gmac_ops rk3568_ops = {
#define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5)
#define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5)
-#define RK3576_GMAC_CLK_RGMII_DIV1 GRF_FIELD_CONST(6, 5, 0)
-#define RK3576_GMAC_CLK_RGMII_DIV5 GRF_FIELD_CONST(6, 5, 3)
-#define RK3576_GMAC_CLK_RGMII_DIV50 GRF_FIELD_CONST(6, 5, 2)
+#define RK3576_GMAC_CLK_RGMII(val) GRF_FIELD_CONST(6, 5, val)
#define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4)
#define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4)
@@ -1145,9 +1131,9 @@ static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3578_reg_speed_data = {
- .rgmii_10 = RK3576_GMAC_CLK_RGMII_DIV50,
- .rgmii_100 = RK3576_GMAC_CLK_RGMII_DIV5,
- .rgmii_1000 = RK3576_GMAC_CLK_RGMII_DIV1,
+ .rgmii_10 = RK3576_GMAC_CLK_RGMII(GMAC_CLK_DIV50_2_5M),
+ .rgmii_100 = RK3576_GMAC_CLK_RGMII(GMAC_CLK_DIV5_25M),
+ .rgmii_1000 = RK3576_GMAC_CLK_RGMII(GMAC_CLK_DIV1_125M),
.rmii_10 = RK3576_GMAC_CLK_RMII_DIV20,
.rmii_100 = RK3576_GMAC_CLK_RMII_DIV2,
};
@@ -1223,12 +1209,8 @@ static const struct rk_gmac_ops rk3576_ops = {
#define RK3588_GMA_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2)
#define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2)
-#define RK3588_GMAC_CLK_RGMII_DIV1(id) \
- (GRF_FIELD_CONST(3, 2, 0) << ((id) * 5))
-#define RK3588_GMAC_CLK_RGMII_DIV5(id) \
- (GRF_FIELD_CONST(3, 2, 3) << ((id) * 5))
-#define RK3588_GMAC_CLK_RGMII_DIV50(id) \
- (GRF_FIELD_CONST(3, 2, 2) << ((id) * 5))
+#define RK3588_GMAC_CLK_RGMII(id, val) \
+ (GRF_FIELD_CONST(3, 2, val) << ((id) * 5))
#define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1)
#define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1)
@@ -1275,17 +1257,17 @@ static int rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv,
if (interface == PHY_INTERFACE_MODE_RMII)
val = RK3588_GMA_CLK_RMII_DIV20(id);
else
- val = RK3588_GMAC_CLK_RGMII_DIV50(id);
+ val = RK3588_GMAC_CLK_RGMII(id, GMAC_CLK_DIV50_2_5M);
break;
case 100:
if (interface == PHY_INTERFACE_MODE_RMII)
val = RK3588_GMA_CLK_RMII_DIV2(id);
else
- val = RK3588_GMAC_CLK_RGMII_DIV5(id);
+ val = RK3588_GMAC_CLK_RGMII(id, GMAC_CLK_DIV5_25M);
break;
case 1000:
if (interface != PHY_INTERFACE_MODE_RMII)
- val = RK3588_GMAC_CLK_RGMII_DIV1(id);
+ val = RK3588_GMAC_CLK_RGMII(id, GMAC_CLK_DIV1_125M);
else
goto err;
break;
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH net-next 06/21] net: stmmac: rk: add SoC specific ->init() method
2026-01-23 10:59 [PATCH net-next 00/21] net: stmmac: rk: simplify per-SoC configuration Russell King (Oracle)
` (4 preceding siblings ...)
2026-01-23 11:00 ` [PATCH net-next 05/21] net: stmmac: rk: add GMAC_CLK_xx constants, simplify RGMII definitions Russell King (Oracle)
@ 2026-01-23 11:00 ` Russell King (Oracle)
2026-01-23 11:00 ` [PATCH net-next 07/21] net: stmmac: rk: convert to mask-based interface mode configuration Russell King (Oracle)
` (14 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Russell King (Oracle) @ 2026-01-23 11:00 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, netdev, Paolo Abeni
Add a SoC specific init method.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 7f8ffd1549bc..4117f6863ff0 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -35,6 +35,7 @@ struct rk_reg_speed_data {
};
struct rk_gmac_ops {
+ int (*init)(struct rk_priv_data *bsp_priv);
void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay);
void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
@@ -1618,6 +1619,14 @@ static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
bsp_priv->dev = dev;
+ if (ops->init) {
+ ret = ops->init(bsp_priv);
+ if (ret) {
+ dev_err_probe(dev, ret, "failed to init BSP\n");
+ return ERR_PTR(ret);
+ }
+ }
+
return bsp_priv;
}
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH net-next 07/21] net: stmmac: rk: convert to mask-based interface mode configuration
2026-01-23 10:59 [PATCH net-next 00/21] net: stmmac: rk: simplify per-SoC configuration Russell King (Oracle)
` (5 preceding siblings ...)
2026-01-23 11:00 ` [PATCH net-next 06/21] net: stmmac: rk: add SoC specific ->init() method Russell King (Oracle)
@ 2026-01-23 11:00 ` Russell King (Oracle)
2026-01-25 22:16 ` [net-next,07/21] " Jakub Kicinski
2026-01-23 11:00 ` [PATCH net-next 08/21] net: stmmac: rk: move speed GRF register offset to private data Russell King (Oracle)
` (13 subsequent siblings)
20 siblings, 1 reply; 31+ messages in thread
From: Russell King (Oracle) @ 2026-01-23 11:00 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, netdev, Paolo Abeni
The majority of Rockchip implementations require three common pieces
of information to configure the PHY interface mode:
- The grf register offset for configuring the GMAC phy_intf_sel field
and the RMII mode bit.
- The bitfield in this register for the GMAC's phy_intf_sel.
- The bit position for RMII mode but clear for RGMII mode.
Introduce members for this information into struct rk_priv_data and
struct rk_gmac_ops, which will be used to pre-initialise the struct
rk_priv_data members. We describe the register contents using
bitfields, even for those that are a single bit for consistency.
As each register comprises of two halves, where the upper half enables
changing the bit state in the lower half, we can describe these
bitfields using a 16-bit data type, and provide rk_encode_wm16() to
generate the actual register values from the field mask and field
value. We are unable to use the FIELD_PREP_WM16() macros for this as
these require the field mask to be a constant.
Add code to rk_gmac_powerup() to get the phy_intf_sel value, validating
that the resulting mode is either RMII or RGMII. No other modes are
supported by any of the Rockchip SoCs supported by this driver.
If either of the bitfield mask values are populated in struct
rk_priv_data, use these to generate the register contents, and write
the resulting value to the specified GRF register.
Convert many Rockchip implementations to use this new infrastructure.
For those where there is a single GMAC instance, it is merely a case of
filling in the new members of struct rk_gmac_ops. For those with
multiple instances, one or more of these members depends on the GMAC
instance, so setup of the members in struct rk_gmac has to be done via
the .init method of struct rk_gmac_ops. The corresponding code is
removed from the set_to_rgmii() and set_to_rmii() implementations.
Since the member name documents the purpose of the field that is being
initialised, providing preprocessor macros to define the bitfields is
deemed to be less than useful given the massive size of this driver.
The existing mechanisms remain behind for those SoCs that can not be
converted to this scheme.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 281 +++++++++++-------
1 file changed, 171 insertions(+), 110 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 4117f6863ff0..48fc5b58092f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -45,6 +45,11 @@ struct rk_gmac_ops {
bool enable);
void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
void (*integrated_phy_powerdown)(struct rk_priv_data *bsp_priv);
+
+ u16 gmac_grf_reg;
+ u16 gmac_phy_intf_sel_mask;
+ u16 gmac_rmii_mode_mask;
+
bool php_grf_required;
bool regs_valid;
u32 regs[];
@@ -90,12 +95,37 @@ struct rk_priv_data {
struct regmap *grf;
struct regmap *php_grf;
+
+ u16 gmac_grf_reg;
+ u16 gmac_phy_intf_sel_mask;
+ u16 gmac_rmii_mode_mask;
};
#define GMAC_CLK_DIV1_125M 0
#define GMAC_CLK_DIV50_2_5M 2
#define GMAC_CLK_DIV5_25M 3
+static int rk_get_phy_intf_sel(phy_interface_t interface)
+{
+ int ret = stmmac_get_phy_intf_sel(interface);
+
+ /* Only RGMII and RMII are supported */
+ if (ret != PHY_INTF_SEL_RGMII && ret != PHY_INTF_SEL_RMII)
+ ret = -EINVAL;
+
+ return ret;
+}
+
+static u32 rk_encode_wm16(u16 val, u16 mask)
+{
+ u32 reg_val = mask << 16;
+
+ if (mask)
+ reg_val |= mask & (val << (ffs(mask) - 1));
+
+ return reg_val;
+}
+
static int rk_set_reg_speed(struct rk_priv_data *bsp_priv,
const struct rk_reg_speed_data *rsd,
unsigned int reg, phy_interface_t interface,
@@ -241,14 +271,11 @@ static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv,
#define PX30_GRF_GMAC_CON1 0x0904
/* PX30_GRF_GMAC_CON1 */
-#define PX30_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val)
#define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2)
#define PX30_GMAC_SPEED_100M GRF_BIT(2)
static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)
{
- regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
- PX30_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII));
}
static int px30_set_speed(struct rk_priv_data *bsp_priv,
@@ -283,6 +310,9 @@ static int px30_set_speed(struct rk_priv_data *bsp_priv,
static const struct rk_gmac_ops px30_ops = {
.set_to_rmii = px30_set_to_rmii,
.set_speed = px30_set_speed,
+
+ .gmac_grf_reg = PX30_GRF_GMAC_CON1,
+ .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
};
#define RK3128_GRF_MAC_CON0 0x0168
@@ -297,7 +327,6 @@ static const struct rk_gmac_ops px30_ops = {
#define RK3128_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
/* RK3128_GRF_MAC_CON1 */
-#define RK3128_GMAC_PHY_INTF_SEL(val) GRF_FIELD(8, 6, val)
#define RK3128_GMAC_FLOW_CTRL GRF_BIT(9)
#define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
#define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10)
@@ -305,15 +334,10 @@ static const struct rk_gmac_ops px30_ops = {
#define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11)
#define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
#define RK3128_GMAC_CLK(val) GRF_FIELD_CONST(13, 12, val)
-#define RK3128_GMAC_RMII_MODE GRF_BIT(14)
-#define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
- regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
- RK3128_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
- RK3128_GMAC_RMII_MODE_CLR);
regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
DELAY_ENABLE(RK3128, tx_delay, rx_delay) |
RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) |
@@ -322,9 +346,6 @@ static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
{
- regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
- RK3128_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
- RK3128_GMAC_RMII_MODE);
}
static const struct rk_reg_speed_data rk3128_reg_speed_data = {
@@ -346,6 +367,10 @@ static const struct rk_gmac_ops rk3128_ops = {
.set_to_rgmii = rk3128_set_to_rgmii,
.set_to_rmii = rk3128_set_to_rmii,
.set_speed = rk3128_set_speed,
+
+ .gmac_grf_reg = RK3128_GRF_MAC_CON1,
+ .gmac_phy_intf_sel_mask = GENMASK_U16(8, 6),
+ .gmac_rmii_mode_mask = BIT_U16(14),
};
#define RK3228_GRF_MAC_CON0 0x0900
@@ -358,7 +383,6 @@ static const struct rk_gmac_ops rk3128_ops = {
#define RK3228_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
/* RK3228_GRF_MAC_CON1 */
-#define RK3228_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val)
#define RK3228_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
#define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2)
@@ -366,8 +390,6 @@ static const struct rk_gmac_ops rk3128_ops = {
#define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7)
#define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
#define RK3228_GMAC_CLK(val) GRF_FIELD_CONST(9, 8, val)
-#define RK3228_GMAC_RMII_MODE GRF_BIT(10)
-#define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10)
#define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
#define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
#define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
@@ -380,8 +402,6 @@ static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
- RK3228_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
- RK3228_GMAC_RMII_MODE_CLR |
DELAY_ENABLE(RK3228, tx_delay, rx_delay));
regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
@@ -391,10 +411,6 @@ static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
{
- regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
- RK3228_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
- RK3228_GMAC_RMII_MODE);
-
/* set MAC to RMII mode */
regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
}
@@ -428,13 +444,17 @@ static const struct rk_gmac_ops rk3228_ops = {
.set_speed = rk3228_set_speed,
.integrated_phy_powerup = rk3228_integrated_phy_powerup,
.integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,
+
+ .gmac_grf_reg = RK3228_GRF_MAC_CON1,
+ .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
+ .gmac_rmii_mode_mask = BIT_U16(10),
+
};
#define RK3288_GRF_SOC_CON1 0x0248
#define RK3288_GRF_SOC_CON3 0x0250
/*RK3288_GRF_SOC_CON1*/
-#define RK3288_GMAC_PHY_INTF_SEL(val) GRF_FIELD(8, 6, val)
#define RK3288_GMAC_FLOW_CTRL GRF_BIT(9)
#define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
#define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10)
@@ -442,8 +462,6 @@ static const struct rk_gmac_ops rk3228_ops = {
#define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11)
#define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
#define RK3288_GMAC_CLK(val) GRF_FIELD_CONST(13, 12, val)
-#define RK3288_GMAC_RMII_MODE GRF_BIT(14)
-#define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
/*RK3288_GRF_SOC_CON3*/
#define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
@@ -456,9 +474,6 @@ static const struct rk_gmac_ops rk3228_ops = {
static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
- regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
- RK3288_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
- RK3288_GMAC_RMII_MODE_CLR);
regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
@@ -467,9 +482,6 @@ static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
{
- regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
- RK3288_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
- RK3288_GMAC_RMII_MODE);
}
static const struct rk_reg_speed_data rk3288_reg_speed_data = {
@@ -491,12 +503,15 @@ static const struct rk_gmac_ops rk3288_ops = {
.set_to_rgmii = rk3288_set_to_rgmii,
.set_to_rmii = rk3288_set_to_rmii,
.set_speed = rk3288_set_speed,
+
+ .gmac_grf_reg = RK3288_GRF_SOC_CON1,
+ .gmac_phy_intf_sel_mask = GENMASK_U16(8, 6),
+ .gmac_rmii_mode_mask = BIT_U16(14),
};
#define RK3308_GRF_MAC_CON0 0x04a0
/* RK3308_GRF_MAC_CON0 */
-#define RK3308_GMAC_PHY_INTF_SEL(val) GRF_FIELD(4, 2, val)
#define RK3308_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
#define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0)
@@ -504,8 +519,6 @@ static const struct rk_gmac_ops rk3288_ops = {
static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
{
- regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
- RK3308_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII));
}
static const struct rk_reg_speed_data rk3308_reg_speed_data = {
@@ -523,6 +536,9 @@ static int rk3308_set_speed(struct rk_priv_data *bsp_priv,
static const struct rk_gmac_ops rk3308_ops = {
.set_to_rmii = rk3308_set_to_rmii,
.set_speed = rk3308_set_speed,
+
+ .gmac_grf_reg = RK3308_GRF_MAC_CON0,
+ .gmac_phy_intf_sel_mask = GENMASK_U16(4, 2),
};
#define RK3328_GRF_MAC_CON0 0x0900
@@ -535,7 +551,6 @@ static const struct rk_gmac_ops rk3308_ops = {
#define RK3328_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
/* RK3328_GRF_MAC_CON1 */
-#define RK3328_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val)
#define RK3328_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
#define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2)
@@ -543,20 +558,32 @@ static const struct rk_gmac_ops rk3308_ops = {
#define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7)
#define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
#define RK3328_GMAC_CLK(val) GRF_FIELD_CONST(12, 11, val)
-#define RK3328_GMAC_RMII_MODE GRF_BIT(9)
-#define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9)
#define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
#define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
/* RK3328_GRF_MACPHY_CON1 */
#define RK3328_MACPHY_RMII_MODE GRF_BIT(9)
+static int rk3328_init(struct rk_priv_data *bsp_priv)
+{
+ switch (bsp_priv->id) {
+ case 0: /* gmac2io */
+ bsp_priv->gmac_grf_reg = RK3328_GRF_MAC_CON1;
+ return 0;
+
+ case 1: /* gmac2phy */
+ bsp_priv->gmac_grf_reg = RK3328_GRF_MAC_CON2;
+ return 0;
+
+ default:
+ return -EINVAL;
+ }
+}
+
static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
- RK3328_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
- RK3328_GMAC_RMII_MODE_CLR |
RK3328_GMAC_RXCLK_DLY_ENABLE |
RK3328_GMAC_TXCLK_DLY_ENABLE);
@@ -567,13 +594,6 @@ static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
{
- unsigned int reg;
-
- reg = bsp_priv->id ? RK3328_GRF_MAC_CON2 : RK3328_GRF_MAC_CON1;
-
- regmap_write(bsp_priv->grf, reg,
- RK3328_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
- RK3328_GMAC_RMII_MODE);
}
static const struct rk_reg_speed_data rk3328_reg_speed_data = {
@@ -604,12 +624,16 @@ static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
}
static const struct rk_gmac_ops rk3328_ops = {
+ .init = rk3328_init,
.set_to_rgmii = rk3328_set_to_rgmii,
.set_to_rmii = rk3328_set_to_rmii,
.set_speed = rk3328_set_speed,
.integrated_phy_powerup = rk3328_integrated_phy_powerup,
.integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,
+ .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
+ .gmac_rmii_mode_mask = BIT_U16(9),
+
.regs_valid = true,
.regs = {
0xff540000, /* gmac2io */
@@ -622,7 +646,6 @@ static const struct rk_gmac_ops rk3328_ops = {
#define RK3366_GRF_SOC_CON7 0x041c
/* RK3366_GRF_SOC_CON6 */
-#define RK3366_GMAC_PHY_INTF_SEL(val) GRF_FIELD(11, 9, val)
#define RK3366_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
#define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7)
@@ -630,8 +653,6 @@ static const struct rk_gmac_ops rk3328_ops = {
#define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3)
#define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
#define RK3366_GMAC_CLK(val) GRF_FIELD_CONST(5, 4, val)
-#define RK3366_GMAC_RMII_MODE GRF_BIT(6)
-#define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
/* RK3366_GRF_SOC_CON7 */
#define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
@@ -644,9 +665,6 @@ static const struct rk_gmac_ops rk3328_ops = {
static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
- regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
- RK3366_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
- RK3366_GMAC_RMII_MODE_CLR);
regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
@@ -655,9 +673,6 @@ static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
{
- regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
- RK3366_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
- RK3366_GMAC_RMII_MODE);
}
static const struct rk_reg_speed_data rk3366_reg_speed_data = {
@@ -679,13 +694,16 @@ static const struct rk_gmac_ops rk3366_ops = {
.set_to_rgmii = rk3366_set_to_rgmii,
.set_to_rmii = rk3366_set_to_rmii,
.set_speed = rk3366_set_speed,
+
+ .gmac_grf_reg = RK3366_GRF_SOC_CON6,
+ .gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
+ .gmac_rmii_mode_mask = BIT_U16(6),
};
#define RK3368_GRF_SOC_CON15 0x043c
#define RK3368_GRF_SOC_CON16 0x0440
/* RK3368_GRF_SOC_CON15 */
-#define RK3368_GMAC_PHY_INTF_SEL(val) GRF_FIELD(11, 9, val)
#define RK3368_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
#define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7)
@@ -693,8 +711,6 @@ static const struct rk_gmac_ops rk3366_ops = {
#define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3)
#define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
#define RK3368_GMAC_CLK(val) GRF_FIELD_CONST(5, 4, val)
-#define RK3368_GMAC_RMII_MODE GRF_BIT(6)
-#define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
/* RK3368_GRF_SOC_CON16 */
#define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
@@ -707,9 +723,6 @@ static const struct rk_gmac_ops rk3366_ops = {
static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
- regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
- RK3368_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
- RK3368_GMAC_RMII_MODE_CLR);
regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
@@ -718,9 +731,6 @@ static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
{
- regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
- RK3368_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
- RK3368_GMAC_RMII_MODE);
}
static const struct rk_reg_speed_data rk3368_reg_speed_data = {
@@ -742,13 +752,16 @@ static const struct rk_gmac_ops rk3368_ops = {
.set_to_rgmii = rk3368_set_to_rgmii,
.set_to_rmii = rk3368_set_to_rmii,
.set_speed = rk3368_set_speed,
+
+ .gmac_grf_reg = RK3368_GRF_SOC_CON15,
+ .gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
+ .gmac_rmii_mode_mask = BIT_U16(6),
};
#define RK3399_GRF_SOC_CON5 0xc214
#define RK3399_GRF_SOC_CON6 0xc218
/* RK3399_GRF_SOC_CON5 */
-#define RK3399_GMAC_PHY_INTF_SEL(val) GRF_FIELD(11, 9, val)
#define RK3399_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
#define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7)
@@ -756,8 +769,6 @@ static const struct rk_gmac_ops rk3368_ops = {
#define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3)
#define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
#define RK3399_GMAC_CLK(val) GRF_FIELD_CONST(5, 4, val)
-#define RK3399_GMAC_RMII_MODE GRF_BIT(6)
-#define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
/* RK3399_GRF_SOC_CON6 */
#define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
@@ -770,9 +781,6 @@ static const struct rk_gmac_ops rk3368_ops = {
static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
- regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
- RK3399_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
- RK3399_GMAC_RMII_MODE_CLR);
regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
@@ -781,9 +789,6 @@ static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
{
- regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
- RK3399_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
- RK3399_GMAC_RMII_MODE);
}
static const struct rk_reg_speed_data rk3399_reg_speed_data = {
@@ -805,6 +810,10 @@ static const struct rk_gmac_ops rk3399_ops = {
.set_to_rgmii = rk3399_set_to_rgmii,
.set_to_rmii = rk3399_set_to_rmii,
.set_speed = rk3399_set_speed,
+
+ .gmac_grf_reg = RK3399_GRF_SOC_CON5,
+ .gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
+ .gmac_rmii_mode_mask = BIT_U16(6),
};
#define RK3506_GRF_SOC_CON8 0x0020
@@ -1007,7 +1016,6 @@ static const struct rk_gmac_ops rk3528_ops = {
#define RK3568_GRF_GMAC1_CON1 0x038c
/* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
-#define RK3568_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val)
#define RK3568_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
#define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
@@ -1019,6 +1027,22 @@ static const struct rk_gmac_ops rk3528_ops = {
#define RK3568_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val)
#define RK3568_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
+static int rk3568_init(struct rk_priv_data *bsp_priv)
+{
+ switch (bsp_priv->id) {
+ case 0:
+ bsp_priv->gmac_grf_reg = RK3568_GRF_GMAC0_CON1;
+ return 0;
+
+ case 1:
+ bsp_priv->gmac_grf_reg = RK3568_GRF_GMAC1_CON1;
+ return 0;
+
+ default:
+ return -EINVAL;
+ }
+}
+
static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
@@ -1034,25 +1058,22 @@ static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
regmap_write(bsp_priv->grf, con1,
- RK3568_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
RK3568_GMAC_RXCLK_DLY_ENABLE |
RK3568_GMAC_TXCLK_DLY_ENABLE);
}
static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)
{
- u32 con1;
-
- con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
- RK3568_GRF_GMAC0_CON1;
- regmap_write(bsp_priv->grf, con1,
- RK3568_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII));
}
static const struct rk_gmac_ops rk3568_ops = {
+ .init = rk3568_init,
.set_to_rgmii = rk3568_set_to_rgmii,
.set_to_rmii = rk3568_set_to_rmii,
.set_speed = rk_set_clk_mac_speed,
+
+ .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
+
.regs_valid = true,
.regs = {
0xfe2a0000, /* gmac0 */
@@ -1079,9 +1100,6 @@ static const struct rk_gmac_ops rk3568_ops = {
#define RK3576_GRF_GMAC_CON0 0X0020
#define RK3576_GRF_GMAC_CON1 0X0024
-#define RK3576_GMAC_RMII_MODE GRF_BIT(3)
-#define RK3576_GMAC_RGMII_MODE GRF_CLR_BIT(3)
-
#define RK3576_GMAC_CLK_SELECT_IO GRF_BIT(7)
#define RK3576_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(7)
@@ -1093,16 +1111,27 @@ static const struct rk_gmac_ops rk3568_ops = {
#define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4)
#define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4)
+static int rk3576_init(struct rk_priv_data *bsp_priv)
+{
+ switch (bsp_priv->id) {
+ case 0:
+ bsp_priv->gmac_grf_reg = RK3576_GRF_GMAC_CON0;
+ return 0;
+
+ case 1:
+ bsp_priv->gmac_grf_reg = RK3576_GRF_GMAC_CON1;
+ return 0;
+
+ default:
+ return -EINVAL;
+ }
+}
+
static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
unsigned int offset_con;
- offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
- RK3576_GRF_GMAC_CON0;
-
- regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RGMII_MODE);
-
offset_con = bsp_priv->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 :
RK3576_VCCIO0_1_3_IOC_CON2;
@@ -1123,12 +1152,6 @@ static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv,
static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv)
{
- unsigned int offset_con;
-
- offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
- RK3576_GRF_GMAC_CON0;
-
- regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RMII_MODE);
}
static const struct rk_reg_speed_data rk3578_reg_speed_data = {
@@ -1168,10 +1191,14 @@ static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input
}
static const struct rk_gmac_ops rk3576_ops = {
+ .init = rk3576_init,
.set_to_rgmii = rk3576_set_to_rgmii,
.set_to_rmii = rk3576_set_to_rmii,
.set_speed = rk3576_set_gmac_speed,
.set_clock_selection = rk3576_set_clock_selection,
+
+ .gmac_rmii_mode_mask = BIT_U16(3),
+
.php_grf_required = true,
.regs_valid = true,
.regs = {
@@ -1198,9 +1225,6 @@ static const struct rk_gmac_ops rk3576_ops = {
#define RK3588_GRF_GMAC_CON0 0X0008
#define RK3588_GRF_CLK_CON1 0X0070
-#define RK3588_GMAC_PHY_INTF_SEL(id, val) \
- (GRF_FIELD(5, 3, val) << ((id) * 6))
-
#define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id))
#define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id))
@@ -1216,6 +1240,22 @@ static const struct rk_gmac_ops rk3576_ops = {
#define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1)
#define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1)
+static int rk3588_init(struct rk_priv_data *bsp_priv)
+{
+ switch (bsp_priv->id) {
+ case 0:
+ bsp_priv->gmac_phy_intf_sel_mask = GENMASK_U16(5, 3);
+ return 0;
+
+ case 1:
+ bsp_priv->gmac_phy_intf_sel_mask = GENMASK_U16(11, 9);
+ return 0;
+
+ default:
+ return -EINVAL;
+ }
+}
+
static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
@@ -1224,9 +1264,6 @@ static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 :
RK3588_GRF_GMAC_CON8;
- regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
- RK3588_GMAC_PHY_INTF_SEL(id, PHY_INTF_SEL_RGMII));
-
regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
RK3588_GMAC_CLK_RGMII_MODE(id));
@@ -1241,9 +1278,6 @@ static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
{
- regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
- RK3588_GMAC_PHY_INTF_SEL(bsp_priv->id, PHY_INTF_SEL_RMII));
-
regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id));
}
@@ -1296,10 +1330,14 @@ static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input
}
static const struct rk_gmac_ops rk3588_ops = {
+ .init = rk3588_init,
.set_to_rgmii = rk3588_set_to_rgmii,
.set_to_rmii = rk3588_set_to_rmii,
.set_speed = rk3588_set_gmac_speed,
.set_clock_selection = rk3588_set_clock_selection,
+
+ .gmac_grf_reg = RK3588_GRF_GMAC_CON0,
+
.php_grf_required = true,
.regs_valid = true,
.regs = {
@@ -1312,7 +1350,6 @@ static const struct rk_gmac_ops rk3588_ops = {
#define RV1108_GRF_GMAC_CON0 0X0900
/* RV1108_GRF_GMAC_CON0 */
-#define RV1108_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val)
#define RV1108_GMAC_FLOW_CTRL GRF_BIT(3)
#define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
#define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2)
@@ -1322,8 +1359,6 @@ static const struct rk_gmac_ops rk3588_ops = {
static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
{
- regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
- RV1108_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII));
}
static const struct rk_reg_speed_data rv1108_reg_speed_data = {
@@ -1341,6 +1376,9 @@ static int rv1108_set_speed(struct rk_priv_data *bsp_priv,
static const struct rk_gmac_ops rv1108_ops = {
.set_to_rmii = rv1108_set_to_rmii,
.set_speed = rv1108_set_speed,
+
+ .gmac_grf_reg = RV1108_GRF_GMAC_CON0,
+ .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
};
#define RV1126_GRF_GMAC_CON0 0X0070
@@ -1348,7 +1386,6 @@ static const struct rk_gmac_ops rv1108_ops = {
#define RV1126_GRF_GMAC_CON2 0X0078
/* RV1126_GRF_GMAC_CON0 */
-#define RV1126_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val)
#define RV1126_GMAC_FLOW_CTRL GRF_BIT(7)
#define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7)
#define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1)
@@ -1371,7 +1408,6 @@ static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
- RV1126_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
RV1126_GMAC_M0_RXCLK_DLY_ENABLE |
RV1126_GMAC_M0_TXCLK_DLY_ENABLE |
RV1126_GMAC_M1_RXCLK_DLY_ENABLE |
@@ -1388,14 +1424,15 @@ static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv)
{
- regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
- RV1126_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII));
}
static const struct rk_gmac_ops rv1126_ops = {
.set_to_rgmii = rv1126_set_to_rgmii,
.set_to_rmii = rv1126_set_to_rmii,
.set_speed = rk_set_clk_mac_speed,
+
+ .gmac_grf_reg = RV1126_GRF_GMAC_CON0,
+ .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
};
static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
@@ -1619,6 +1656,11 @@ static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
bsp_priv->dev = dev;
+ /* Set the default phy_intf_sel and RMII mode register parameters. */
+ bsp_priv->gmac_grf_reg = ops->gmac_grf_reg;
+ bsp_priv->gmac_phy_intf_sel_mask = ops->gmac_phy_intf_sel_mask;
+ bsp_priv->gmac_rmii_mode_mask = ops->gmac_rmii_mode_mask;
+
if (ops->init) {
ret = ops->init(bsp_priv);
if (ret) {
@@ -1654,6 +1696,7 @@ static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv)
static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
{
struct device *dev = bsp_priv->dev;
+ u32 val;
int ret;
ret = rk_gmac_check_ops(bsp_priv);
@@ -1664,6 +1707,24 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
if (ret)
return ret;
+ ret = rk_get_phy_intf_sel(bsp_priv->phy_iface);
+ if (ret < 0)
+ return ret;
+
+ if (bsp_priv->gmac_phy_intf_sel_mask ||
+ bsp_priv->gmac_rmii_mode_mask) {
+ /* If defined, encode the phy_intf_sel value */
+ val = rk_encode_wm16(ret, bsp_priv->gmac_phy_intf_sel_mask);
+
+ /* If defined, encode the RMII mode mask setting. */
+ val |= rk_encode_wm16(ret == PHY_INTF_SEL_RMII,
+ bsp_priv->gmac_rmii_mode_mask);
+
+ ret = regmap_write(bsp_priv->grf, bsp_priv->gmac_grf_reg, val);
+ if (ret < 0)
+ return ret;
+ }
+
/*rmii or rgmii*/
switch (bsp_priv->phy_iface) {
case PHY_INTERFACE_MODE_RGMII:
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH net-next 08/21] net: stmmac: rk: move speed GRF register offset to private data
2026-01-23 10:59 [PATCH net-next 00/21] net: stmmac: rk: simplify per-SoC configuration Russell King (Oracle)
` (6 preceding siblings ...)
2026-01-23 11:00 ` [PATCH net-next 07/21] net: stmmac: rk: convert to mask-based interface mode configuration Russell King (Oracle)
@ 2026-01-23 11:00 ` Russell King (Oracle)
2026-01-23 11:01 ` [PATCH net-next 09/21] net: stmmac: rk: convert rk3588 to rk_set_reg_speed() Russell King (Oracle)
` (12 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Russell King (Oracle) @ 2026-01-23 11:00 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, netdev, Paolo Abeni
Move the speed/clocking related GRF register offset into the driver
private data, convert rk_set_reg_speed() to use it and initialise this
member either from the corresponding member in struct rk_gmac_ops, or
the SoC specific initialisation function.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 114 +++++++++++++-----
1 file changed, 81 insertions(+), 33 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 48fc5b58092f..246a7b9205a5 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -50,6 +50,8 @@ struct rk_gmac_ops {
u16 gmac_phy_intf_sel_mask;
u16 gmac_rmii_mode_mask;
+ u16 clock_grf_reg;
+
bool php_grf_required;
bool regs_valid;
u32 regs[];
@@ -99,6 +101,8 @@ struct rk_priv_data {
u16 gmac_grf_reg;
u16 gmac_phy_intf_sel_mask;
u16 gmac_rmii_mode_mask;
+
+ u16 clock_grf_reg;
};
#define GMAC_CLK_DIV1_125M 0
@@ -126,10 +130,14 @@ static u32 rk_encode_wm16(u16 val, u16 mask)
return reg_val;
}
+static int rk_write_clock_grf_reg(struct rk_priv_data *bsp_priv, u32 val)
+{
+ return regmap_write(bsp_priv->grf, bsp_priv->clock_grf_reg, val);
+}
+
static int rk_set_reg_speed(struct rk_priv_data *bsp_priv,
const struct rk_reg_speed_data *rsd,
- unsigned int reg, phy_interface_t interface,
- int speed)
+ phy_interface_t interface, int speed)
{
unsigned int val;
@@ -165,7 +173,7 @@ static int rk_set_reg_speed(struct rk_priv_data *bsp_priv,
return -EINVAL;
}
- regmap_write(bsp_priv->grf, reg, val);
+ rk_write_clock_grf_reg(bsp_priv, val);
return 0;
@@ -360,7 +368,7 @@ static int rk3128_set_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
return rk_set_reg_speed(bsp_priv, &rk3128_reg_speed_data,
- RK3128_GRF_MAC_CON1, interface, speed);
+ interface, speed);
}
static const struct rk_gmac_ops rk3128_ops = {
@@ -371,6 +379,8 @@ static const struct rk_gmac_ops rk3128_ops = {
.gmac_grf_reg = RK3128_GRF_MAC_CON1,
.gmac_phy_intf_sel_mask = GENMASK_U16(8, 6),
.gmac_rmii_mode_mask = BIT_U16(14),
+
+ .clock_grf_reg = RK3128_GRF_MAC_CON1,
};
#define RK3228_GRF_MAC_CON0 0x0900
@@ -427,7 +437,7 @@ static int rk3228_set_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
return rk_set_reg_speed(bsp_priv, &rk3228_reg_speed_data,
- RK3228_GRF_MAC_CON1, interface, speed);
+ interface, speed);
}
static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
@@ -449,6 +459,7 @@ static const struct rk_gmac_ops rk3228_ops = {
.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
.gmac_rmii_mode_mask = BIT_U16(10),
+ .clock_grf_reg = RK3228_GRF_MAC_CON1,
};
#define RK3288_GRF_SOC_CON1 0x0248
@@ -496,7 +507,7 @@ static int rk3288_set_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
return rk_set_reg_speed(bsp_priv, &rk3288_reg_speed_data,
- RK3288_GRF_SOC_CON1, interface, speed);
+ interface, speed);
}
static const struct rk_gmac_ops rk3288_ops = {
@@ -507,6 +518,8 @@ static const struct rk_gmac_ops rk3288_ops = {
.gmac_grf_reg = RK3288_GRF_SOC_CON1,
.gmac_phy_intf_sel_mask = GENMASK_U16(8, 6),
.gmac_rmii_mode_mask = BIT_U16(14),
+
+ .clock_grf_reg = RK3288_GRF_SOC_CON1,
};
#define RK3308_GRF_MAC_CON0 0x04a0
@@ -530,7 +543,7 @@ static int rk3308_set_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
return rk_set_reg_speed(bsp_priv, &rk3308_reg_speed_data,
- RK3308_GRF_MAC_CON0, interface, speed);
+ interface, speed);
}
static const struct rk_gmac_ops rk3308_ops = {
@@ -539,6 +552,8 @@ static const struct rk_gmac_ops rk3308_ops = {
.gmac_grf_reg = RK3308_GRF_MAC_CON0,
.gmac_phy_intf_sel_mask = GENMASK_U16(4, 2),
+
+ .clock_grf_reg = RK3308_GRF_MAC_CON0,
};
#define RK3328_GRF_MAC_CON0 0x0900
@@ -569,10 +584,12 @@ static int rk3328_init(struct rk_priv_data *bsp_priv)
switch (bsp_priv->id) {
case 0: /* gmac2io */
bsp_priv->gmac_grf_reg = RK3328_GRF_MAC_CON1;
+ bsp_priv->clock_grf_reg = RK3328_GRF_MAC_CON1;
return 0;
case 1: /* gmac2phy */
bsp_priv->gmac_grf_reg = RK3328_GRF_MAC_CON2;
+ bsp_priv->clock_grf_reg = RK3328_GRF_MAC_CON2;
return 0;
default:
@@ -607,11 +624,7 @@ static const struct rk_reg_speed_data rk3328_reg_speed_data = {
static int rk3328_set_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
- unsigned int reg;
-
- reg = bsp_priv->id ? RK3328_GRF_MAC_CON2 : RK3328_GRF_MAC_CON1;
-
- return rk_set_reg_speed(bsp_priv, &rk3328_reg_speed_data, reg,
+ return rk_set_reg_speed(bsp_priv, &rk3328_reg_speed_data,
interface, speed);
}
@@ -687,7 +700,7 @@ static int rk3366_set_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
return rk_set_reg_speed(bsp_priv, &rk3366_reg_speed_data,
- RK3366_GRF_SOC_CON6, interface, speed);
+ interface, speed);
}
static const struct rk_gmac_ops rk3366_ops = {
@@ -698,6 +711,8 @@ static const struct rk_gmac_ops rk3366_ops = {
.gmac_grf_reg = RK3366_GRF_SOC_CON6,
.gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
.gmac_rmii_mode_mask = BIT_U16(6),
+
+ .clock_grf_reg = RK3366_GRF_SOC_CON6,
};
#define RK3368_GRF_SOC_CON15 0x043c
@@ -745,7 +760,7 @@ static int rk3368_set_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
return rk_set_reg_speed(bsp_priv, &rk3368_reg_speed_data,
- RK3368_GRF_SOC_CON15, interface, speed);
+ interface, speed);
}
static const struct rk_gmac_ops rk3368_ops = {
@@ -756,6 +771,8 @@ static const struct rk_gmac_ops rk3368_ops = {
.gmac_grf_reg = RK3368_GRF_SOC_CON15,
.gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
.gmac_rmii_mode_mask = BIT_U16(6),
+
+ .clock_grf_reg = RK3368_GRF_SOC_CON15,
};
#define RK3399_GRF_SOC_CON5 0xc214
@@ -803,7 +820,7 @@ static int rk3399_set_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
return rk_set_reg_speed(bsp_priv, &rk3399_reg_speed_data,
- RK3399_GRF_SOC_CON5, interface, speed);
+ interface, speed);
}
static const struct rk_gmac_ops rk3399_ops = {
@@ -814,6 +831,8 @@ static const struct rk_gmac_ops rk3399_ops = {
.gmac_grf_reg = RK3399_GRF_SOC_CON5,
.gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
.gmac_rmii_mode_mask = BIT_U16(6),
+
+ .clock_grf_reg = RK3399_GRF_SOC_CON5,
};
#define RK3506_GRF_SOC_CON8 0x0020
@@ -830,6 +849,22 @@ static const struct rk_gmac_ops rk3399_ops = {
#define RK3506_GMAC_CLK_RMII_GATE GRF_BIT(2)
#define RK3506_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(2)
+static int rk3506_init(struct rk_priv_data *bsp_priv)
+{
+ switch (bsp_priv->id) {
+ case 0:
+ bsp_priv->clock_grf_reg = RK3506_GRF_SOC_CON8;
+ return 0;
+
+ case 1:
+ bsp_priv->clock_grf_reg = RK3506_GRF_SOC_CON11;
+ return 0;
+
+ default:
+ return -EINVAL;
+ }
+}
+
static void rk3506_set_to_rmii(struct rk_priv_data *bsp_priv)
{
unsigned int id = bsp_priv->id, offset;
@@ -846,11 +881,8 @@ static const struct rk_reg_speed_data rk3506_reg_speed_data = {
static int rk3506_set_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
- unsigned int id = bsp_priv->id, offset;
-
- offset = (id == 1) ? RK3506_GRF_SOC_CON11 : RK3506_GRF_SOC_CON8;
return rk_set_reg_speed(bsp_priv, &rk3506_reg_speed_data,
- offset, interface, speed);
+ interface, speed);
}
static void rk3506_set_clock_selection(struct rk_priv_data *bsp_priv,
@@ -868,6 +900,7 @@ static void rk3506_set_clock_selection(struct rk_priv_data *bsp_priv,
}
static const struct rk_gmac_ops rk3506_ops = {
+ .init = rk3506_init,
.set_to_rmii = rk3506_set_to_rmii,
.set_speed = rk3506_set_speed,
.set_clock_selection = rk3506_set_clock_selection,
@@ -912,6 +945,22 @@ static const struct rk_gmac_ops rk3506_ops = {
#define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9)
#define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9)
+static int rk3528_init(struct rk_priv_data *bsp_priv)
+{
+ switch (bsp_priv->id) {
+ case 0:
+ bsp_priv->clock_grf_reg = RK3528_VO_GRF_GMAC_CON;
+ return 0;
+
+ case 1:
+ bsp_priv->clock_grf_reg = RK3528_VPU_GRF_GMAC_CON5;
+ return 0;
+
+ default:
+ return -EINVAL;
+ }
+}
+
static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
@@ -954,17 +1003,13 @@ static int rk3528_set_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
const struct rk_reg_speed_data *rsd;
- unsigned int reg;
- if (bsp_priv->id == 1) {
+ if (bsp_priv->id == 1)
rsd = &rk3528_gmac1_reg_speed_data;
- reg = RK3528_VPU_GRF_GMAC_CON5;
- } else {
+ else
rsd = &rk3528_gmac0_reg_speed_data;
- reg = RK3528_VO_GRF_GMAC_CON;
- }
- return rk_set_reg_speed(bsp_priv, rsd, reg, interface, speed);
+ return rk_set_reg_speed(bsp_priv, rsd, interface, speed);
}
static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv,
@@ -996,6 +1041,7 @@ static void rk3528_integrated_phy_powerdown(struct rk_priv_data *bsp_priv)
}
static const struct rk_gmac_ops rk3528_ops = {
+ .init = rk3528_init,
.set_to_rgmii = rk3528_set_to_rgmii,
.set_to_rmii = rk3528_set_to_rmii,
.set_speed = rk3528_set_speed,
@@ -1116,10 +1162,12 @@ static int rk3576_init(struct rk_priv_data *bsp_priv)
switch (bsp_priv->id) {
case 0:
bsp_priv->gmac_grf_reg = RK3576_GRF_GMAC_CON0;
+ bsp_priv->clock_grf_reg = RK3576_GRF_GMAC_CON0;
return 0;
case 1:
bsp_priv->gmac_grf_reg = RK3576_GRF_GMAC_CON1;
+ bsp_priv->clock_grf_reg = RK3576_GRF_GMAC_CON1;
return 0;
default:
@@ -1165,12 +1213,7 @@ static const struct rk_reg_speed_data rk3578_reg_speed_data = {
static int rk3576_set_gmac_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
- unsigned int offset_con;
-
- offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
- RK3576_GRF_GMAC_CON0;
-
- return rk_set_reg_speed(bsp_priv, &rk3578_reg_speed_data, offset_con,
+ return rk_set_reg_speed(bsp_priv, &rk3578_reg_speed_data,
interface, speed);
}
@@ -1370,7 +1413,7 @@ static int rv1108_set_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
return rk_set_reg_speed(bsp_priv, &rv1108_reg_speed_data,
- RV1108_GRF_GMAC_CON0, interface, speed);
+ interface, speed);
}
static const struct rk_gmac_ops rv1108_ops = {
@@ -1379,6 +1422,8 @@ static const struct rk_gmac_ops rv1108_ops = {
.gmac_grf_reg = RV1108_GRF_GMAC_CON0,
.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
+
+ .clock_grf_reg = RV1108_GRF_GMAC_CON0,
};
#define RV1126_GRF_GMAC_CON0 0X0070
@@ -1661,6 +1706,9 @@ static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
bsp_priv->gmac_phy_intf_sel_mask = ops->gmac_phy_intf_sel_mask;
bsp_priv->gmac_rmii_mode_mask = ops->gmac_rmii_mode_mask;
+ /* Set the default clock control register related parameters */
+ bsp_priv->clock_grf_reg = ops->clock_grf_reg;
+
if (ops->init) {
ret = ops->init(bsp_priv);
if (ret) {
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH net-next 09/21] net: stmmac: rk: convert rk3588 to rk_set_reg_speed()
2026-01-23 10:59 [PATCH net-next 00/21] net: stmmac: rk: simplify per-SoC configuration Russell King (Oracle)
` (7 preceding siblings ...)
2026-01-23 11:00 ` [PATCH net-next 08/21] net: stmmac: rk: move speed GRF register offset to private data Russell King (Oracle)
@ 2026-01-23 11:01 ` Russell King (Oracle)
2026-01-23 11:01 ` [PATCH net-next 10/21] net: stmmac: rk: remove rk3528 RMII clock initialisation Russell King (Oracle)
` (11 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Russell King (Oracle) @ 2026-01-23 11:01 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, netdev, Paolo Abeni
Update rk_set_reg_speed() to use either the grf or php_grf regmap
depending on the SoC's requirements and convert rk3588, removing
its custom code.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 63 ++++++++++---------
1 file changed, 34 insertions(+), 29 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 246a7b9205a5..4f32e4b3769c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -52,6 +52,7 @@ struct rk_gmac_ops {
u16 clock_grf_reg;
+ bool clock_grf_reg_in_php;
bool php_grf_required;
bool regs_valid;
u32 regs[];
@@ -132,7 +133,14 @@ static u32 rk_encode_wm16(u16 val, u16 mask)
static int rk_write_clock_grf_reg(struct rk_priv_data *bsp_priv, u32 val)
{
- return regmap_write(bsp_priv->grf, bsp_priv->clock_grf_reg, val);
+ struct regmap *regmap;
+
+ if (bsp_priv->ops->clock_grf_reg_in_php)
+ regmap = bsp_priv->php_grf;
+ else
+ regmap = bsp_priv->grf;
+
+ return regmap_write(regmap, bsp_priv->clock_grf_reg, val);
}
static int rk_set_reg_speed(struct rk_priv_data *bsp_priv,
@@ -1325,39 +1333,33 @@ static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id));
}
+static const struct rk_reg_speed_data rk3588_gmac0_speed_data = {
+ .rgmii_10 = RK3588_GMAC_CLK_RGMII(0, GMAC_CLK_DIV50_2_5M),
+ .rgmii_100 = RK3588_GMAC_CLK_RGMII(0, GMAC_CLK_DIV5_25M),
+ .rgmii_1000 = RK3588_GMAC_CLK_RGMII(0, GMAC_CLK_DIV1_125M),
+ .rmii_10 = RK3588_GMA_CLK_RMII_DIV20(0),
+ .rmii_100 = RK3588_GMA_CLK_RMII_DIV2(0),
+};
+
+static const struct rk_reg_speed_data rk3588_gmac1_speed_data = {
+ .rgmii_10 = RK3588_GMAC_CLK_RGMII(1, GMAC_CLK_DIV50_2_5M),
+ .rgmii_100 = RK3588_GMAC_CLK_RGMII(1, GMAC_CLK_DIV5_25M),
+ .rgmii_1000 = RK3588_GMAC_CLK_RGMII(1, GMAC_CLK_DIV1_125M),
+ .rmii_10 = RK3588_GMA_CLK_RMII_DIV20(1),
+ .rmii_100 = RK3588_GMA_CLK_RMII_DIV2(1),
+};
+
static int rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
- unsigned int val = 0, id = bsp_priv->id;
-
- switch (speed) {
- case 10:
- if (interface == PHY_INTERFACE_MODE_RMII)
- val = RK3588_GMA_CLK_RMII_DIV20(id);
- else
- val = RK3588_GMAC_CLK_RGMII(id, GMAC_CLK_DIV50_2_5M);
- break;
- case 100:
- if (interface == PHY_INTERFACE_MODE_RMII)
- val = RK3588_GMA_CLK_RMII_DIV2(id);
- else
- val = RK3588_GMAC_CLK_RGMII(id, GMAC_CLK_DIV5_25M);
- break;
- case 1000:
- if (interface != PHY_INTERFACE_MODE_RMII)
- val = RK3588_GMAC_CLK_RGMII(id, GMAC_CLK_DIV1_125M);
- else
- goto err;
- break;
- default:
- goto err;
- }
+ const struct rk_reg_speed_data *rsd;
- regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);
+ if (bsp_priv->id == 0)
+ rsd = &rk3588_gmac0_speed_data;
+ else
+ rsd = &rk3588_gmac1_speed_data;
- return 0;
-err:
- return -EINVAL;
+ return rk_set_reg_speed(bsp_priv, rsd, interface, speed);
}
static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
@@ -1381,6 +1383,9 @@ static const struct rk_gmac_ops rk3588_ops = {
.gmac_grf_reg = RK3588_GRF_GMAC_CON0,
+ .clock_grf_reg_in_php = true,
+ .clock_grf_reg = RK3588_GRF_CLK_CON1,
+
.php_grf_required = true,
.regs_valid = true,
.regs = {
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH net-next 10/21] net: stmmac: rk: remove rk3528 RMII clock initialisation
2026-01-23 10:59 [PATCH net-next 00/21] net: stmmac: rk: simplify per-SoC configuration Russell King (Oracle)
` (8 preceding siblings ...)
2026-01-23 11:01 ` [PATCH net-next 09/21] net: stmmac: rk: convert rk3588 to rk_set_reg_speed() Russell King (Oracle)
@ 2026-01-23 11:01 ` Russell King (Oracle)
2026-01-23 11:01 ` [PATCH net-next 11/21] net: stmmac: rk: use rk_encode_wm16() for RGMII clocks Russell King (Oracle)
` (10 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Russell King (Oracle) @ 2026-01-23 11:01 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, netdev, Paolo Abeni
There is no need to pre-initialise the rk3528 RMII clock when
selecting RMII mode on gmac0.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 4f32e4b3769c..f2b7917b6a30 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -990,8 +990,7 @@ static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)
RK3528_GMAC1_PHY_INTF_SEL_RMII);
else
regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON,
- RK3528_GMAC0_PHY_INTF_SEL_RMII |
- RK3528_GMAC0_CLK_RMII_DIV2);
+ RK3528_GMAC0_PHY_INTF_SEL_RMII);
}
static const struct rk_reg_speed_data rk3528_gmac0_reg_speed_data = {
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH net-next 11/21] net: stmmac: rk: use rk_encode_wm16() for RGMII clocks
2026-01-23 10:59 [PATCH net-next 00/21] net: stmmac: rk: simplify per-SoC configuration Russell King (Oracle)
` (9 preceding siblings ...)
2026-01-23 11:01 ` [PATCH net-next 10/21] net: stmmac: rk: remove rk3528 RMII clock initialisation Russell King (Oracle)
@ 2026-01-23 11:01 ` Russell King (Oracle)
2026-01-23 11:01 ` [PATCH net-next 12/21] net: stmmac: rk: use rk_encode_wm16() for RMII speed Russell King (Oracle)
` (9 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Russell King (Oracle) @ 2026-01-23 11:01 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, netdev, Paolo Abeni
As all of the RGMII clock selection bitfields (gmii_clk_sel) use the
same encoding, parameterise this by providing the bitfield mask in
the BSP private data.
This is the last user of GRF_FIELD_CONST(), so remove that definition
as well.
One additional change is for RK3328 - as only gmac2io supports RGMII,
only initialise the mask for this instance.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 100 +++++++-----------
1 file changed, 36 insertions(+), 64 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index f2b7917b6a30..0f94304e721a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -26,10 +26,11 @@
struct rk_priv_data;
+struct rk_clock_fields {
+ u16 gmii_clk_sel_mask;
+};
+
struct rk_reg_speed_data {
- unsigned int rgmii_10;
- unsigned int rgmii_100;
- unsigned int rgmii_1000;
unsigned int rmii_10;
unsigned int rmii_100;
};
@@ -51,6 +52,7 @@ struct rk_gmac_ops {
u16 gmac_rmii_mode_mask;
u16 clock_grf_reg;
+ struct rk_clock_fields clock;
bool clock_grf_reg_in_php;
bool php_grf_required;
@@ -104,12 +106,24 @@ struct rk_priv_data {
u16 gmac_rmii_mode_mask;
u16 clock_grf_reg;
+ struct rk_clock_fields clock;
};
#define GMAC_CLK_DIV1_125M 0
#define GMAC_CLK_DIV50_2_5M 2
#define GMAC_CLK_DIV5_25M 3
+static int rk_gmac_rgmii_clk_div(int speed)
+{
+ if (speed == SPEED_10)
+ return GMAC_CLK_DIV50_2_5M;
+ if (speed == SPEED_100)
+ return GMAC_CLK_DIV5_25M;
+ if (speed == SPEED_1000)
+ return GMAC_CLK_DIV1_125M;
+ return -EINVAL;
+}
+
static int rk_get_phy_intf_sel(phy_interface_t interface)
{
int ret = stmmac_get_phy_intf_sel(interface);
@@ -148,20 +162,14 @@ static int rk_set_reg_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
unsigned int val;
+ int ret;
if (phy_interface_mode_is_rgmii(interface)) {
- if (speed == SPEED_10) {
- val = rsd->rgmii_10;
- } else if (speed == SPEED_100) {
- val = rsd->rgmii_100;
- } else if (speed == SPEED_1000) {
- val = rsd->rgmii_1000;
- } else {
- /* Phylink will not allow inappropriate speeds for
- * interface modes, so this should never happen.
- */
- return -EINVAL;
- }
+ ret = rk_gmac_rgmii_clk_div(speed);
+ if (ret < 0)
+ return ret;
+
+ val = rk_encode_wm16(ret, bsp_priv->clock.gmii_clk_sel_mask);
} else if (interface == PHY_INTERFACE_MODE_RMII) {
if (speed == SPEED_10) {
val = rsd->rmii_10;
@@ -202,8 +210,6 @@ static int rk_set_clk_mac_speed(struct rk_priv_data *bsp_priv,
#define GRF_FIELD(hi, lo, val) \
FIELD_PREP_WM16(GENMASK_U16(hi, lo), val)
-#define GRF_FIELD_CONST(hi, lo, val) \
- FIELD_PREP_WM16_CONST(GENMASK_U16(hi, lo), val)
#define GRF_BIT(nr) (BIT(nr) | BIT(nr+16))
#define GRF_CLR_BIT(nr) (BIT(nr+16))
@@ -349,7 +355,6 @@ static const struct rk_gmac_ops px30_ops = {
#define RK3128_GMAC_SPEED_100M GRF_BIT(10)
#define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11)
#define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
-#define RK3128_GMAC_CLK(val) GRF_FIELD_CONST(13, 12, val)
static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
@@ -365,9 +370,6 @@ static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3128_reg_speed_data = {
- .rgmii_10 = RK3128_GMAC_CLK(GMAC_CLK_DIV50_2_5M),
- .rgmii_100 = RK3128_GMAC_CLK(GMAC_CLK_DIV5_25M),
- .rgmii_1000 = RK3128_GMAC_CLK(GMAC_CLK_DIV1_125M),
.rmii_10 = RK3128_GMAC_RMII_CLK_2_5M | RK3128_GMAC_SPEED_10M,
.rmii_100 = RK3128_GMAC_RMII_CLK_25M | RK3128_GMAC_SPEED_100M,
};
@@ -389,6 +391,7 @@ static const struct rk_gmac_ops rk3128_ops = {
.gmac_rmii_mode_mask = BIT_U16(14),
.clock_grf_reg = RK3128_GRF_MAC_CON1,
+ .clock.gmii_clk_sel_mask = GENMASK_U16(13, 12),
};
#define RK3228_GRF_MAC_CON0 0x0900
@@ -407,7 +410,6 @@ static const struct rk_gmac_ops rk3128_ops = {
#define RK3228_GMAC_SPEED_100M GRF_BIT(2)
#define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7)
#define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
-#define RK3228_GMAC_CLK(val) GRF_FIELD_CONST(9, 8, val)
#define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
#define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
#define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
@@ -434,9 +436,6 @@ static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3228_reg_speed_data = {
- .rgmii_10 = RK3228_GMAC_CLK(GMAC_CLK_DIV50_2_5M),
- .rgmii_100 = RK3228_GMAC_CLK(GMAC_CLK_DIV5_25M),
- .rgmii_1000 = RK3228_GMAC_CLK(GMAC_CLK_DIV1_125M),
.rmii_10 = RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_SPEED_10M,
.rmii_100 = RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_SPEED_100M,
};
@@ -468,6 +467,7 @@ static const struct rk_gmac_ops rk3228_ops = {
.gmac_rmii_mode_mask = BIT_U16(10),
.clock_grf_reg = RK3228_GRF_MAC_CON1,
+ .clock.gmii_clk_sel_mask = GENMASK_U16(9, 8),
};
#define RK3288_GRF_SOC_CON1 0x0248
@@ -480,7 +480,6 @@ static const struct rk_gmac_ops rk3228_ops = {
#define RK3288_GMAC_SPEED_100M GRF_BIT(10)
#define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11)
#define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
-#define RK3288_GMAC_CLK(val) GRF_FIELD_CONST(13, 12, val)
/*RK3288_GRF_SOC_CON3*/
#define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
@@ -504,9 +503,6 @@ static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3288_reg_speed_data = {
- .rgmii_10 = RK3288_GMAC_CLK(GMAC_CLK_DIV50_2_5M),
- .rgmii_100 = RK3288_GMAC_CLK(GMAC_CLK_DIV5_25M),
- .rgmii_1000 = RK3288_GMAC_CLK(GMAC_CLK_DIV1_125M),
.rmii_10 = RK3288_GMAC_RMII_CLK_2_5M | RK3288_GMAC_SPEED_10M,
.rmii_100 = RK3288_GMAC_RMII_CLK_25M | RK3288_GMAC_SPEED_100M,
};
@@ -528,6 +524,7 @@ static const struct rk_gmac_ops rk3288_ops = {
.gmac_rmii_mode_mask = BIT_U16(14),
.clock_grf_reg = RK3288_GRF_SOC_CON1,
+ .clock.gmii_clk_sel_mask = GENMASK_U16(13, 12),
};
#define RK3308_GRF_MAC_CON0 0x04a0
@@ -580,7 +577,6 @@ static const struct rk_gmac_ops rk3308_ops = {
#define RK3328_GMAC_SPEED_100M GRF_BIT(2)
#define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7)
#define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
-#define RK3328_GMAC_CLK(val) GRF_FIELD_CONST(12, 11, val)
#define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
#define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
@@ -593,6 +589,7 @@ static int rk3328_init(struct rk_priv_data *bsp_priv)
case 0: /* gmac2io */
bsp_priv->gmac_grf_reg = RK3328_GRF_MAC_CON1;
bsp_priv->clock_grf_reg = RK3328_GRF_MAC_CON1;
+ bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(12, 11);
return 0;
case 1: /* gmac2phy */
@@ -622,9 +619,6 @@ static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3328_reg_speed_data = {
- .rgmii_10 = RK3328_GMAC_CLK(GMAC_CLK_DIV50_2_5M),
- .rgmii_100 = RK3328_GMAC_CLK(GMAC_CLK_DIV5_25M),
- .rgmii_1000 = RK3328_GMAC_CLK(GMAC_CLK_DIV1_125M),
.rmii_10 = RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_SPEED_10M,
.rmii_100 = RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_SPEED_100M,
};
@@ -673,7 +667,6 @@ static const struct rk_gmac_ops rk3328_ops = {
#define RK3366_GMAC_SPEED_100M GRF_BIT(7)
#define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3)
#define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
-#define RK3366_GMAC_CLK(val) GRF_FIELD_CONST(5, 4, val)
/* RK3366_GRF_SOC_CON7 */
#define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
@@ -697,9 +690,6 @@ static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3366_reg_speed_data = {
- .rgmii_10 = RK3366_GMAC_CLK(GMAC_CLK_DIV50_2_5M),
- .rgmii_100 = RK3366_GMAC_CLK(GMAC_CLK_DIV5_25M),
- .rgmii_1000 = RK3366_GMAC_CLK(GMAC_CLK_DIV1_125M),
.rmii_10 = RK3366_GMAC_RMII_CLK_2_5M | RK3366_GMAC_SPEED_10M,
.rmii_100 = RK3366_GMAC_RMII_CLK_25M | RK3366_GMAC_SPEED_100M,
};
@@ -721,6 +711,7 @@ static const struct rk_gmac_ops rk3366_ops = {
.gmac_rmii_mode_mask = BIT_U16(6),
.clock_grf_reg = RK3366_GRF_SOC_CON6,
+ .clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
};
#define RK3368_GRF_SOC_CON15 0x043c
@@ -733,7 +724,6 @@ static const struct rk_gmac_ops rk3366_ops = {
#define RK3368_GMAC_SPEED_100M GRF_BIT(7)
#define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3)
#define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
-#define RK3368_GMAC_CLK(val) GRF_FIELD_CONST(5, 4, val)
/* RK3368_GRF_SOC_CON16 */
#define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
@@ -757,9 +747,6 @@ static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3368_reg_speed_data = {
- .rgmii_10 = RK3368_GMAC_CLK(GMAC_CLK_DIV50_2_5M),
- .rgmii_100 = RK3368_GMAC_CLK(GMAC_CLK_DIV5_25M),
- .rgmii_1000 = RK3368_GMAC_CLK(GMAC_CLK_DIV1_125M),
.rmii_10 = RK3368_GMAC_RMII_CLK_2_5M | RK3368_GMAC_SPEED_10M,
.rmii_100 = RK3368_GMAC_RMII_CLK_25M | RK3368_GMAC_SPEED_100M,
};
@@ -781,6 +768,7 @@ static const struct rk_gmac_ops rk3368_ops = {
.gmac_rmii_mode_mask = BIT_U16(6),
.clock_grf_reg = RK3368_GRF_SOC_CON15,
+ .clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
};
#define RK3399_GRF_SOC_CON5 0xc214
@@ -793,7 +781,6 @@ static const struct rk_gmac_ops rk3368_ops = {
#define RK3399_GMAC_SPEED_100M GRF_BIT(7)
#define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3)
#define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
-#define RK3399_GMAC_CLK(val) GRF_FIELD_CONST(5, 4, val)
/* RK3399_GRF_SOC_CON6 */
#define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
@@ -817,9 +804,6 @@ static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3399_reg_speed_data = {
- .rgmii_10 = RK3399_GMAC_CLK(GMAC_CLK_DIV50_2_5M),
- .rgmii_100 = RK3399_GMAC_CLK(GMAC_CLK_DIV5_25M),
- .rgmii_1000 = RK3399_GMAC_CLK(GMAC_CLK_DIV1_125M),
.rmii_10 = RK3399_GMAC_RMII_CLK_2_5M | RK3399_GMAC_SPEED_10M,
.rmii_100 = RK3399_GMAC_RMII_CLK_25M | RK3399_GMAC_SPEED_100M,
};
@@ -841,6 +825,7 @@ static const struct rk_gmac_ops rk3399_ops = {
.gmac_rmii_mode_mask = BIT_U16(6),
.clock_grf_reg = RK3399_GRF_SOC_CON5,
+ .clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
};
#define RK3506_GRF_SOC_CON8 0x0020
@@ -946,8 +931,6 @@ static const struct rk_gmac_ops rk3506_ops = {
#define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10)
#define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10)
-#define RK3528_GMAC1_CLK_RGMII(val) GRF_FIELD_CONST(11, 10, val)
-
#define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2)
#define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2)
#define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9)
@@ -962,6 +945,7 @@ static int rk3528_init(struct rk_priv_data *bsp_priv)
case 1:
bsp_priv->clock_grf_reg = RK3528_VPU_GRF_GMAC_CON5;
+ bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(11, 10);
return 0;
default:
@@ -999,9 +983,6 @@ static const struct rk_reg_speed_data rk3528_gmac0_reg_speed_data = {
};
static const struct rk_reg_speed_data rk3528_gmac1_reg_speed_data = {
- .rgmii_10 = RK3528_GMAC1_CLK_RGMII(GMAC_CLK_DIV50_2_5M),
- .rgmii_100 = RK3528_GMAC1_CLK_RGMII(GMAC_CLK_DIV5_25M),
- .rgmii_1000 = RK3528_GMAC1_CLK_RGMII(GMAC_CLK_DIV1_125M),
.rmii_10 = RK3528_GMAC1_CLK_RMII_DIV20,
.rmii_100 = RK3528_GMAC1_CLK_RMII_DIV2,
};
@@ -1159,8 +1140,6 @@ static const struct rk_gmac_ops rk3568_ops = {
#define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5)
#define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5)
-#define RK3576_GMAC_CLK_RGMII(val) GRF_FIELD_CONST(6, 5, val)
-
#define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4)
#define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4)
@@ -1210,9 +1189,6 @@ static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3578_reg_speed_data = {
- .rgmii_10 = RK3576_GMAC_CLK_RGMII(GMAC_CLK_DIV50_2_5M),
- .rgmii_100 = RK3576_GMAC_CLK_RGMII(GMAC_CLK_DIV5_25M),
- .rgmii_1000 = RK3576_GMAC_CLK_RGMII(GMAC_CLK_DIV1_125M),
.rmii_10 = RK3576_GMAC_CLK_RMII_DIV20,
.rmii_100 = RK3576_GMAC_CLK_RMII_DIV2,
};
@@ -1249,6 +1225,8 @@ static const struct rk_gmac_ops rk3576_ops = {
.gmac_rmii_mode_mask = BIT_U16(3),
+ .clock.gmii_clk_sel_mask = GENMASK_U16(6, 5),
+
.php_grf_required = true,
.regs_valid = true,
.regs = {
@@ -1284,9 +1262,6 @@ static const struct rk_gmac_ops rk3576_ops = {
#define RK3588_GMA_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2)
#define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2)
-#define RK3588_GMAC_CLK_RGMII(id, val) \
- (GRF_FIELD_CONST(3, 2, val) << ((id) * 5))
-
#define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1)
#define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1)
@@ -1295,10 +1270,12 @@ static int rk3588_init(struct rk_priv_data *bsp_priv)
switch (bsp_priv->id) {
case 0:
bsp_priv->gmac_phy_intf_sel_mask = GENMASK_U16(5, 3);
+ bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(3, 2);
return 0;
case 1:
bsp_priv->gmac_phy_intf_sel_mask = GENMASK_U16(11, 9);
+ bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(8, 7);
return 0;
default:
@@ -1333,17 +1310,11 @@ static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3588_gmac0_speed_data = {
- .rgmii_10 = RK3588_GMAC_CLK_RGMII(0, GMAC_CLK_DIV50_2_5M),
- .rgmii_100 = RK3588_GMAC_CLK_RGMII(0, GMAC_CLK_DIV5_25M),
- .rgmii_1000 = RK3588_GMAC_CLK_RGMII(0, GMAC_CLK_DIV1_125M),
.rmii_10 = RK3588_GMA_CLK_RMII_DIV20(0),
.rmii_100 = RK3588_GMA_CLK_RMII_DIV2(0),
};
static const struct rk_reg_speed_data rk3588_gmac1_speed_data = {
- .rgmii_10 = RK3588_GMAC_CLK_RGMII(1, GMAC_CLK_DIV50_2_5M),
- .rgmii_100 = RK3588_GMAC_CLK_RGMII(1, GMAC_CLK_DIV5_25M),
- .rgmii_1000 = RK3588_GMAC_CLK_RGMII(1, GMAC_CLK_DIV1_125M),
.rmii_10 = RK3588_GMA_CLK_RMII_DIV20(1),
.rmii_100 = RK3588_GMA_CLK_RMII_DIV2(1),
};
@@ -1712,6 +1683,7 @@ static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
/* Set the default clock control register related parameters */
bsp_priv->clock_grf_reg = ops->clock_grf_reg;
+ bsp_priv->clock = ops->clock;
if (ops->init) {
ret = ops->init(bsp_priv);
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH net-next 12/21] net: stmmac: rk: use rk_encode_wm16() for RMII speed
2026-01-23 10:59 [PATCH net-next 00/21] net: stmmac: rk: simplify per-SoC configuration Russell King (Oracle)
` (10 preceding siblings ...)
2026-01-23 11:01 ` [PATCH net-next 11/21] net: stmmac: rk: use rk_encode_wm16() for RGMII clocks Russell King (Oracle)
@ 2026-01-23 11:01 ` Russell King (Oracle)
2026-01-23 11:01 ` [PATCH net-next 13/21] net: stmmac: rk: use rk_encode_wm16() for RMII clock Russell King (Oracle)
` (8 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Russell King (Oracle) @ 2026-01-23 11:01 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, netdev, Paolo Abeni
The RMII speed configuration is encoded as a single bit, which is set
for 100M and clean for 10M. Provide the bitfield definition in
struct rk_clock_fields, moving it out of struct rk_reg_speed_data's
rmii_10 and rmii_100 initialisers. Update rk_set_reg_speed() to handle
the new definition location of this bit.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 69 +++++++++----------
1 file changed, 31 insertions(+), 38 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 0f94304e721a..48852054390d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -28,6 +28,7 @@ struct rk_priv_data;
struct rk_clock_fields {
u16 gmii_clk_sel_mask;
+ u16 mac_speed_mask;
};
struct rk_reg_speed_data {
@@ -171,10 +172,12 @@ static int rk_set_reg_speed(struct rk_priv_data *bsp_priv,
val = rk_encode_wm16(ret, bsp_priv->clock.gmii_clk_sel_mask);
} else if (interface == PHY_INTERFACE_MODE_RMII) {
+ val = rk_encode_wm16(speed == SPEED_100,
+ bsp_priv->clock.mac_speed_mask);
if (speed == SPEED_10) {
- val = rsd->rmii_10;
+ val |= rsd->rmii_10;
} else if (speed == SPEED_100) {
- val = rsd->rmii_100;
+ val |= rsd->rmii_100;
} else {
/* Phylink will not allow inappropriate speeds for
* interface modes, so this should never happen.
@@ -351,8 +354,6 @@ static const struct rk_gmac_ops px30_ops = {
/* RK3128_GRF_MAC_CON1 */
#define RK3128_GMAC_FLOW_CTRL GRF_BIT(9)
#define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
-#define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10)
-#define RK3128_GMAC_SPEED_100M GRF_BIT(10)
#define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11)
#define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
@@ -370,8 +371,8 @@ static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3128_reg_speed_data = {
- .rmii_10 = RK3128_GMAC_RMII_CLK_2_5M | RK3128_GMAC_SPEED_10M,
- .rmii_100 = RK3128_GMAC_RMII_CLK_25M | RK3128_GMAC_SPEED_100M,
+ .rmii_10 = RK3128_GMAC_RMII_CLK_2_5M,
+ .rmii_100 = RK3128_GMAC_RMII_CLK_25M,
};
static int rk3128_set_speed(struct rk_priv_data *bsp_priv,
@@ -392,6 +393,7 @@ static const struct rk_gmac_ops rk3128_ops = {
.clock_grf_reg = RK3128_GRF_MAC_CON1,
.clock.gmii_clk_sel_mask = GENMASK_U16(13, 12),
+ .clock.mac_speed_mask = BIT_U16(10),
};
#define RK3228_GRF_MAC_CON0 0x0900
@@ -406,8 +408,6 @@ static const struct rk_gmac_ops rk3128_ops = {
/* RK3228_GRF_MAC_CON1 */
#define RK3228_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
-#define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2)
-#define RK3228_GMAC_SPEED_100M GRF_BIT(2)
#define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7)
#define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
#define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
@@ -436,8 +436,8 @@ static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3228_reg_speed_data = {
- .rmii_10 = RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_SPEED_10M,
- .rmii_100 = RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_SPEED_100M,
+ .rmii_10 = RK3228_GMAC_RMII_CLK_2_5M,
+ .rmii_100 = RK3228_GMAC_RMII_CLK_25M,
};
static int rk3228_set_speed(struct rk_priv_data *bsp_priv,
@@ -468,6 +468,7 @@ static const struct rk_gmac_ops rk3228_ops = {
.clock_grf_reg = RK3228_GRF_MAC_CON1,
.clock.gmii_clk_sel_mask = GENMASK_U16(9, 8),
+ .clock.mac_speed_mask = BIT_U16(2),
};
#define RK3288_GRF_SOC_CON1 0x0248
@@ -476,8 +477,6 @@ static const struct rk_gmac_ops rk3228_ops = {
/*RK3288_GRF_SOC_CON1*/
#define RK3288_GMAC_FLOW_CTRL GRF_BIT(9)
#define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
-#define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10)
-#define RK3288_GMAC_SPEED_100M GRF_BIT(10)
#define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11)
#define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
@@ -503,8 +502,8 @@ static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3288_reg_speed_data = {
- .rmii_10 = RK3288_GMAC_RMII_CLK_2_5M | RK3288_GMAC_SPEED_10M,
- .rmii_100 = RK3288_GMAC_RMII_CLK_25M | RK3288_GMAC_SPEED_100M,
+ .rmii_10 = RK3288_GMAC_RMII_CLK_2_5M,
+ .rmii_100 = RK3288_GMAC_RMII_CLK_25M,
};
static int rk3288_set_speed(struct rk_priv_data *bsp_priv,
@@ -525,6 +524,7 @@ static const struct rk_gmac_ops rk3288_ops = {
.clock_grf_reg = RK3288_GRF_SOC_CON1,
.clock.gmii_clk_sel_mask = GENMASK_U16(13, 12),
+ .clock.mac_speed_mask = BIT_U16(10),
};
#define RK3308_GRF_MAC_CON0 0x04a0
@@ -532,16 +532,12 @@ static const struct rk_gmac_ops rk3288_ops = {
/* RK3308_GRF_MAC_CON0 */
#define RK3308_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
-#define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0)
-#define RK3308_GMAC_SPEED_100M GRF_BIT(0)
static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
{
}
static const struct rk_reg_speed_data rk3308_reg_speed_data = {
- .rmii_10 = RK3308_GMAC_SPEED_10M,
- .rmii_100 = RK3308_GMAC_SPEED_100M,
};
static int rk3308_set_speed(struct rk_priv_data *bsp_priv,
@@ -559,6 +555,7 @@ static const struct rk_gmac_ops rk3308_ops = {
.gmac_phy_intf_sel_mask = GENMASK_U16(4, 2),
.clock_grf_reg = RK3308_GRF_MAC_CON0,
+ .clock.mac_speed_mask = BIT_U16(0),
};
#define RK3328_GRF_MAC_CON0 0x0900
@@ -573,8 +570,6 @@ static const struct rk_gmac_ops rk3308_ops = {
/* RK3328_GRF_MAC_CON1 */
#define RK3328_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
-#define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2)
-#define RK3328_GMAC_SPEED_100M GRF_BIT(2)
#define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7)
#define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
#define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
@@ -619,8 +614,8 @@ static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3328_reg_speed_data = {
- .rmii_10 = RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_SPEED_10M,
- .rmii_100 = RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_SPEED_100M,
+ .rmii_10 = RK3328_GMAC_RMII_CLK_2_5M,
+ .rmii_100 = RK3328_GMAC_RMII_CLK_25M,
};
static int rk3328_set_speed(struct rk_priv_data *bsp_priv,
@@ -649,6 +644,8 @@ static const struct rk_gmac_ops rk3328_ops = {
.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
.gmac_rmii_mode_mask = BIT_U16(9),
+ .clock.mac_speed_mask = BIT_U16(2),
+
.regs_valid = true,
.regs = {
0xff540000, /* gmac2io */
@@ -663,8 +660,6 @@ static const struct rk_gmac_ops rk3328_ops = {
/* RK3366_GRF_SOC_CON6 */
#define RK3366_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
-#define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7)
-#define RK3366_GMAC_SPEED_100M GRF_BIT(7)
#define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3)
#define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
@@ -690,8 +685,8 @@ static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3366_reg_speed_data = {
- .rmii_10 = RK3366_GMAC_RMII_CLK_2_5M | RK3366_GMAC_SPEED_10M,
- .rmii_100 = RK3366_GMAC_RMII_CLK_25M | RK3366_GMAC_SPEED_100M,
+ .rmii_10 = RK3366_GMAC_RMII_CLK_2_5M,
+ .rmii_100 = RK3366_GMAC_RMII_CLK_25M,
};
static int rk3366_set_speed(struct rk_priv_data *bsp_priv,
@@ -712,6 +707,7 @@ static const struct rk_gmac_ops rk3366_ops = {
.clock_grf_reg = RK3366_GRF_SOC_CON6,
.clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
+ .clock.mac_speed_mask = BIT_U16(7),
};
#define RK3368_GRF_SOC_CON15 0x043c
@@ -720,8 +716,6 @@ static const struct rk_gmac_ops rk3366_ops = {
/* RK3368_GRF_SOC_CON15 */
#define RK3368_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
-#define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7)
-#define RK3368_GMAC_SPEED_100M GRF_BIT(7)
#define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3)
#define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
@@ -747,8 +741,8 @@ static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3368_reg_speed_data = {
- .rmii_10 = RK3368_GMAC_RMII_CLK_2_5M | RK3368_GMAC_SPEED_10M,
- .rmii_100 = RK3368_GMAC_RMII_CLK_25M | RK3368_GMAC_SPEED_100M,
+ .rmii_10 = RK3368_GMAC_RMII_CLK_2_5M,
+ .rmii_100 = RK3368_GMAC_RMII_CLK_25M,
};
static int rk3368_set_speed(struct rk_priv_data *bsp_priv,
@@ -769,6 +763,7 @@ static const struct rk_gmac_ops rk3368_ops = {
.clock_grf_reg = RK3368_GRF_SOC_CON15,
.clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
+ .clock.mac_speed_mask = BIT_U16(7),
};
#define RK3399_GRF_SOC_CON5 0xc214
@@ -777,8 +772,6 @@ static const struct rk_gmac_ops rk3368_ops = {
/* RK3399_GRF_SOC_CON5 */
#define RK3399_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
-#define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7)
-#define RK3399_GMAC_SPEED_100M GRF_BIT(7)
#define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3)
#define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
@@ -804,8 +797,8 @@ static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rk3399_reg_speed_data = {
- .rmii_10 = RK3399_GMAC_RMII_CLK_2_5M | RK3399_GMAC_SPEED_10M,
- .rmii_100 = RK3399_GMAC_RMII_CLK_25M | RK3399_GMAC_SPEED_100M,
+ .rmii_10 = RK3399_GMAC_RMII_CLK_2_5M,
+ .rmii_100 = RK3399_GMAC_RMII_CLK_25M,
};
static int rk3399_set_speed(struct rk_priv_data *bsp_priv,
@@ -826,6 +819,7 @@ static const struct rk_gmac_ops rk3399_ops = {
.clock_grf_reg = RK3399_GRF_SOC_CON5,
.clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
+ .clock.mac_speed_mask = BIT_U16(7),
};
#define RK3506_GRF_SOC_CON8 0x0020
@@ -1370,8 +1364,6 @@ static const struct rk_gmac_ops rk3588_ops = {
/* RV1108_GRF_GMAC_CON0 */
#define RV1108_GMAC_FLOW_CTRL GRF_BIT(3)
#define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
-#define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2)
-#define RV1108_GMAC_SPEED_100M GRF_BIT(2)
#define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7)
#define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
@@ -1380,8 +1372,8 @@ static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
}
static const struct rk_reg_speed_data rv1108_reg_speed_data = {
- .rmii_10 = RV1108_GMAC_RMII_CLK_2_5M | RV1108_GMAC_SPEED_10M,
- .rmii_100 = RV1108_GMAC_RMII_CLK_25M | RV1108_GMAC_SPEED_100M,
+ .rmii_10 = RV1108_GMAC_RMII_CLK_2_5M,
+ .rmii_100 = RV1108_GMAC_RMII_CLK_25M,
};
static int rv1108_set_speed(struct rk_priv_data *bsp_priv,
@@ -1399,6 +1391,7 @@ static const struct rk_gmac_ops rv1108_ops = {
.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
.clock_grf_reg = RV1108_GRF_GMAC_CON0,
+ .clock.mac_speed_mask = BIT_U16(2),
};
#define RV1126_GRF_GMAC_CON0 0X0070
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH net-next 13/21] net: stmmac: rk: use rk_encode_wm16() for RMII clock
2026-01-23 10:59 [PATCH net-next 00/21] net: stmmac: rk: simplify per-SoC configuration Russell King (Oracle)
` (11 preceding siblings ...)
2026-01-23 11:01 ` [PATCH net-next 12/21] net: stmmac: rk: use rk_encode_wm16() for RMII speed Russell King (Oracle)
@ 2026-01-23 11:01 ` Russell King (Oracle)
2026-01-23 11:01 ` [PATCH net-next 14/21] net: stmmac: rk: remove need for ->set_speed() method Russell King (Oracle)
` (7 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Russell King (Oracle) @ 2026-01-23 11:01 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, netdev, Paolo Abeni
The RMII clock is a single bit, which is set for 100M and clear for
10M. Move this out of struct rk_reg_speed_data (which gets rid of
this structure) into the struct rk_clock_fields as the bitmask for
this bit.
This gets rid of the per-SoC variability in the calls to
rk_set_reg_speed().
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 191 +++---------------
1 file changed, 33 insertions(+), 158 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 48852054390d..9ad9ea90d82c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -28,14 +28,10 @@ struct rk_priv_data;
struct rk_clock_fields {
u16 gmii_clk_sel_mask;
+ u16 rmii_clk_sel_mask;
u16 mac_speed_mask;
};
-struct rk_reg_speed_data {
- unsigned int rmii_10;
- unsigned int rmii_100;
-};
-
struct rk_gmac_ops {
int (*init)(struct rk_priv_data *bsp_priv);
void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
@@ -159,7 +155,6 @@ static int rk_write_clock_grf_reg(struct rk_priv_data *bsp_priv, u32 val)
}
static int rk_set_reg_speed(struct rk_priv_data *bsp_priv,
- const struct rk_reg_speed_data *rsd,
phy_interface_t interface, int speed)
{
unsigned int val;
@@ -173,17 +168,9 @@ static int rk_set_reg_speed(struct rk_priv_data *bsp_priv,
val = rk_encode_wm16(ret, bsp_priv->clock.gmii_clk_sel_mask);
} else if (interface == PHY_INTERFACE_MODE_RMII) {
val = rk_encode_wm16(speed == SPEED_100,
- bsp_priv->clock.mac_speed_mask);
- if (speed == SPEED_10) {
- val |= rsd->rmii_10;
- } else if (speed == SPEED_100) {
- val |= rsd->rmii_100;
- } else {
- /* Phylink will not allow inappropriate speeds for
- * interface modes, so this should never happen.
- */
- return -EINVAL;
- }
+ bsp_priv->clock.mac_speed_mask) |
+ rk_encode_wm16(speed == SPEED_100,
+ bsp_priv->clock.rmii_clk_sel_mask);
} else {
/* This should never happen, as .get_interfaces() limits
* the interface modes that are supported to RGMII and/or
@@ -354,8 +341,6 @@ static const struct rk_gmac_ops px30_ops = {
/* RK3128_GRF_MAC_CON1 */
#define RK3128_GMAC_FLOW_CTRL GRF_BIT(9)
#define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
-#define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11)
-#define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
@@ -370,16 +355,10 @@ static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
{
}
-static const struct rk_reg_speed_data rk3128_reg_speed_data = {
- .rmii_10 = RK3128_GMAC_RMII_CLK_2_5M,
- .rmii_100 = RK3128_GMAC_RMII_CLK_25M,
-};
-
static int rk3128_set_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
- return rk_set_reg_speed(bsp_priv, &rk3128_reg_speed_data,
- interface, speed);
+ return rk_set_reg_speed(bsp_priv, interface, speed);
}
static const struct rk_gmac_ops rk3128_ops = {
@@ -393,6 +372,7 @@ static const struct rk_gmac_ops rk3128_ops = {
.clock_grf_reg = RK3128_GRF_MAC_CON1,
.clock.gmii_clk_sel_mask = GENMASK_U16(13, 12),
+ .clock.rmii_clk_sel_mask = BIT_U16(11),
.clock.mac_speed_mask = BIT_U16(10),
};
@@ -408,8 +388,6 @@ static const struct rk_gmac_ops rk3128_ops = {
/* RK3228_GRF_MAC_CON1 */
#define RK3228_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
-#define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7)
-#define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
#define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
#define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
#define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
@@ -435,16 +413,10 @@ static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
}
-static const struct rk_reg_speed_data rk3228_reg_speed_data = {
- .rmii_10 = RK3228_GMAC_RMII_CLK_2_5M,
- .rmii_100 = RK3228_GMAC_RMII_CLK_25M,
-};
-
static int rk3228_set_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
- return rk_set_reg_speed(bsp_priv, &rk3228_reg_speed_data,
- interface, speed);
+ return rk_set_reg_speed(bsp_priv, interface, speed);
}
static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
@@ -468,6 +440,7 @@ static const struct rk_gmac_ops rk3228_ops = {
.clock_grf_reg = RK3228_GRF_MAC_CON1,
.clock.gmii_clk_sel_mask = GENMASK_U16(9, 8),
+ .clock.rmii_clk_sel_mask = BIT_U16(7),
.clock.mac_speed_mask = BIT_U16(2),
};
@@ -477,8 +450,6 @@ static const struct rk_gmac_ops rk3228_ops = {
/*RK3288_GRF_SOC_CON1*/
#define RK3288_GMAC_FLOW_CTRL GRF_BIT(9)
#define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
-#define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11)
-#define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
/*RK3288_GRF_SOC_CON3*/
#define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
@@ -501,16 +472,10 @@ static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
{
}
-static const struct rk_reg_speed_data rk3288_reg_speed_data = {
- .rmii_10 = RK3288_GMAC_RMII_CLK_2_5M,
- .rmii_100 = RK3288_GMAC_RMII_CLK_25M,
-};
-
static int rk3288_set_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
- return rk_set_reg_speed(bsp_priv, &rk3288_reg_speed_data,
- interface, speed);
+ return rk_set_reg_speed(bsp_priv, interface, speed);
}
static const struct rk_gmac_ops rk3288_ops = {
@@ -524,6 +489,7 @@ static const struct rk_gmac_ops rk3288_ops = {
.clock_grf_reg = RK3288_GRF_SOC_CON1,
.clock.gmii_clk_sel_mask = GENMASK_U16(13, 12),
+ .clock.rmii_clk_sel_mask = BIT_U16(11),
.clock.mac_speed_mask = BIT_U16(10),
};
@@ -537,14 +503,10 @@ static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
{
}
-static const struct rk_reg_speed_data rk3308_reg_speed_data = {
-};
-
static int rk3308_set_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
- return rk_set_reg_speed(bsp_priv, &rk3308_reg_speed_data,
- interface, speed);
+ return rk_set_reg_speed(bsp_priv, interface, speed);
}
static const struct rk_gmac_ops rk3308_ops = {
@@ -570,8 +532,6 @@ static const struct rk_gmac_ops rk3308_ops = {
/* RK3328_GRF_MAC_CON1 */
#define RK3328_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
-#define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7)
-#define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
#define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
#define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
@@ -613,16 +573,10 @@ static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
{
}
-static const struct rk_reg_speed_data rk3328_reg_speed_data = {
- .rmii_10 = RK3328_GMAC_RMII_CLK_2_5M,
- .rmii_100 = RK3328_GMAC_RMII_CLK_25M,
-};
-
static int rk3328_set_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
- return rk_set_reg_speed(bsp_priv, &rk3328_reg_speed_data,
- interface, speed);
+ return rk_set_reg_speed(bsp_priv, interface, speed);
}
static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
@@ -644,6 +598,7 @@ static const struct rk_gmac_ops rk3328_ops = {
.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
.gmac_rmii_mode_mask = BIT_U16(9),
+ .clock.rmii_clk_sel_mask = BIT_U16(7),
.clock.mac_speed_mask = BIT_U16(2),
.regs_valid = true,
@@ -660,8 +615,6 @@ static const struct rk_gmac_ops rk3328_ops = {
/* RK3366_GRF_SOC_CON6 */
#define RK3366_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
-#define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3)
-#define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
/* RK3366_GRF_SOC_CON7 */
#define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
@@ -684,16 +637,10 @@ static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
{
}
-static const struct rk_reg_speed_data rk3366_reg_speed_data = {
- .rmii_10 = RK3366_GMAC_RMII_CLK_2_5M,
- .rmii_100 = RK3366_GMAC_RMII_CLK_25M,
-};
-
static int rk3366_set_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
- return rk_set_reg_speed(bsp_priv, &rk3366_reg_speed_data,
- interface, speed);
+ return rk_set_reg_speed(bsp_priv, interface, speed);
}
static const struct rk_gmac_ops rk3366_ops = {
@@ -707,6 +654,7 @@ static const struct rk_gmac_ops rk3366_ops = {
.clock_grf_reg = RK3366_GRF_SOC_CON6,
.clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
+ .clock.rmii_clk_sel_mask = BIT_U16(3),
.clock.mac_speed_mask = BIT_U16(7),
};
@@ -716,8 +664,6 @@ static const struct rk_gmac_ops rk3366_ops = {
/* RK3368_GRF_SOC_CON15 */
#define RK3368_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
-#define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3)
-#define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
/* RK3368_GRF_SOC_CON16 */
#define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
@@ -740,16 +686,10 @@ static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
{
}
-static const struct rk_reg_speed_data rk3368_reg_speed_data = {
- .rmii_10 = RK3368_GMAC_RMII_CLK_2_5M,
- .rmii_100 = RK3368_GMAC_RMII_CLK_25M,
-};
-
static int rk3368_set_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
- return rk_set_reg_speed(bsp_priv, &rk3368_reg_speed_data,
- interface, speed);
+ return rk_set_reg_speed(bsp_priv, interface, speed);
}
static const struct rk_gmac_ops rk3368_ops = {
@@ -763,6 +703,7 @@ static const struct rk_gmac_ops rk3368_ops = {
.clock_grf_reg = RK3368_GRF_SOC_CON15,
.clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
+ .clock.rmii_clk_sel_mask = BIT_U16(3),
.clock.mac_speed_mask = BIT_U16(7),
};
@@ -772,8 +713,6 @@ static const struct rk_gmac_ops rk3368_ops = {
/* RK3399_GRF_SOC_CON5 */
#define RK3399_GMAC_FLOW_CTRL GRF_BIT(8)
#define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
-#define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3)
-#define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
/* RK3399_GRF_SOC_CON6 */
#define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
@@ -796,16 +735,10 @@ static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
{
}
-static const struct rk_reg_speed_data rk3399_reg_speed_data = {
- .rmii_10 = RK3399_GMAC_RMII_CLK_2_5M,
- .rmii_100 = RK3399_GMAC_RMII_CLK_25M,
-};
-
static int rk3399_set_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
- return rk_set_reg_speed(bsp_priv, &rk3399_reg_speed_data,
- interface, speed);
+ return rk_set_reg_speed(bsp_priv, interface, speed);
}
static const struct rk_gmac_ops rk3399_ops = {
@@ -819,6 +752,7 @@ static const struct rk_gmac_ops rk3399_ops = {
.clock_grf_reg = RK3399_GRF_SOC_CON5,
.clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
+ .clock.rmii_clk_sel_mask = BIT_U16(3),
.clock.mac_speed_mask = BIT_U16(7),
};
@@ -827,9 +761,6 @@ static const struct rk_gmac_ops rk3399_ops = {
#define RK3506_GMAC_RMII_MODE GRF_BIT(1)
-#define RK3506_GMAC_CLK_RMII_DIV2 GRF_BIT(3)
-#define RK3506_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(3)
-
#define RK3506_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(5)
#define RK3506_GMAC_CLK_SELECT_IO GRF_BIT(5)
@@ -860,16 +791,10 @@ static void rk3506_set_to_rmii(struct rk_priv_data *bsp_priv)
regmap_write(bsp_priv->grf, offset, RK3506_GMAC_RMII_MODE);
}
-static const struct rk_reg_speed_data rk3506_reg_speed_data = {
- .rmii_10 = RK3506_GMAC_CLK_RMII_DIV20,
- .rmii_100 = RK3506_GMAC_CLK_RMII_DIV2,
-};
-
static int rk3506_set_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
- return rk_set_reg_speed(bsp_priv, &rk3506_reg_speed_data,
- interface, speed);
+ return rk_set_reg_speed(bsp_priv, interface, speed);
}
static void rk3506_set_clock_selection(struct rk_priv_data *bsp_priv,
@@ -891,6 +816,9 @@ static const struct rk_gmac_ops rk3506_ops = {
.set_to_rmii = rk3506_set_to_rmii,
.set_speed = rk3506_set_speed,
.set_clock_selection = rk3506_set_clock_selection,
+
+ .clock.rmii_clk_sel_mask = BIT_U16(3),
+
.regs_valid = true,
.regs = {
0xff4c8000, /* gmac0 */
@@ -920,11 +848,6 @@ static const struct rk_gmac_ops rk3506_ops = {
#define RK3528_GMAC1_CLK_SELECT_CRU GRF_CLR_BIT(12)
#define RK3528_GMAC1_CLK_SELECT_IO GRF_BIT(12)
-#define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3)
-#define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3)
-#define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10)
-#define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10)
-
#define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2)
#define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2)
#define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9)
@@ -935,11 +858,13 @@ static int rk3528_init(struct rk_priv_data *bsp_priv)
switch (bsp_priv->id) {
case 0:
bsp_priv->clock_grf_reg = RK3528_VO_GRF_GMAC_CON;
+ bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(3);
return 0;
case 1:
bsp_priv->clock_grf_reg = RK3528_VPU_GRF_GMAC_CON5;
bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(11, 10);
+ bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(10);
return 0;
default:
@@ -971,27 +896,10 @@ static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)
RK3528_GMAC0_PHY_INTF_SEL_RMII);
}
-static const struct rk_reg_speed_data rk3528_gmac0_reg_speed_data = {
- .rmii_10 = RK3528_GMAC0_CLK_RMII_DIV20,
- .rmii_100 = RK3528_GMAC0_CLK_RMII_DIV2,
-};
-
-static const struct rk_reg_speed_data rk3528_gmac1_reg_speed_data = {
- .rmii_10 = RK3528_GMAC1_CLK_RMII_DIV20,
- .rmii_100 = RK3528_GMAC1_CLK_RMII_DIV2,
-};
-
static int rk3528_set_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
- const struct rk_reg_speed_data *rsd;
-
- if (bsp_priv->id == 1)
- rsd = &rk3528_gmac1_reg_speed_data;
- else
- rsd = &rk3528_gmac0_reg_speed_data;
-
- return rk_set_reg_speed(bsp_priv, rsd, interface, speed);
+ return rk_set_reg_speed(bsp_priv, interface, speed);
}
static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv,
@@ -1131,9 +1039,6 @@ static const struct rk_gmac_ops rk3568_ops = {
#define RK3576_GMAC_CLK_SELECT_IO GRF_BIT(7)
#define RK3576_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(7)
-#define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5)
-#define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5)
-
#define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4)
#define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4)
@@ -1182,16 +1087,10 @@ static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv)
{
}
-static const struct rk_reg_speed_data rk3578_reg_speed_data = {
- .rmii_10 = RK3576_GMAC_CLK_RMII_DIV20,
- .rmii_100 = RK3576_GMAC_CLK_RMII_DIV2,
-};
-
static int rk3576_set_gmac_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
- return rk_set_reg_speed(bsp_priv, &rk3578_reg_speed_data,
- interface, speed);
+ return rk_set_reg_speed(bsp_priv, interface, speed);
}
static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
@@ -1220,6 +1119,7 @@ static const struct rk_gmac_ops rk3576_ops = {
.gmac_rmii_mode_mask = BIT_U16(3),
.clock.gmii_clk_sel_mask = GENMASK_U16(6, 5),
+ .clock.rmii_clk_sel_mask = BIT_U16(5),
.php_grf_required = true,
.regs_valid = true,
@@ -1253,9 +1153,6 @@ static const struct rk_gmac_ops rk3576_ops = {
#define RK3588_GMAC_CLK_SELECT_CRU(id) GRF_BIT(5 * (id) + 4)
#define RK3588_GMAC_CLK_SELECT_IO(id) GRF_CLR_BIT(5 * (id) + 4)
-#define RK3588_GMA_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2)
-#define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2)
-
#define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1)
#define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1)
@@ -1265,11 +1162,13 @@ static int rk3588_init(struct rk_priv_data *bsp_priv)
case 0:
bsp_priv->gmac_phy_intf_sel_mask = GENMASK_U16(5, 3);
bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(3, 2);
+ bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(2);
return 0;
case 1:
bsp_priv->gmac_phy_intf_sel_mask = GENMASK_U16(11, 9);
bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(8, 7);
+ bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(7);
return 0;
default:
@@ -1303,27 +1202,10 @@ static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id));
}
-static const struct rk_reg_speed_data rk3588_gmac0_speed_data = {
- .rmii_10 = RK3588_GMA_CLK_RMII_DIV20(0),
- .rmii_100 = RK3588_GMA_CLK_RMII_DIV2(0),
-};
-
-static const struct rk_reg_speed_data rk3588_gmac1_speed_data = {
- .rmii_10 = RK3588_GMA_CLK_RMII_DIV20(1),
- .rmii_100 = RK3588_GMA_CLK_RMII_DIV2(1),
-};
-
static int rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
- const struct rk_reg_speed_data *rsd;
-
- if (bsp_priv->id == 0)
- rsd = &rk3588_gmac0_speed_data;
- else
- rsd = &rk3588_gmac1_speed_data;
-
- return rk_set_reg_speed(bsp_priv, rsd, interface, speed);
+ return rk_set_reg_speed(bsp_priv, interface, speed);
}
static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
@@ -1364,23 +1246,15 @@ static const struct rk_gmac_ops rk3588_ops = {
/* RV1108_GRF_GMAC_CON0 */
#define RV1108_GMAC_FLOW_CTRL GRF_BIT(3)
#define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
-#define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7)
-#define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
{
}
-static const struct rk_reg_speed_data rv1108_reg_speed_data = {
- .rmii_10 = RV1108_GMAC_RMII_CLK_2_5M,
- .rmii_100 = RV1108_GMAC_RMII_CLK_25M,
-};
-
static int rv1108_set_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
- return rk_set_reg_speed(bsp_priv, &rv1108_reg_speed_data,
- interface, speed);
+ return rk_set_reg_speed(bsp_priv, interface, speed);
}
static const struct rk_gmac_ops rv1108_ops = {
@@ -1391,6 +1265,7 @@ static const struct rk_gmac_ops rv1108_ops = {
.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
.clock_grf_reg = RV1108_GRF_GMAC_CON0,
+ .clock.rmii_clk_sel_mask = BIT_U16(7),
.clock.mac_speed_mask = BIT_U16(2),
};
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH net-next 14/21] net: stmmac: rk: remove need for ->set_speed() method
2026-01-23 10:59 [PATCH net-next 00/21] net: stmmac: rk: simplify per-SoC configuration Russell King (Oracle)
` (12 preceding siblings ...)
2026-01-23 11:01 ` [PATCH net-next 13/21] net: stmmac: rk: use rk_encode_wm16() for RMII clock Russell King (Oracle)
@ 2026-01-23 11:01 ` Russell King (Oracle)
2026-01-23 11:01 ` [PATCH net-next 15/21] net: stmmac: rk: convert px30 Russell King (Oracle)
` (6 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Russell King (Oracle) @ 2026-01-23 11:01 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, netdev, Paolo Abeni
As we can detect whether the SoC provides the parameters necessary for
rk_set_reg_speed(), we don't need to have explicit calls to this.
Instead, we can move the contents of this function to
rk_set_clk_tx_rate().
This remsoves all the .set_speed() implementations that merely go on to
invoke rk_set_reg_speed().
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 153 ++++--------------
1 file changed, 28 insertions(+), 125 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 9ad9ea90d82c..812e6729a703 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -154,37 +154,6 @@ static int rk_write_clock_grf_reg(struct rk_priv_data *bsp_priv, u32 val)
return regmap_write(regmap, bsp_priv->clock_grf_reg, val);
}
-static int rk_set_reg_speed(struct rk_priv_data *bsp_priv,
- phy_interface_t interface, int speed)
-{
- unsigned int val;
- int ret;
-
- if (phy_interface_mode_is_rgmii(interface)) {
- ret = rk_gmac_rgmii_clk_div(speed);
- if (ret < 0)
- return ret;
-
- val = rk_encode_wm16(ret, bsp_priv->clock.gmii_clk_sel_mask);
- } else if (interface == PHY_INTERFACE_MODE_RMII) {
- val = rk_encode_wm16(speed == SPEED_100,
- bsp_priv->clock.mac_speed_mask) |
- rk_encode_wm16(speed == SPEED_100,
- bsp_priv->clock.rmii_clk_sel_mask);
- } else {
- /* This should never happen, as .get_interfaces() limits
- * the interface modes that are supported to RGMII and/or
- * RMII.
- */
- return -EINVAL;
- }
-
- rk_write_clock_grf_reg(bsp_priv, val);
-
- return 0;
-
-}
-
static int rk_set_clk_mac_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
@@ -355,16 +324,9 @@ static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
{
}
-static int rk3128_set_speed(struct rk_priv_data *bsp_priv,
- phy_interface_t interface, int speed)
-{
- return rk_set_reg_speed(bsp_priv, interface, speed);
-}
-
static const struct rk_gmac_ops rk3128_ops = {
.set_to_rgmii = rk3128_set_to_rgmii,
.set_to_rmii = rk3128_set_to_rmii,
- .set_speed = rk3128_set_speed,
.gmac_grf_reg = RK3128_GRF_MAC_CON1,
.gmac_phy_intf_sel_mask = GENMASK_U16(8, 6),
@@ -413,12 +375,6 @@ static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
}
-static int rk3228_set_speed(struct rk_priv_data *bsp_priv,
- phy_interface_t interface, int speed)
-{
- return rk_set_reg_speed(bsp_priv, interface, speed);
-}
-
static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
{
regmap_write(priv->grf, RK3228_GRF_CON_MUX,
@@ -430,7 +386,6 @@ static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
static const struct rk_gmac_ops rk3228_ops = {
.set_to_rgmii = rk3228_set_to_rgmii,
.set_to_rmii = rk3228_set_to_rmii,
- .set_speed = rk3228_set_speed,
.integrated_phy_powerup = rk3228_integrated_phy_powerup,
.integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,
@@ -472,16 +427,9 @@ static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
{
}
-static int rk3288_set_speed(struct rk_priv_data *bsp_priv,
- phy_interface_t interface, int speed)
-{
- return rk_set_reg_speed(bsp_priv, interface, speed);
-}
-
static const struct rk_gmac_ops rk3288_ops = {
.set_to_rgmii = rk3288_set_to_rgmii,
.set_to_rmii = rk3288_set_to_rmii,
- .set_speed = rk3288_set_speed,
.gmac_grf_reg = RK3288_GRF_SOC_CON1,
.gmac_phy_intf_sel_mask = GENMASK_U16(8, 6),
@@ -503,15 +451,8 @@ static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
{
}
-static int rk3308_set_speed(struct rk_priv_data *bsp_priv,
- phy_interface_t interface, int speed)
-{
- return rk_set_reg_speed(bsp_priv, interface, speed);
-}
-
static const struct rk_gmac_ops rk3308_ops = {
.set_to_rmii = rk3308_set_to_rmii,
- .set_speed = rk3308_set_speed,
.gmac_grf_reg = RK3308_GRF_MAC_CON0,
.gmac_phy_intf_sel_mask = GENMASK_U16(4, 2),
@@ -573,12 +514,6 @@ static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
{
}
-static int rk3328_set_speed(struct rk_priv_data *bsp_priv,
- phy_interface_t interface, int speed)
-{
- return rk_set_reg_speed(bsp_priv, interface, speed);
-}
-
static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
{
regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
@@ -591,7 +526,6 @@ static const struct rk_gmac_ops rk3328_ops = {
.init = rk3328_init,
.set_to_rgmii = rk3328_set_to_rgmii,
.set_to_rmii = rk3328_set_to_rmii,
- .set_speed = rk3328_set_speed,
.integrated_phy_powerup = rk3328_integrated_phy_powerup,
.integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,
@@ -637,16 +571,9 @@ static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
{
}
-static int rk3366_set_speed(struct rk_priv_data *bsp_priv,
- phy_interface_t interface, int speed)
-{
- return rk_set_reg_speed(bsp_priv, interface, speed);
-}
-
static const struct rk_gmac_ops rk3366_ops = {
.set_to_rgmii = rk3366_set_to_rgmii,
.set_to_rmii = rk3366_set_to_rmii,
- .set_speed = rk3366_set_speed,
.gmac_grf_reg = RK3366_GRF_SOC_CON6,
.gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
@@ -686,16 +613,9 @@ static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
{
}
-static int rk3368_set_speed(struct rk_priv_data *bsp_priv,
- phy_interface_t interface, int speed)
-{
- return rk_set_reg_speed(bsp_priv, interface, speed);
-}
-
static const struct rk_gmac_ops rk3368_ops = {
.set_to_rgmii = rk3368_set_to_rgmii,
.set_to_rmii = rk3368_set_to_rmii,
- .set_speed = rk3368_set_speed,
.gmac_grf_reg = RK3368_GRF_SOC_CON15,
.gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
@@ -735,16 +655,9 @@ static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
{
}
-static int rk3399_set_speed(struct rk_priv_data *bsp_priv,
- phy_interface_t interface, int speed)
-{
- return rk_set_reg_speed(bsp_priv, interface, speed);
-}
-
static const struct rk_gmac_ops rk3399_ops = {
.set_to_rgmii = rk3399_set_to_rgmii,
.set_to_rmii = rk3399_set_to_rmii,
- .set_speed = rk3399_set_speed,
.gmac_grf_reg = RK3399_GRF_SOC_CON5,
.gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
@@ -791,12 +704,6 @@ static void rk3506_set_to_rmii(struct rk_priv_data *bsp_priv)
regmap_write(bsp_priv->grf, offset, RK3506_GMAC_RMII_MODE);
}
-static int rk3506_set_speed(struct rk_priv_data *bsp_priv,
- phy_interface_t interface, int speed)
-{
- return rk_set_reg_speed(bsp_priv, interface, speed);
-}
-
static void rk3506_set_clock_selection(struct rk_priv_data *bsp_priv,
bool input, bool enable)
{
@@ -814,7 +721,6 @@ static void rk3506_set_clock_selection(struct rk_priv_data *bsp_priv,
static const struct rk_gmac_ops rk3506_ops = {
.init = rk3506_init,
.set_to_rmii = rk3506_set_to_rmii,
- .set_speed = rk3506_set_speed,
.set_clock_selection = rk3506_set_clock_selection,
.clock.rmii_clk_sel_mask = BIT_U16(3),
@@ -896,12 +802,6 @@ static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)
RK3528_GMAC0_PHY_INTF_SEL_RMII);
}
-static int rk3528_set_speed(struct rk_priv_data *bsp_priv,
- phy_interface_t interface, int speed)
-{
- return rk_set_reg_speed(bsp_priv, interface, speed);
-}
-
static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv,
bool input, bool enable)
{
@@ -934,7 +834,6 @@ static const struct rk_gmac_ops rk3528_ops = {
.init = rk3528_init,
.set_to_rgmii = rk3528_set_to_rgmii,
.set_to_rmii = rk3528_set_to_rmii,
- .set_speed = rk3528_set_speed,
.set_clock_selection = rk3528_set_clock_selection,
.integrated_phy_powerup = rk3528_integrated_phy_powerup,
.integrated_phy_powerdown = rk3528_integrated_phy_powerdown,
@@ -1087,12 +986,6 @@ static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv)
{
}
-static int rk3576_set_gmac_speed(struct rk_priv_data *bsp_priv,
- phy_interface_t interface, int speed)
-{
- return rk_set_reg_speed(bsp_priv, interface, speed);
-}
-
static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
bool enable)
{
@@ -1113,7 +1006,6 @@ static const struct rk_gmac_ops rk3576_ops = {
.init = rk3576_init,
.set_to_rgmii = rk3576_set_to_rgmii,
.set_to_rmii = rk3576_set_to_rmii,
- .set_speed = rk3576_set_gmac_speed,
.set_clock_selection = rk3576_set_clock_selection,
.gmac_rmii_mode_mask = BIT_U16(3),
@@ -1202,12 +1094,6 @@ static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id));
}
-static int rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv,
- phy_interface_t interface, int speed)
-{
- return rk_set_reg_speed(bsp_priv, interface, speed);
-}
-
static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
bool enable)
{
@@ -1224,7 +1110,6 @@ static const struct rk_gmac_ops rk3588_ops = {
.init = rk3588_init,
.set_to_rgmii = rk3588_set_to_rgmii,
.set_to_rmii = rk3588_set_to_rmii,
- .set_speed = rk3588_set_gmac_speed,
.set_clock_selection = rk3588_set_clock_selection,
.gmac_grf_reg = RK3588_GRF_GMAC_CON0,
@@ -1251,15 +1136,8 @@ static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
{
}
-static int rv1108_set_speed(struct rk_priv_data *bsp_priv,
- phy_interface_t interface, int speed)
-{
- return rk_set_reg_speed(bsp_priv, interface, speed);
-}
-
static const struct rk_gmac_ops rv1108_ops = {
.set_to_rmii = rv1108_set_to_rmii,
- .set_speed = rv1108_set_speed,
.gmac_grf_reg = RV1108_GRF_GMAC_CON0,
.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
@@ -1685,11 +1563,36 @@ static int rk_set_clk_tx_rate(void *bsp_priv_, struct clk *clk_tx_i,
phy_interface_t interface, int speed)
{
struct rk_priv_data *bsp_priv = bsp_priv_;
+ int ret = -EINVAL;
+ bool is_100m;
+ u32 val;
- if (bsp_priv->ops->set_speed)
- return bsp_priv->ops->set_speed(bsp_priv, interface, speed);
+ if (bsp_priv->ops->set_speed) {
+ ret = bsp_priv->ops->set_speed(bsp_priv, interface, speed);
+ if (ret < 0)
+ return ret;
+ }
- return -EINVAL;
+ if (phy_interface_mode_is_rgmii(interface) &&
+ bsp_priv->clock.gmii_clk_sel_mask) {
+ ret = rk_gmac_rgmii_clk_div(speed);
+ if (ret < 0)
+ return ret;
+
+ val = rk_encode_wm16(ret, bsp_priv->clock.gmii_clk_sel_mask);
+
+ ret = rk_write_clock_grf_reg(bsp_priv, val);
+ } else if (interface == PHY_INTERFACE_MODE_RMII &&
+ (bsp_priv->clock.rmii_clk_sel_mask ||
+ bsp_priv->clock.mac_speed_mask)) {
+ is_100m = speed == SPEED_100;
+ val = rk_encode_wm16(is_100m, bsp_priv->clock.mac_speed_mask) |
+ rk_encode_wm16(is_100m, bsp_priv->clock.rmii_clk_sel_mask);
+
+ ret = rk_write_clock_grf_reg(bsp_priv, val);
+ }
+
+ return ret;
}
static int rk_gmac_suspend(struct device *dev, void *bsp_priv_)
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH net-next 15/21] net: stmmac: rk: convert px30
2026-01-23 10:59 [PATCH net-next 00/21] net: stmmac: rk: simplify per-SoC configuration Russell King (Oracle)
` (13 preceding siblings ...)
2026-01-23 11:01 ` [PATCH net-next 14/21] net: stmmac: rk: remove need for ->set_speed() method Russell King (Oracle)
@ 2026-01-23 11:01 ` Russell King (Oracle)
2026-01-23 11:01 ` [PATCH net-next 16/21] net: stmmac: rk: introduce flags indicating support for RGMII/RMII Russell King (Oracle)
` (5 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Russell King (Oracle) @ 2026-01-23 11:01 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, netdev, Paolo Abeni
Use rk_set_clk_mac_speed() rather than px30 specific function for
configuring RMII clock.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 38 ++-----------------
1 file changed, 4 insertions(+), 34 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 812e6729a703..802052beb668 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -251,49 +251,19 @@ static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv,
#define PX30_GRF_GMAC_CON1 0x0904
-/* PX30_GRF_GMAC_CON1 */
-#define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2)
-#define PX30_GMAC_SPEED_100M GRF_BIT(2)
-
static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)
{
}
-static int px30_set_speed(struct rk_priv_data *bsp_priv,
- phy_interface_t interface, int speed)
-{
- struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk;
- struct device *dev = bsp_priv->dev;
- unsigned int con1;
- long rate;
-
- if (!clk_mac_speed) {
- dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__);
- return -EINVAL;
- }
-
- if (speed == 10) {
- con1 = PX30_GMAC_SPEED_10M;
- rate = 2500000;
- } else if (speed == 100) {
- con1 = PX30_GMAC_SPEED_100M;
- rate = 25000000;
- } else {
- dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
- return -EINVAL;
- }
-
- regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, con1);
-
- return clk_set_rate(clk_mac_speed, rate);
-}
-
static const struct rk_gmac_ops px30_ops = {
.set_to_rmii = px30_set_to_rmii,
- .set_speed = px30_set_speed,
+ .set_speed = rk_set_clk_mac_speed,
.gmac_grf_reg = PX30_GRF_GMAC_CON1,
.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
+
+ .clock_grf_reg = PX30_GRF_GMAC_CON1,
+ .clock.mac_speed_mask = BIT_U16(2),
};
#define RK3128_GRF_MAC_CON0 0x0168
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH net-next 16/21] net: stmmac: rk: introduce flags indicating support for RGMII/RMII
2026-01-23 10:59 [PATCH net-next 00/21] net: stmmac: rk: simplify per-SoC configuration Russell King (Oracle)
` (14 preceding siblings ...)
2026-01-23 11:01 ` [PATCH net-next 15/21] net: stmmac: rk: convert px30 Russell King (Oracle)
@ 2026-01-23 11:01 ` Russell King (Oracle)
2026-01-23 11:01 ` [PATCH net-next 17/21] net: stmmac: rk: replace empty set_to_rmii() with supports_rmii Russell King (Oracle)
` (4 subsequent siblings)
20 siblings, 0 replies; 31+ messages in thread
From: Russell King (Oracle) @ 2026-01-23 11:01 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, netdev, Paolo Abeni
Introduce two boolean flags into struct rk_priv_data indicating
whether RGMII and/or RMII is supported for this instance. Use these
to configure the supported_interfaces mask for phylink, validate the
interface mode. Initialise these from equivalent flags in the
rk_gmac_ops or depending on the presence of the ops->set_to_rgmii and
ops->set_to_mii methods. Finally, make ops->set_to_* optional.
This will allow us to get rid of empty set_to_rmii() methods.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 35 +++++++++++++------
1 file changed, 25 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 802052beb668..49a075565832 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -52,6 +52,8 @@ struct rk_gmac_ops {
struct rk_clock_fields clock;
bool clock_grf_reg_in_php;
+ bool supports_rgmii;
+ bool supports_rmii;
bool php_grf_required;
bool regs_valid;
u32 regs[];
@@ -85,6 +87,8 @@ struct rk_priv_data {
bool clk_enabled;
bool clock_input;
bool integrated_phy;
+ bool supports_rgmii;
+ bool supports_rmii;
struct clk_bulk_data *clks;
int num_clks;
@@ -1401,6 +1405,9 @@ static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
bsp_priv->clock_grf_reg = ops->clock_grf_reg;
bsp_priv->clock = ops->clock;
+ bsp_priv->supports_rgmii = ops->supports_rgmii || !!ops->set_to_rgmii;
+ bsp_priv->supports_rmii = ops->supports_rmii || !!ops->set_to_rmii;
+
if (ops->init) {
ret = ops->init(bsp_priv);
if (ret) {
@@ -1419,11 +1426,11 @@ static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv)
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
- if (!bsp_priv->ops->set_to_rgmii)
+ if (!bsp_priv->supports_rgmii)
return -EINVAL;
break;
case PHY_INTERFACE_MODE_RMII:
- if (!bsp_priv->ops->set_to_rmii)
+ if (!bsp_priv->supports_rmii)
return -EINVAL;
break;
default:
@@ -1469,24 +1476,32 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
switch (bsp_priv->phy_iface) {
case PHY_INTERFACE_MODE_RGMII:
dev_info(dev, "init for RGMII\n");
- bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay,
- bsp_priv->rx_delay);
+ if (bsp_priv->ops->set_to_rgmii)
+ bsp_priv->ops->set_to_rgmii(bsp_priv,
+ bsp_priv->tx_delay,
+ bsp_priv->rx_delay);
break;
case PHY_INTERFACE_MODE_RGMII_ID:
dev_info(dev, "init for RGMII_ID\n");
- bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
+ if (bsp_priv->ops->set_to_rgmii)
+ bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
break;
case PHY_INTERFACE_MODE_RGMII_RXID:
dev_info(dev, "init for RGMII_RXID\n");
- bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0);
+ if (bsp_priv->ops->set_to_rgmii)
+ bsp_priv->ops->set_to_rgmii(bsp_priv,
+ bsp_priv->tx_delay, 0);
break;
case PHY_INTERFACE_MODE_RGMII_TXID:
dev_info(dev, "init for RGMII_TXID\n");
- bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay);
+ if (bsp_priv->ops->set_to_rgmii)
+ bsp_priv->ops->set_to_rgmii(bsp_priv,
+ 0, bsp_priv->rx_delay);
break;
case PHY_INTERFACE_MODE_RMII:
dev_info(dev, "init for RMII\n");
- bsp_priv->ops->set_to_rmii(bsp_priv);
+ if (bsp_priv->ops->set_to_rmii)
+ bsp_priv->ops->set_to_rmii(bsp_priv);
break;
default:
dev_err(dev, "NO interface defined!\n");
@@ -1522,10 +1537,10 @@ static void rk_get_interfaces(struct stmmac_priv *priv, void *bsp_priv,
{
struct rk_priv_data *rk = bsp_priv;
- if (rk->ops->set_to_rgmii)
+ if (rk->supports_rgmii)
phy_interface_set_rgmii(interfaces);
- if (rk->ops->set_to_rmii)
+ if (rk->supports_rmii)
__set_bit(PHY_INTERFACE_MODE_RMII, interfaces);
}
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH net-next 17/21] net: stmmac: rk: replace empty set_to_rmii() with supports_rmii
2026-01-23 10:59 [PATCH net-next 00/21] net: stmmac: rk: simplify per-SoC configuration Russell King (Oracle)
` (15 preceding siblings ...)
2026-01-23 11:01 ` [PATCH net-next 16/21] net: stmmac: rk: introduce flags indicating support for RGMII/RMII Russell King (Oracle)
@ 2026-01-23 11:01 ` Russell King (Oracle)
2026-01-25 22:16 ` [net-next,17/21] " Jakub Kicinski
2026-01-23 11:01 ` [PATCH net-next 18/21] net: stmmac: rk: rk3328: gmac2phy only supports RMII Russell King (Oracle)
` (3 subsequent siblings)
20 siblings, 1 reply; 31+ messages in thread
From: Russell King (Oracle) @ 2026-01-23 11:01 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, netdev, Paolo Abeni
Rather than providing a now-empty set_to_rmii() method to indicate
that RMII is supported, switch to setting ops->supports_rmii instead.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 86 ++++++-------------
1 file changed, 24 insertions(+), 62 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 49a075565832..2d464ecb0e8f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -255,12 +255,7 @@ static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv,
#define PX30_GRF_GMAC_CON1 0x0904
-static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
-}
-
static const struct rk_gmac_ops px30_ops = {
- .set_to_rmii = px30_set_to_rmii,
.set_speed = rk_set_clk_mac_speed,
.gmac_grf_reg = PX30_GRF_GMAC_CON1,
@@ -268,6 +263,8 @@ static const struct rk_gmac_ops px30_ops = {
.clock_grf_reg = PX30_GRF_GMAC_CON1,
.clock.mac_speed_mask = BIT_U16(2),
+
+ .supports_rmii = true,
};
#define RK3128_GRF_MAC_CON0 0x0168
@@ -294,13 +291,8 @@ static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));
}
-static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
-}
-
static const struct rk_gmac_ops rk3128_ops = {
.set_to_rgmii = rk3128_set_to_rgmii,
- .set_to_rmii = rk3128_set_to_rmii,
.gmac_grf_reg = RK3128_GRF_MAC_CON1,
.gmac_phy_intf_sel_mask = GENMASK_U16(8, 6),
@@ -310,6 +302,8 @@ static const struct rk_gmac_ops rk3128_ops = {
.clock.gmii_clk_sel_mask = GENMASK_U16(13, 12),
.clock.rmii_clk_sel_mask = BIT_U16(11),
.clock.mac_speed_mask = BIT_U16(10),
+
+ .supports_rmii = true,
};
#define RK3228_GRF_MAC_CON0 0x0900
@@ -397,13 +391,8 @@ static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
}
-static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
-}
-
static const struct rk_gmac_ops rk3288_ops = {
.set_to_rgmii = rk3288_set_to_rgmii,
- .set_to_rmii = rk3288_set_to_rmii,
.gmac_grf_reg = RK3288_GRF_SOC_CON1,
.gmac_phy_intf_sel_mask = GENMASK_U16(8, 6),
@@ -413,6 +402,8 @@ static const struct rk_gmac_ops rk3288_ops = {
.clock.gmii_clk_sel_mask = GENMASK_U16(13, 12),
.clock.rmii_clk_sel_mask = BIT_U16(11),
.clock.mac_speed_mask = BIT_U16(10),
+
+ .supports_rmii = true,
};
#define RK3308_GRF_MAC_CON0 0x04a0
@@ -421,18 +412,14 @@ static const struct rk_gmac_ops rk3288_ops = {
#define RK3308_GMAC_FLOW_CTRL GRF_BIT(3)
#define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
-static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
-}
-
static const struct rk_gmac_ops rk3308_ops = {
- .set_to_rmii = rk3308_set_to_rmii,
-
.gmac_grf_reg = RK3308_GRF_MAC_CON0,
.gmac_phy_intf_sel_mask = GENMASK_U16(4, 2),
.clock_grf_reg = RK3308_GRF_MAC_CON0,
.clock.mac_speed_mask = BIT_U16(0),
+
+ .supports_rmii = true,
};
#define RK3328_GRF_MAC_CON0 0x0900
@@ -484,10 +471,6 @@ static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
}
-static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
-}
-
static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
{
regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
@@ -499,7 +482,6 @@ static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
static const struct rk_gmac_ops rk3328_ops = {
.init = rk3328_init,
.set_to_rgmii = rk3328_set_to_rgmii,
- .set_to_rmii = rk3328_set_to_rmii,
.integrated_phy_powerup = rk3328_integrated_phy_powerup,
.integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,
@@ -509,6 +491,8 @@ static const struct rk_gmac_ops rk3328_ops = {
.clock.rmii_clk_sel_mask = BIT_U16(7),
.clock.mac_speed_mask = BIT_U16(2),
+ .supports_rmii = true,
+
.regs_valid = true,
.regs = {
0xff540000, /* gmac2io */
@@ -541,13 +525,8 @@ static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
}
-static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
-}
-
static const struct rk_gmac_ops rk3366_ops = {
.set_to_rgmii = rk3366_set_to_rgmii,
- .set_to_rmii = rk3366_set_to_rmii,
.gmac_grf_reg = RK3366_GRF_SOC_CON6,
.gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
@@ -557,6 +536,8 @@ static const struct rk_gmac_ops rk3366_ops = {
.clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
.clock.rmii_clk_sel_mask = BIT_U16(3),
.clock.mac_speed_mask = BIT_U16(7),
+
+ .supports_rmii = true,
};
#define RK3368_GRF_SOC_CON15 0x043c
@@ -583,13 +564,8 @@ static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
}
-static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
-}
-
static const struct rk_gmac_ops rk3368_ops = {
.set_to_rgmii = rk3368_set_to_rgmii,
- .set_to_rmii = rk3368_set_to_rmii,
.gmac_grf_reg = RK3368_GRF_SOC_CON15,
.gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
@@ -599,6 +575,8 @@ static const struct rk_gmac_ops rk3368_ops = {
.clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
.clock.rmii_clk_sel_mask = BIT_U16(3),
.clock.mac_speed_mask = BIT_U16(7),
+
+ .supports_rmii = true,
};
#define RK3399_GRF_SOC_CON5 0xc214
@@ -625,13 +603,8 @@ static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
}
-static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
-}
-
static const struct rk_gmac_ops rk3399_ops = {
.set_to_rgmii = rk3399_set_to_rgmii,
- .set_to_rmii = rk3399_set_to_rmii,
.gmac_grf_reg = RK3399_GRF_SOC_CON5,
.gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
@@ -641,6 +614,8 @@ static const struct rk_gmac_ops rk3399_ops = {
.clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
.clock.rmii_clk_sel_mask = BIT_U16(3),
.clock.mac_speed_mask = BIT_U16(7),
+
+ .supports_rmii = true,
};
#define RK3506_GRF_SOC_CON8 0x0020
@@ -871,18 +846,15 @@ static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
RK3568_GMAC_TXCLK_DLY_ENABLE);
}
-static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
-}
-
static const struct rk_gmac_ops rk3568_ops = {
.init = rk3568_init,
.set_to_rgmii = rk3568_set_to_rgmii,
- .set_to_rmii = rk3568_set_to_rmii,
.set_speed = rk_set_clk_mac_speed,
.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
+ .supports_rmii = true,
+
.regs_valid = true,
.regs = {
0xfe2a0000, /* gmac0 */
@@ -956,10 +928,6 @@ static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv,
RK3576_GMAC_CLK_RX_DL_CFG(rx_delay));
}
-static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
-}
-
static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
bool enable)
{
@@ -979,7 +947,6 @@ static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input
static const struct rk_gmac_ops rk3576_ops = {
.init = rk3576_init,
.set_to_rgmii = rk3576_set_to_rgmii,
- .set_to_rmii = rk3576_set_to_rmii,
.set_clock_selection = rk3576_set_clock_selection,
.gmac_rmii_mode_mask = BIT_U16(3),
@@ -987,6 +954,8 @@ static const struct rk_gmac_ops rk3576_ops = {
.clock.gmii_clk_sel_mask = GENMASK_U16(6, 5),
.clock.rmii_clk_sel_mask = BIT_U16(5),
+ .supports_rmii = true,
+
.php_grf_required = true,
.regs_valid = true,
.regs = {
@@ -1106,19 +1075,15 @@ static const struct rk_gmac_ops rk3588_ops = {
#define RV1108_GMAC_FLOW_CTRL GRF_BIT(3)
#define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
-static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
-}
-
static const struct rk_gmac_ops rv1108_ops = {
- .set_to_rmii = rv1108_set_to_rmii,
-
.gmac_grf_reg = RV1108_GRF_GMAC_CON0,
.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
.clock_grf_reg = RV1108_GRF_GMAC_CON0,
.clock.rmii_clk_sel_mask = BIT_U16(7),
.clock.mac_speed_mask = BIT_U16(2),
+
+ .supports_rmii = true,
};
#define RV1126_GRF_GMAC_CON0 0X0070
@@ -1162,17 +1127,14 @@ static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay));
}
-static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
-}
-
static const struct rk_gmac_ops rv1126_ops = {
.set_to_rgmii = rv1126_set_to_rgmii,
- .set_to_rmii = rv1126_set_to_rmii,
.set_speed = rk_set_clk_mac_speed,
.gmac_grf_reg = RV1126_GRF_GMAC_CON0,
.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
+
+ .supports_rmii = true,
};
static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH net-next 18/21] net: stmmac: rk: rk3328: gmac2phy only supports RMII
2026-01-23 10:59 [PATCH net-next 00/21] net: stmmac: rk: simplify per-SoC configuration Russell King (Oracle)
` (16 preceding siblings ...)
2026-01-23 11:01 ` [PATCH net-next 17/21] net: stmmac: rk: replace empty set_to_rmii() with supports_rmii Russell King (Oracle)
@ 2026-01-23 11:01 ` Russell King (Oracle)
2026-01-25 22:16 ` [net-next,18/21] " Jakub Kicinski
2026-01-23 11:01 ` [PATCH net-next 19/21] net: stmmac: rk: rk3528: gmac0 " Russell King (Oracle)
` (2 subsequent siblings)
20 siblings, 1 reply; 31+ messages in thread
From: Russell King (Oracle) @ 2026-01-23 11:01 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, netdev, Paolo Abeni
As detailed in a previous commit ("net: stmmac: rk: convert rk3328 to
use bsp_priv->id") rk3328 gmac2phy only supports RMII, whereas gmac2io
supports both RMII and RGMII. Clear supports_rgmii for gmac2phy.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 2d464ecb0e8f..109ed62fb04c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -452,6 +452,7 @@ static int rk3328_init(struct rk_priv_data *bsp_priv)
case 1: /* gmac2phy */
bsp_priv->gmac_grf_reg = RK3328_GRF_MAC_CON2;
bsp_priv->clock_grf_reg = RK3328_GRF_MAC_CON2;
+ bsp_priv->supports_rgmii = false;
return 0;
default:
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH net-next 19/21] net: stmmac: rk: rk3528: gmac0 only supports RMII
2026-01-23 10:59 [PATCH net-next 00/21] net: stmmac: rk: simplify per-SoC configuration Russell King (Oracle)
` (17 preceding siblings ...)
2026-01-23 11:01 ` [PATCH net-next 18/21] net: stmmac: rk: rk3328: gmac2phy only supports RMII Russell King (Oracle)
@ 2026-01-23 11:01 ` Russell King (Oracle)
2026-01-25 22:16 ` [net-next,19/21] " Jakub Kicinski
2026-01-23 11:02 ` [PATCH net-next 20/21] net: stmmac: rk: use rk_encode_wm16() for clock selection Russell King (Oracle)
2026-01-23 11:02 ` [PATCH net-next 21/21] net: stmmac: rk: rk3506, rk3528 and kk3588 have rmii_mode in clock register Russell King (Oracle)
20 siblings, 1 reply; 31+ messages in thread
From: Russell King (Oracle) @ 2026-01-23 11:01 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, netdev, Paolo Abeni
RK3528 gmac0 dtsi contains:
gmac0: ethernet@ffbd0000 {
phy-handle = <&rmii0_phy>;
phy-mode = "rmii";
mdio0: mdio {
rmii0_phy: ethernet-phy@2 {
phy-is-integrated;
};
};
};
This follows the same pattern as rk3328, where this gmac instance
only supports RMII. Disable RGMII in phylink's supported_interfaces
mask for this gmac instance.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 109ed62fb04c..d99e77211b95 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -715,6 +715,7 @@ static int rk3528_init(struct rk_priv_data *bsp_priv)
case 0:
bsp_priv->clock_grf_reg = RK3528_VO_GRF_GMAC_CON;
bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(3);
+ bsp_priv->supports_rgmii = false;
return 0;
case 1:
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH net-next 20/21] net: stmmac: rk: use rk_encode_wm16() for clock selection
2026-01-23 10:59 [PATCH net-next 00/21] net: stmmac: rk: simplify per-SoC configuration Russell King (Oracle)
` (18 preceding siblings ...)
2026-01-23 11:01 ` [PATCH net-next 19/21] net: stmmac: rk: rk3528: gmac0 " Russell King (Oracle)
@ 2026-01-23 11:02 ` Russell King (Oracle)
2026-01-25 22:16 ` [net-next,20/21] " Jakub Kicinski
2026-01-23 11:02 ` [PATCH net-next 21/21] net: stmmac: rk: rk3506, rk3528 and kk3588 have rmii_mode in clock register Russell King (Oracle)
20 siblings, 1 reply; 31+ messages in thread
From: Russell King (Oracle) @ 2026-01-23 11:02 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, netdev, Paolo Abeni
Use rk_encode_wm16() for RMII clock gating control, and also for the
io_clksel bit used to select the transmit clock between CRU-derived
and IO-derived clock sources.
Both of these were configured via the "set_clock_selection" method in
the SoC specific operations, but there is no requirement to change the
io_clksel except when enabling clocks.
It is also possible that we don't need to ungate the RMII clock if we
are operating in RGMII mode, but this commit makes no change there.
Split up the configuration of these as separate functions, and remove
the set_clock_selection() method. Since these clocking bits are in the
same register that we call the "speed" register, move the logic for
writing that register into rk_write_speed_grf_reg().
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 174 ++++++++----------
1 file changed, 75 insertions(+), 99 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index d99e77211b95..ebbc09ea572a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -27,8 +27,17 @@
struct rk_priv_data;
struct rk_clock_fields {
+ /* io_clksel_cru_mask - io_clksel bit in clock GRF register which,
+ * when set, selects the tx clock from CRU.
+ */
+ u16 io_clksel_cru_mask;
+ /* io_clksel_io_mask - io_clksel bit in clock GRF register which,
+ * when set, selects the tx clock from IO.
+ */
+ u16 io_clksel_io_mask;
u16 gmii_clk_sel_mask;
u16 rmii_clk_sel_mask;
+ u16 rmii_gate_en_mask;
u16 mac_speed_mask;
};
@@ -39,8 +48,6 @@ struct rk_gmac_ops {
void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
int (*set_speed)(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed);
- void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input,
- bool enable);
void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
void (*integrated_phy_powerdown)(struct rk_priv_data *bsp_priv);
@@ -158,6 +165,54 @@ static int rk_write_clock_grf_reg(struct rk_priv_data *bsp_priv, u32 val)
return regmap_write(regmap, bsp_priv->clock_grf_reg, val);
}
+static int rk_set_rmii_gate_en(struct rk_priv_data *bsp_priv, bool state)
+{
+ u32 val;
+
+ if (!bsp_priv->clock.rmii_gate_en_mask)
+ return 0;
+
+ val = rk_encode_wm16(state, bsp_priv->clock.rmii_gate_en_mask);
+
+ return rk_write_clock_grf_reg(bsp_priv, val);
+}
+
+static int rk_ungate_rmii_clock(struct rk_priv_data *bsp_priv)
+{
+ return rk_set_rmii_gate_en(bsp_priv, false);
+}
+
+static int rk_gate_rmii_clock(struct rk_priv_data *bsp_priv)
+{
+ return rk_set_rmii_gate_en(bsp_priv, true);
+}
+
+static int rk_configure_io_clksel(struct rk_priv_data *bsp_priv)
+{
+ bool io, cru;
+ u32 val;
+
+ if (!bsp_priv->clock.io_clksel_io_mask &&
+ !bsp_priv->clock.io_clksel_cru_mask)
+ return 0;
+
+ io = bsp_priv->clock_input;
+ cru = !io;
+
+ /* The io_clksel configuration can be either:
+ * 0=CRU, 1=IO (rk3506, rk3520, rk3576) or
+ * 0=IO, 1=CRU (rk3588)
+ * where CRU means the transmit clock comes from the CRU and IO
+ * means the transmit clock comes from IO.
+ *
+ * Handle this by having two masks.
+ */
+ val = rk_encode_wm16(io, bsp_priv->clock.io_clksel_io_mask) |
+ rk_encode_wm16(cru, bsp_priv->clock.io_clksel_cru_mask);
+
+ return rk_write_clock_grf_reg(bsp_priv, val);
+}
+
static int rk_set_clk_mac_speed(struct rk_priv_data *bsp_priv,
phy_interface_t interface, int speed)
{
@@ -624,12 +679,6 @@ static const struct rk_gmac_ops rk3399_ops = {
#define RK3506_GMAC_RMII_MODE GRF_BIT(1)
-#define RK3506_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(5)
-#define RK3506_GMAC_CLK_SELECT_IO GRF_BIT(5)
-
-#define RK3506_GMAC_CLK_RMII_GATE GRF_BIT(2)
-#define RK3506_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(2)
-
static int rk3506_init(struct rk_priv_data *bsp_priv)
{
switch (bsp_priv->id) {
@@ -654,26 +703,13 @@ static void rk3506_set_to_rmii(struct rk_priv_data *bsp_priv)
regmap_write(bsp_priv->grf, offset, RK3506_GMAC_RMII_MODE);
}
-static void rk3506_set_clock_selection(struct rk_priv_data *bsp_priv,
- bool input, bool enable)
-{
- unsigned int value, offset, id = bsp_priv->id;
-
- offset = (id == 1) ? RK3506_GRF_SOC_CON11 : RK3506_GRF_SOC_CON8;
-
- value = input ? RK3506_GMAC_CLK_SELECT_IO :
- RK3506_GMAC_CLK_SELECT_CRU;
- value |= enable ? RK3506_GMAC_CLK_RMII_NOGATE :
- RK3506_GMAC_CLK_RMII_GATE;
- regmap_write(bsp_priv->grf, offset, value);
-}
-
static const struct rk_gmac_ops rk3506_ops = {
.init = rk3506_init,
.set_to_rmii = rk3506_set_to_rmii,
- .set_clock_selection = rk3506_set_clock_selection,
+ .clock.io_clksel_io_mask = BIT_U16(5),
.clock.rmii_clk_sel_mask = BIT_U16(3),
+ .clock.rmii_gate_en_mask = BIT_U16(2),
.regs_valid = true,
.regs = {
@@ -701,27 +737,22 @@ static const struct rk_gmac_ops rk3506_ops = {
#define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8)
#define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8)
-#define RK3528_GMAC1_CLK_SELECT_CRU GRF_CLR_BIT(12)
-#define RK3528_GMAC1_CLK_SELECT_IO GRF_BIT(12)
-
-#define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2)
-#define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2)
-#define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9)
-#define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9)
-
static int rk3528_init(struct rk_priv_data *bsp_priv)
{
switch (bsp_priv->id) {
case 0:
bsp_priv->clock_grf_reg = RK3528_VO_GRF_GMAC_CON;
bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(3);
+ bsp_priv->clock.rmii_gate_en_mask = BIT_U16(2);
bsp_priv->supports_rgmii = false;
return 0;
case 1:
bsp_priv->clock_grf_reg = RK3528_VPU_GRF_GMAC_CON5;
+ bsp_priv->clock.io_clksel_io_mask = BIT_U16(12);
bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(11, 10);
bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(10);
+ bsp_priv->clock.rmii_gate_en_mask = BIT_U16(9);
return 0;
default:
@@ -753,24 +784,6 @@ static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)
RK3528_GMAC0_PHY_INTF_SEL_RMII);
}
-static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv,
- bool input, bool enable)
-{
- unsigned int val;
-
- if (bsp_priv->id == 1) {
- val = input ? RK3528_GMAC1_CLK_SELECT_IO :
- RK3528_GMAC1_CLK_SELECT_CRU;
- val |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE :
- RK3528_GMAC1_CLK_RMII_GATE;
- regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val);
- } else {
- val = enable ? RK3528_GMAC0_CLK_RMII_NOGATE :
- RK3528_GMAC0_CLK_RMII_GATE;
- regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, val);
- }
-}
-
static void rk3528_integrated_phy_powerup(struct rk_priv_data *bsp_priv)
{
rk_gmac_integrated_fephy_powerup(bsp_priv, RK3528_VO_GRF_MACPHY_CON0);
@@ -785,7 +798,6 @@ static const struct rk_gmac_ops rk3528_ops = {
.init = rk3528_init,
.set_to_rgmii = rk3528_set_to_rgmii,
.set_to_rmii = rk3528_set_to_rmii,
- .set_clock_selection = rk3528_set_clock_selection,
.integrated_phy_powerup = rk3528_integrated_phy_powerup,
.integrated_phy_powerdown = rk3528_integrated_phy_powerdown,
.regs_valid = true,
@@ -883,12 +895,6 @@ static const struct rk_gmac_ops rk3568_ops = {
#define RK3576_GRF_GMAC_CON0 0X0020
#define RK3576_GRF_GMAC_CON1 0X0024
-#define RK3576_GMAC_CLK_SELECT_IO GRF_BIT(7)
-#define RK3576_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(7)
-
-#define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4)
-#define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4)
-
static int rk3576_init(struct rk_priv_data *bsp_priv)
{
switch (bsp_priv->id) {
@@ -930,31 +936,16 @@ static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv,
RK3576_GMAC_CLK_RX_DL_CFG(rx_delay));
}
-static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
- bool enable)
-{
- unsigned int val = input ? RK3576_GMAC_CLK_SELECT_IO :
- RK3576_GMAC_CLK_SELECT_CRU;
- unsigned int offset_con;
-
- val |= enable ? RK3576_GMAC_CLK_RMII_NOGATE :
- RK3576_GMAC_CLK_RMII_GATE;
-
- offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
- RK3576_GRF_GMAC_CON0;
-
- regmap_write(bsp_priv->grf, offset_con, val);
-}
-
static const struct rk_gmac_ops rk3576_ops = {
.init = rk3576_init,
.set_to_rgmii = rk3576_set_to_rgmii,
- .set_clock_selection = rk3576_set_clock_selection,
.gmac_rmii_mode_mask = BIT_U16(3),
+ .clock.io_clksel_io_mask = BIT_U16(7),
.clock.gmii_clk_sel_mask = GENMASK_U16(6, 5),
.clock.rmii_clk_sel_mask = BIT_U16(5),
+ .clock.rmii_gate_en_mask = BIT_U16(4),
.supports_rmii = true,
@@ -987,25 +978,23 @@ static const struct rk_gmac_ops rk3576_ops = {
#define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id))
#define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id))
-#define RK3588_GMAC_CLK_SELECT_CRU(id) GRF_BIT(5 * (id) + 4)
-#define RK3588_GMAC_CLK_SELECT_IO(id) GRF_CLR_BIT(5 * (id) + 4)
-
-#define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1)
-#define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1)
-
static int rk3588_init(struct rk_priv_data *bsp_priv)
{
switch (bsp_priv->id) {
case 0:
bsp_priv->gmac_phy_intf_sel_mask = GENMASK_U16(5, 3);
+ bsp_priv->clock.io_clksel_cru_mask = BIT_U16(4);
bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(3, 2);
bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(2);
+ bsp_priv->clock.rmii_gate_en_mask = BIT_U16(1);
return 0;
case 1:
bsp_priv->gmac_phy_intf_sel_mask = GENMASK_U16(11, 9);
+ bsp_priv->clock.io_clksel_cru_mask = BIT_U16(10);
bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(8, 7);
bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(7);
+ bsp_priv->clock.rmii_gate_en_mask = BIT_U16(6);
return 0;
default:
@@ -1039,23 +1028,10 @@ static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id));
}
-static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
- bool enable)
-{
- unsigned int val = input ? RK3588_GMAC_CLK_SELECT_IO(bsp_priv->id) :
- RK3588_GMAC_CLK_SELECT_CRU(bsp_priv->id);
-
- val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->id) :
- RK3588_GMAC_CLK_RMII_GATE(bsp_priv->id);
-
- regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);
-}
-
static const struct rk_gmac_ops rk3588_ops = {
.init = rk3588_init,
.set_to_rgmii = rk3588_set_to_rgmii,
.set_to_rmii = rk3588_set_to_rmii,
- .set_clock_selection = rk3588_set_clock_selection,
.gmac_grf_reg = RK3588_GRF_GMAC_CON0,
@@ -1202,19 +1178,15 @@ static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
if (ret)
return ret;
- if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
- bsp_priv->ops->set_clock_selection(bsp_priv,
- bsp_priv->clock_input, true);
+ rk_configure_io_clksel(bsp_priv);
+ rk_ungate_rmii_clock(bsp_priv);
mdelay(5);
bsp_priv->clk_enabled = true;
}
} else {
if (bsp_priv->clk_enabled) {
- if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) {
- bsp_priv->ops->set_clock_selection(bsp_priv,
- bsp_priv->clock_input, false);
- }
+ rk_gate_rmii_clock(bsp_priv);
clk_bulk_disable_unprepare(bsp_priv->num_clks,
bsp_priv->clks);
@@ -1380,6 +1352,10 @@ static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
}
}
+ if (bsp_priv->clock.io_clksel_cru_mask &&
+ bsp_priv->clock.io_clksel_io_mask)
+ dev_warn(dev, "both CRU and IO io_clksel masks should not be populated - driver may malfunction\n");
+
return bsp_priv;
}
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH net-next 21/21] net: stmmac: rk: rk3506, rk3528 and kk3588 have rmii_mode in clock register
2026-01-23 10:59 [PATCH net-next 00/21] net: stmmac: rk: simplify per-SoC configuration Russell King (Oracle)
` (19 preceding siblings ...)
2026-01-23 11:02 ` [PATCH net-next 20/21] net: stmmac: rk: use rk_encode_wm16() for clock selection Russell King (Oracle)
@ 2026-01-23 11:02 ` Russell King (Oracle)
2026-01-25 22:16 ` [net-next,21/21] " Jakub Kicinski
20 siblings, 1 reply; 31+ messages in thread
From: Russell King (Oracle) @ 2026-01-23 11:02 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Heiko Stuebner, Jakub Kicinski, linux-arm-kernel, linux-rockchip,
linux-stm32, netdev, Paolo Abeni
rk3506, rk3528 and rk3588 have the rmii_mode bit in the clock GRF
register rather than the gmac GRF register. Provide a mask for this
field in the clock register, and convert these SoCs to use this.
Add the necessary code in rk_gmac_powerup() to write this field.
This allows us to get rid of these SoCs set_to_rmii() function. As
such, we need to mark these SoCs as supporting RMII mode.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 62 +++++++------------
1 file changed, 22 insertions(+), 40 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index ebbc09ea572a..759deb66ef2a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -38,6 +38,7 @@ struct rk_clock_fields {
u16 gmii_clk_sel_mask;
u16 rmii_clk_sel_mask;
u16 rmii_gate_en_mask;
+ u16 rmii_mode_mask;
u16 mac_speed_mask;
};
@@ -695,21 +696,15 @@ static int rk3506_init(struct rk_priv_data *bsp_priv)
}
}
-static void rk3506_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
- unsigned int id = bsp_priv->id, offset;
-
- offset = (id == 1) ? RK3506_GRF_SOC_CON11 : RK3506_GRF_SOC_CON8;
- regmap_write(bsp_priv->grf, offset, RK3506_GMAC_RMII_MODE);
-}
-
static const struct rk_gmac_ops rk3506_ops = {
.init = rk3506_init,
- .set_to_rmii = rk3506_set_to_rmii,
.clock.io_clksel_io_mask = BIT_U16(5),
.clock.rmii_clk_sel_mask = BIT_U16(3),
.clock.rmii_gate_en_mask = BIT_U16(2),
+ .clock.rmii_mode_mask = BIT_U16(1),
+
+ .supports_rmii = true,
.regs_valid = true,
.regs = {
@@ -733,10 +728,6 @@ static const struct rk_gmac_ops rk3506_ops = {
#define RK3528_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(15, 8, val)
#define RK3528_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(7, 0, val)
-#define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1)
-#define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8)
-#define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8)
-
static int rk3528_init(struct rk_priv_data *bsp_priv)
{
switch (bsp_priv->id) {
@@ -744,6 +735,7 @@ static int rk3528_init(struct rk_priv_data *bsp_priv)
bsp_priv->clock_grf_reg = RK3528_VO_GRF_GMAC_CON;
bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(3);
bsp_priv->clock.rmii_gate_en_mask = BIT_U16(2);
+ bsp_priv->clock.rmii_mode_mask = BIT_U16(1);
bsp_priv->supports_rgmii = false;
return 0;
@@ -753,6 +745,7 @@ static int rk3528_init(struct rk_priv_data *bsp_priv)
bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(11, 10);
bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(10);
bsp_priv->clock.rmii_gate_en_mask = BIT_U16(9);
+ bsp_priv->clock.rmii_mode_mask = BIT_U16(8);
return 0;
default:
@@ -763,9 +756,6 @@ static int rk3528_init(struct rk_priv_data *bsp_priv)
static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
- regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
- RK3528_GMAC1_PHY_INTF_SEL_RGMII);
-
regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
DELAY_ENABLE(RK3528, tx_delay, rx_delay));
@@ -774,16 +764,6 @@ static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,
RK3528_GMAC_CLK_TX_DL_CFG(tx_delay));
}
-static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
- if (bsp_priv->id == 1)
- regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
- RK3528_GMAC1_PHY_INTF_SEL_RMII);
- else
- regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON,
- RK3528_GMAC0_PHY_INTF_SEL_RMII);
-}
-
static void rk3528_integrated_phy_powerup(struct rk_priv_data *bsp_priv)
{
rk_gmac_integrated_fephy_powerup(bsp_priv, RK3528_VO_GRF_MACPHY_CON0);
@@ -797,9 +777,11 @@ static void rk3528_integrated_phy_powerdown(struct rk_priv_data *bsp_priv)
static const struct rk_gmac_ops rk3528_ops = {
.init = rk3528_init,
.set_to_rgmii = rk3528_set_to_rgmii,
- .set_to_rmii = rk3528_set_to_rmii,
.integrated_phy_powerup = rk3528_integrated_phy_powerup,
.integrated_phy_powerdown = rk3528_integrated_phy_powerdown,
+
+ .supports_rmii = true,
+
.regs_valid = true,
.regs = {
0xffbd0000, /* gmac0 */
@@ -975,9 +957,6 @@ static const struct rk_gmac_ops rk3576_ops = {
#define RK3588_GRF_GMAC_CON0 0X0008
#define RK3588_GRF_CLK_CON1 0X0070
-#define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id))
-#define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id))
-
static int rk3588_init(struct rk_priv_data *bsp_priv)
{
switch (bsp_priv->id) {
@@ -987,6 +966,7 @@ static int rk3588_init(struct rk_priv_data *bsp_priv)
bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(3, 2);
bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(2);
bsp_priv->clock.rmii_gate_en_mask = BIT_U16(1);
+ bsp_priv->clock.rmii_mode_mask = BIT_U16(0);
return 0;
case 1:
@@ -995,6 +975,7 @@ static int rk3588_init(struct rk_priv_data *bsp_priv)
bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(8, 7);
bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(7);
bsp_priv->clock.rmii_gate_en_mask = BIT_U16(6);
+ bsp_priv->clock.rmii_mode_mask = BIT_U16(5);
return 0;
default:
@@ -1010,9 +991,6 @@ static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 :
RK3588_GRF_GMAC_CON8;
- regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
- RK3588_GMAC_CLK_RGMII_MODE(id));
-
regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7,
RK3588_GMAC_RXCLK_DLY_ENABLE(id) |
RK3588_GMAC_TXCLK_DLY_ENABLE(id));
@@ -1022,22 +1000,17 @@ static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
RK3588_GMAC_CLK_TX_DL_CFG(tx_delay));
}
-static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
-{
- regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
- RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id));
-}
-
static const struct rk_gmac_ops rk3588_ops = {
.init = rk3588_init,
.set_to_rgmii = rk3588_set_to_rgmii,
- .set_to_rmii = rk3588_set_to_rmii,
.gmac_grf_reg = RK3588_GRF_GMAC_CON0,
.clock_grf_reg_in_php = true,
.clock_grf_reg = RK3588_GRF_CLK_CON1,
+ .supports_rmii = true,
+
.php_grf_required = true,
.regs_valid = true,
.regs = {
@@ -1412,6 +1385,15 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
return ret;
}
+ if (bsp_priv->clock.rmii_mode_mask) {
+ val = rk_encode_wm16(ret == PHY_INTF_SEL_RMII,
+ bsp_priv->clock.rmii_mode_mask);
+
+ ret = rk_write_clock_grf_reg(bsp_priv, val);
+ if (ret < 0)
+ return ret;
+ }
+
/*rmii or rgmii*/
switch (bsp_priv->phy_iface) {
case PHY_INTERFACE_MODE_RGMII:
--
2.47.3
^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [net-next,03/21] net: stmmac: rk: convert rk3328 to use bsp_priv->id
2026-01-23 11:00 ` [PATCH net-next 03/21] net: stmmac: rk: convert rk3328 to use bsp_priv->id Russell King (Oracle)
@ 2026-01-25 22:16 ` Jakub Kicinski
0 siblings, 0 replies; 31+ messages in thread
From: Jakub Kicinski @ 2026-01-25 22:16 UTC (permalink / raw)
To: rmk+kernel
Cc: Jakub Kicinski, linux-arm-kernel, andrew, davem, alexandre.torgue,
netdev, edumazet, pabeni, heiko, andrew+netdev, linux-rockchip,
linux-stm32
This is an AI-generated review of your patch. The human sending this
email has considered the AI review valid, or at least plausible.
For local reproduction steps see https://netdev-ai.bots.linux.dev/ai-local.html
---
net: stmmac: rk: convert to mask-based interface mode configuration
This commit converts many Rockchip GMAC implementations to use a new
centralized mask-based infrastructure for configuring PHY interface
mode. The PHY_INTF_SEL and RMII mode configuration is moved from
individual set_to_rgmii()/set_to_rmii() functions to rk_gmac_powerup().
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> index 4117f6863ff0..48fc5b58092f 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
[ ... ]
> @@ -1198,9 +1225,6 @@ static const struct rk_gmac_ops rk3576_ops = {
> #define RK3588_GRF_GMAC_CON0 0X0008
> #define RK3588_GRF_CLK_CON1 0X0070
The comment above this definition says "/* php_grf */" indicating that
RK3588_GRF_GMAC_CON0 is in the php_grf address space.
> -#define RK3588_GMAC_PHY_INTF_SEL(id, val) \
> - (GRF_FIELD(5, 3, val) << ((id) * 6))
> -
[ ... ]
> +static int rk3588_init(struct rk_priv_data *bsp_priv)
> +{
> + switch (bsp_priv->id) {
> + case 0:
> + bsp_priv->gmac_phy_intf_sel_mask = GENMASK_U16(5, 3);
> + return 0;
> +
> + case 1:
> + bsp_priv->gmac_phy_intf_sel_mask = GENMASK_U16(11, 9);
> + return 0;
> +
> + default:
> + return -EINVAL;
> + }
> +}
[ ... ]
> static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
> int tx_delay, int rx_delay)
> {
> u32 offset_con, id = bsp_priv->id;
>
> offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 :
> RK3588_GRF_GMAC_CON8;
>
> - regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
> - RK3588_GMAC_PHY_INTF_SEL(id, PHY_INTF_SEL_RGMII));
This removed code wrote to php_grf, but the new centralized code in
rk_gmac_powerup() writes to grf instead. Is this intentional?
[ ... ]
> static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
> {
> - regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
> - RK3588_GMAC_PHY_INTF_SEL(bsp_priv->id, PHY_INTF_SEL_RMII));
Same here - the original wrote to php_grf.
[ ... ]
> static const struct rk_gmac_ops rk3588_ops = {
> + .init = rk3588_init,
> .set_to_rgmii = rk3588_set_to_rgmii,
> .set_to_rmii = rk3588_set_to_rmii,
> .set_speed = rk3588_set_gmac_speed,
> .set_clock_selection = rk3588_set_clock_selection,
> +
> + .gmac_grf_reg = RK3588_GRF_GMAC_CON0,
This sets gmac_grf_reg to RK3588_GRF_GMAC_CON0, which is then used by
rk_gmac_powerup() to write to bsp_priv->grf.
[ ... ]
> @@ -1654,6 +1696,7 @@ static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv)
> static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
> {
> struct device *dev = bsp_priv->dev;
> + u32 val;
> int ret;
[ ... ]
> + if (bsp_priv->gmac_phy_intf_sel_mask ||
> + bsp_priv->gmac_rmii_mode_mask) {
> + /* If defined, encode the phy_intf_sel value */
> + val = rk_encode_wm16(ret, bsp_priv->gmac_phy_intf_sel_mask);
> +
> + /* If defined, encode the RMII mode mask setting. */
> + val |= rk_encode_wm16(ret == PHY_INTF_SEL_RMII,
> + bsp_priv->gmac_rmii_mode_mask);
> +
> + ret = regmap_write(bsp_priv->grf, bsp_priv->gmac_grf_reg, val);
^^^^^^^^^^^^
For RK3588, this writes to bsp_priv->grf at offset RK3588_GRF_GMAC_CON0
(0x0008). However, the original code wrote to bsp_priv->php_grf at the
same offset. These are different regmaps obtained from different device
tree phandles (rockchip,grf vs rockchip,php-grf).
Does RK3588 need a mechanism to write the PHY_INTF_SEL to php_grf rather
than grf? The clock register already has clock_grf_reg_in_php support
to select which regmap to use, but there does not appear to be a similar
mechanism for gmac_grf_reg.
--
pw-bot: cr
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [net-next,07/21] net: stmmac: rk: convert to mask-based interface mode configuration
2026-01-23 11:00 ` [PATCH net-next 07/21] net: stmmac: rk: convert to mask-based interface mode configuration Russell King (Oracle)
@ 2026-01-25 22:16 ` Jakub Kicinski
0 siblings, 0 replies; 31+ messages in thread
From: Jakub Kicinski @ 2026-01-25 22:16 UTC (permalink / raw)
To: rmk+kernel
Cc: Jakub Kicinski, linux-arm-kernel, andrew, davem, alexandre.torgue,
netdev, edumazet, pabeni, heiko, andrew+netdev, linux-rockchip,
linux-stm32
This is an AI-generated review of your patch. The human sending this
email has considered the AI review valid, or at least plausible.
For local reproduction steps see https://netdev-ai.bots.linux.dev/ai-local.html
---
net: stmmac: rk: convert to mask-based interface mode configuration
This patch consolidates PHY interface mode configuration into a common
infrastructure. It introduces mask fields for phy_intf_sel and rmii_mode,
and moves the register writes from SoC-specific set_to_rgmii/set_to_rmii
functions into the common rk_gmac_powerup() function.
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> index 4117f6863ff0..48fc5b58092f 100644
[ ... ]
> @@ -1198,9 +1225,6 @@ static const struct rk_gmac_ops rk3576_ops = {
> #define RK3588_GRF_GMAC_CON0 0X0008
> #define RK3588_GRF_CLK_CON1 0X0070
The comment above these defines says "/* php_grf */" indicating that
RK3588_GRF_GMAC_CON0 is in the php_grf register space.
[ ... ]
> +static int rk3588_init(struct rk_priv_data *bsp_priv)
> +{
> + switch (bsp_priv->id) {
> + case 0:
> + bsp_priv->gmac_phy_intf_sel_mask = GENMASK_U16(5, 3);
> + return 0;
> +
> + case 1:
> + bsp_priv->gmac_phy_intf_sel_mask = GENMASK_U16(11, 9);
> + return 0;
> +
> + default:
> + return -EINVAL;
> + }
> +}
[ ... ]
> @@ -1296,10 +1330,14 @@ static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input
> }
>
> static const struct rk_gmac_ops rk3588_ops = {
> + .init = rk3588_init,
> .set_to_rgmii = rk3588_set_to_rgmii,
> .set_to_rmii = rk3588_set_to_rmii,
> .set_speed = rk3588_set_gmac_speed,
> .set_clock_selection = rk3588_set_clock_selection,
> +
> + .gmac_grf_reg = RK3588_GRF_GMAC_CON0,
rk3588_ops sets gmac_grf_reg to RK3588_GRF_GMAC_CON0, and rk3588_init()
sets gmac_phy_intf_sel_mask. This enables the new common code path in
rk_gmac_powerup().
[ ... ]
> @@ -1664,6 +1707,24 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
> if (ret)
> return ret;
>
> + ret = rk_get_phy_intf_sel(bsp_priv->phy_iface);
> + if (ret < 0)
> + return ret;
> +
> + if (bsp_priv->gmac_phy_intf_sel_mask ||
> + bsp_priv->gmac_rmii_mode_mask) {
> + /* If defined, encode the phy_intf_sel value */
> + val = rk_encode_wm16(ret, bsp_priv->gmac_phy_intf_sel_mask);
> +
> + /* If defined, encode the RMII mode mask setting. */
> + val |= rk_encode_wm16(ret == PHY_INTF_SEL_RMII,
> + bsp_priv->gmac_rmii_mode_mask);
> +
> + ret = regmap_write(bsp_priv->grf, bsp_priv->gmac_grf_reg, val);
^^^^
For rk3588, does this write to the wrong regmap? The old code in
rk3588_set_to_rgmii() and rk3588_set_to_rmii() wrote the PHY_INTF_SEL
register to bsp_priv->php_grf:
regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
RK3588_GMAC_PHY_INTF_SEL(id, PHY_INTF_SEL_RGMII));
But the new common code writes to bsp_priv->grf instead. The comment in
the source indicates RK3588_GRF_GMAC_CON0 is in the php_grf register
space. Should this be using php_grf for rk3588?
> + if (ret < 0)
> + return ret;
> + }
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [net-next,17/21] net: stmmac: rk: replace empty set_to_rmii() with supports_rmii
2026-01-23 11:01 ` [PATCH net-next 17/21] net: stmmac: rk: replace empty set_to_rmii() with supports_rmii Russell King (Oracle)
@ 2026-01-25 22:16 ` Jakub Kicinski
0 siblings, 0 replies; 31+ messages in thread
From: Jakub Kicinski @ 2026-01-25 22:16 UTC (permalink / raw)
To: rmk+kernel
Cc: Jakub Kicinski, linux-arm-kernel, andrew, davem, alexandre.torgue,
netdev, edumazet, pabeni, heiko, andrew+netdev, linux-rockchip,
linux-stm32
This is an AI-generated review of your patch. The human sending this
email has considered the AI review valid, or at least plausible.
For local reproduction steps see https://netdev-ai.bots.linux.dev/ai-local.html
---
net: stmmac: rk: rk3506, rk3528 and kk3588 have rmii_mode in clock register
This patch consolidates RMII mode configuration for rk3506, rk3528, and
rk3588 by moving the rmii_mode bit writes from per-SoC set_to_rmii()
functions into a centralized block in rk_gmac_powerup().
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> index ebbc09ea572a..759deb66ef2a 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
[ ... ]
> @@ -1412,6 +1385,15 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
> return ret;
> }
The context above this hunk is relevant. Earlier in rk_gmac_powerup():
ret = rk_get_phy_intf_sel(bsp_priv->phy_iface);
...
if (bsp_priv->gmac_phy_intf_sel_mask ||
bsp_priv->gmac_rmii_mode_mask) {
...
ret = regmap_write(bsp_priv->grf, bsp_priv->gmac_grf_reg, val);
...
}
At this point, if the first if-block executed, ret has been overwritten by
regmap_write() and will be 0 on success.
> + if (bsp_priv->clock.rmii_mode_mask) {
> + val = rk_encode_wm16(ret == PHY_INTF_SEL_RMII,
> + bsp_priv->clock.rmii_mode_mask);
For RK3588, both gmac_phy_intf_sel_mask and clock.rmii_mode_mask are set.
The first if-block will execute and overwrite ret with the regmap_write()
return value (0 on success).
When this second if-block runs, ret will be 0 rather than the original
PHY_INTF_SEL_RMII value (which is 4). This means ret == PHY_INTF_SEL_RMII
will always evaluate to false for RK3588, causing the rmii_mode bit to be
cleared instead of set when RMII mode is configured.
Should ret be saved before the first if-block and restored here, or should
a separate variable hold the phy interface selection?
> +
> + ret = rk_write_clock_grf_reg(bsp_priv, val);
> + if (ret < 0)
> + return ret;
> + }
[ ... ]
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [net-next,18/21] net: stmmac: rk: rk3328: gmac2phy only supports RMII
2026-01-23 11:01 ` [PATCH net-next 18/21] net: stmmac: rk: rk3328: gmac2phy only supports RMII Russell King (Oracle)
@ 2026-01-25 22:16 ` Jakub Kicinski
2026-01-25 22:27 ` Russell King (Oracle)
0 siblings, 1 reply; 31+ messages in thread
From: Jakub Kicinski @ 2026-01-25 22:16 UTC (permalink / raw)
To: rmk+kernel
Cc: Jakub Kicinski, linux-arm-kernel, andrew, davem, alexandre.torgue,
netdev, edumazet, pabeni, heiko, andrew+netdev, linux-rockchip,
linux-stm32
This is an AI-generated review of your patch. The human sending this
email has considered the AI review valid, or at least plausible.
For local reproduction steps see https://netdev-ai.bots.linux.dev/ai-local.html
---
net: stmmac: rk: rk3506, rk3528 and kk3588 have rmii_mode in clock register
This commit consolidates RMII mode configuration for rk3506, rk3528, and
rk3588 by adding a rmii_mode_mask field to rk_clock_fields, removing the
per-SoC set_to_rmii() functions, and adding common code in rk_gmac_powerup()
to write this field.
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> index ebbc09ea572a..759deb66ef2a 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
[ ... ]
> @@ -1412,6 +1385,15 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
> return ret;
> }
The code above (not shown in the diff, but present in the function) is:
ret = rk_get_phy_intf_sel(bsp_priv->phy_iface);
...
if (bsp_priv->gmac_phy_intf_sel_mask ||
bsp_priv->gmac_rmii_mode_mask) {
...
ret = regmap_write(bsp_priv->grf, bsp_priv->gmac_grf_reg, val);
if (ret < 0)
return ret;
}
At this point, if the block above executed, ret holds the return value from
regmap_write() (0 on success), not the interface selector.
> + if (bsp_priv->clock.rmii_mode_mask) {
> + val = rk_encode_wm16(ret == PHY_INTF_SEL_RMII,
> + bsp_priv->clock.rmii_mode_mask);
For rk3588, both gmac_phy_intf_sel_mask and clock.rmii_mode_mask are set in
rk3588_init(). When the preceding block executes, it overwrites ret with
the regmap_write() return value. Then here, ret == PHY_INTF_SEL_RMII
compares 0 == 4 which is always false, so the rmii_mode bit will never be
set for rk3588 in RMII mode.
Should ret be saved before the preceding block so its original value
(the interface selector) can be used here?
> +
> + ret = rk_write_clock_grf_reg(bsp_priv, val);
> + if (ret < 0)
> + return ret;
> + }
[ ... ]
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [net-next,19/21] net: stmmac: rk: rk3528: gmac0 only supports RMII
2026-01-23 11:01 ` [PATCH net-next 19/21] net: stmmac: rk: rk3528: gmac0 " Russell King (Oracle)
@ 2026-01-25 22:16 ` Jakub Kicinski
0 siblings, 0 replies; 31+ messages in thread
From: Jakub Kicinski @ 2026-01-25 22:16 UTC (permalink / raw)
To: rmk+kernel
Cc: Jakub Kicinski, linux-arm-kernel, andrew, davem, alexandre.torgue,
netdev, edumazet, pabeni, heiko, andrew+netdev, linux-rockchip,
linux-stm32
This is an AI-generated review of your patch. The human sending this
email has considered the AI review valid, or at least plausible.
For local reproduction steps see https://netdev-ai.bots.linux.dev/ai-local.html
---
net: stmmac: rk: rk3506, rk3528 and kk3588 have rmii_mode in clock register
This commit moves the rmii_mode configuration for rk3506, rk3528, and
rk3588 from the per-SoC set_to_rmii() functions into the centralized
rk_gmac_powerup() function, using a new clock.rmii_mode_mask field.
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> index ebbc09ea572a..759deb66ef2a 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
[ ... ]
> @@ -987,6 +966,7 @@ static int rk3588_init(struct rk_priv_data *bsp_priv)
> bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(3, 2);
> bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(2);
> bsp_priv->clock.rmii_gate_en_mask = BIT_U16(1);
> + bsp_priv->clock.rmii_mode_mask = BIT_U16(0);
> return 0;
[ ... ]
> @@ -1412,6 +1385,15 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
> return ret;
> }
>
> + if (bsp_priv->clock.rmii_mode_mask) {
> + val = rk_encode_wm16(ret == PHY_INTF_SEL_RMII,
> + bsp_priv->clock.rmii_mode_mask);
For rk3588, the variable ret has been overwritten by the preceding
regmap_write() in the gmac_phy_intf_sel_mask block. At this point ret
contains 0 (success) rather than PHY_INTF_SEL_RMII (4).
Looking at rk_gmac_powerup(), the flow for rk3588 is:
ret = rk_get_phy_intf_sel(bsp_priv->phy_iface); // ret = 4 for RMII
...
if (bsp_priv->gmac_phy_intf_sel_mask || ...) // true for rk3588
...
ret = regmap_write(...); // ret = 0 on success
...
if (bsp_priv->clock.rmii_mode_mask) // true for rk3588
val = rk_encode_wm16(ret == PHY_INTF_SEL_RMII, ...); // 0 == 4 is false
Since rk3588_init() sets both gmac_phy_intf_sel_mask and
clock.rmii_mode_mask, does this mean RMII mode can never be correctly
configured for rk3588?
> +
> + ret = rk_write_clock_grf_reg(bsp_priv, val);
> + if (ret < 0)
> + return ret;
> + }
[ ... ]
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [net-next,20/21] net: stmmac: rk: use rk_encode_wm16() for clock selection
2026-01-23 11:02 ` [PATCH net-next 20/21] net: stmmac: rk: use rk_encode_wm16() for clock selection Russell King (Oracle)
@ 2026-01-25 22:16 ` Jakub Kicinski
0 siblings, 0 replies; 31+ messages in thread
From: Jakub Kicinski @ 2026-01-25 22:16 UTC (permalink / raw)
To: rmk+kernel
Cc: Jakub Kicinski, linux-arm-kernel, andrew, davem, alexandre.torgue,
netdev, edumazet, pabeni, heiko, andrew+netdev, linux-rockchip,
linux-stm32
This is an AI-generated review of your patch. The human sending this
email has considered the AI review valid, or at least plausible.
For local reproduction steps see https://netdev-ai.bots.linux.dev/ai-local.html
---
net: stmmac: rk: rk3506, rk3528 and kk3588 have rmii_mode in clock register
This patch adds an rmii_mode_mask field to struct rk_clock_fields to handle
RMII mode configuration in the clock GRF register. It removes the SoC-specific
set_to_rmii() functions for rk3506, rk3528, and rk3588, replacing them with a
generic mechanism in rk_gmac_powerup().
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> index ebbc09ea572a..759deb66ef2a 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
[ ... ]
> @@ -1412,6 +1385,15 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
> return ret;
> }
>
> + if (bsp_priv->clock.rmii_mode_mask) {
> + val = rk_encode_wm16(ret == PHY_INTF_SEL_RMII,
> + bsp_priv->clock.rmii_mode_mask);
Is this comparison using the correct value? Earlier in rk_gmac_powerup(), the
variable ret is assigned the return value from rk_get_phy_intf_sel(), which is
PHY_INTF_SEL_RGMII (0) or PHY_INTF_SEL_RMII (1).
However, for SoCs that have gmac_phy_intf_sel_mask set (such as rk3588), the
code enters the preceding if block:
if (bsp_priv->gmac_phy_intf_sel_mask || bsp_priv->gmac_rmii_mode_mask) {
...
ret = regmap_write(bsp_priv->grf, bsp_priv->gmac_grf_reg, val);
...
}
After this block, ret has been overwritten with the regmap_write() return
value (0 on success). When the rmii_mode_mask block executes, the comparison
ret == PHY_INTF_SEL_RMII becomes 0 == 1, which is always false.
This means for rk3588 in RMII mode, the rmii_mode bit in the clock register
will be cleared (RGMII mode) instead of set. Would it be better to save the
PHY interface selection value in a separate variable before it gets
overwritten?
> +
> + ret = rk_write_clock_grf_reg(bsp_priv, val);
> + if (ret < 0)
> + return ret;
> + }
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [net-next,21/21] net: stmmac: rk: rk3506, rk3528 and kk3588 have rmii_mode in clock register
2026-01-23 11:02 ` [PATCH net-next 21/21] net: stmmac: rk: rk3506, rk3528 and kk3588 have rmii_mode in clock register Russell King (Oracle)
@ 2026-01-25 22:16 ` Jakub Kicinski
0 siblings, 0 replies; 31+ messages in thread
From: Jakub Kicinski @ 2026-01-25 22:16 UTC (permalink / raw)
To: rmk+kernel
Cc: Jakub Kicinski, linux-arm-kernel, andrew, davem, alexandre.torgue,
netdev, edumazet, pabeni, heiko, andrew+netdev, linux-rockchip,
linux-stm32
This is an AI-generated review of your patch. The human sending this
email has considered the AI review valid, or at least plausible.
For local reproduction steps see https://netdev-ai.bots.linux.dev/ai-local.html
---
net: stmmac: rk: rk3506, rk3528 and kk3588 have rmii_mode in clock register
This commit moves the RMII mode bit configuration from the dedicated
set_to_rmii() functions to rk_gmac_powerup() using a new rmii_mode_mask
field in the clock register structure.
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> index ebbc09ea572a..759deb66ef2a 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
[ ... ]
> @@ -1412,6 +1385,15 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
> return ret;
> }
For context, prior to this hunk, ret is set by rk_get_phy_intf_sel() to
hold the PHY interface value (e.g., PHY_INTF_SEL_RMII = 4). Then in the
block above (not shown here), if gmac_phy_intf_sel_mask is set, there is:
ret = regmap_write(bsp_priv->grf, bsp_priv->gmac_grf_reg, val);
This overwrites ret with the regmap_write() return value (0 on success).
> + if (bsp_priv->clock.rmii_mode_mask) {
> + val = rk_encode_wm16(ret == PHY_INTF_SEL_RMII,
> + bsp_priv->clock.rmii_mode_mask);
For rk3588, gmac_phy_intf_sel_mask is set in rk3588_init(), so the
previous block executes and ret becomes 0. Then here, the comparison
ret == PHY_INTF_SEL_RMII evaluates to 0 == 4, which is always false.
This means the RMII mode bit will never be set for rk3588 in RMII mode.
Should this use bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII instead,
or should the PHY interface value be saved to a separate variable before
it gets overwritten?
> +
> + ret = rk_write_clock_grf_reg(bsp_priv, val);
> + if (ret < 0)
> + return ret;
> + }
[ ... ]
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [net-next,18/21] net: stmmac: rk: rk3328: gmac2phy only supports RMII
2026-01-25 22:16 ` [net-next,18/21] " Jakub Kicinski
@ 2026-01-25 22:27 ` Russell King (Oracle)
2026-01-25 23:04 ` Jakub Kicinski
0 siblings, 1 reply; 31+ messages in thread
From: Russell King (Oracle) @ 2026-01-25 22:27 UTC (permalink / raw)
To: Jakub Kicinski
Cc: linux-arm-kernel, andrew, davem, alexandre.torgue, netdev,
edumazet, pabeni, heiko, andrew+netdev, linux-rockchip,
linux-stm32
On Sun, Jan 25, 2026 at 02:16:31PM -0800, Jakub Kicinski wrote:
> This is an AI-generated review of your patch. The human sending this
> email has considered the AI review valid, or at least plausible.
>
> For local reproduction steps see https://netdev-ai.bots.linux.dev/ai-local.html
This, and all the other AI generated comments on subsequent patches
are repeats of patch 17.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [net-next,18/21] net: stmmac: rk: rk3328: gmac2phy only supports RMII
2026-01-25 22:27 ` Russell King (Oracle)
@ 2026-01-25 23:04 ` Jakub Kicinski
0 siblings, 0 replies; 31+ messages in thread
From: Jakub Kicinski @ 2026-01-25 23:04 UTC (permalink / raw)
To: Russell King (Oracle)
Cc: linux-arm-kernel, andrew, davem, alexandre.torgue, netdev,
edumazet, pabeni, heiko, andrew+netdev, linux-rockchip,
linux-stm32
On Sun, 25 Jan 2026 22:27:50 +0000 Russell King (Oracle) wrote:
> On Sun, Jan 25, 2026 at 02:16:31PM -0800, Jakub Kicinski wrote:
> > This is an AI-generated review of your patch. The human sending this
> > email has considered the AI review valid, or at least plausible.
> >
> > For local reproduction steps see https://netdev-ai.bots.linux.dev/ai-local.html
>
> This, and all the other AI generated comments on subsequent patches
> are repeats of patch 17.
#$%&, should have checked. Sorry.
^ permalink raw reply [flat|nested] 31+ messages in thread
end of thread, other threads:[~2026-01-25 23:04 UTC | newest]
Thread overview: 31+ messages (download: mbox.gz follow: Atom feed
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2026-01-23 10:59 [PATCH net-next 00/21] net: stmmac: rk: simplify per-SoC configuration Russell King (Oracle)
2026-01-23 11:00 ` [PATCH net-next 01/21] net: stmmac: rk: avoid phy_power_on() Russell King (Oracle)
2026-01-23 11:00 ` [PATCH net-next 02/21] net: stmmac: rk: get rid of rk_phy_power_ctl() Russell King (Oracle)
2026-01-23 11:00 ` [PATCH net-next 03/21] net: stmmac: rk: convert rk3328 to use bsp_priv->id Russell King (Oracle)
2026-01-25 22:16 ` [net-next,03/21] " Jakub Kicinski
2026-01-23 11:00 ` [PATCH net-next 04/21] net: stmmac: rk: group MACPHY register offset and fields together Russell King (Oracle)
2026-01-23 11:00 ` [PATCH net-next 05/21] net: stmmac: rk: add GMAC_CLK_xx constants, simplify RGMII definitions Russell King (Oracle)
2026-01-23 11:00 ` [PATCH net-next 06/21] net: stmmac: rk: add SoC specific ->init() method Russell King (Oracle)
2026-01-23 11:00 ` [PATCH net-next 07/21] net: stmmac: rk: convert to mask-based interface mode configuration Russell King (Oracle)
2026-01-25 22:16 ` [net-next,07/21] " Jakub Kicinski
2026-01-23 11:00 ` [PATCH net-next 08/21] net: stmmac: rk: move speed GRF register offset to private data Russell King (Oracle)
2026-01-23 11:01 ` [PATCH net-next 09/21] net: stmmac: rk: convert rk3588 to rk_set_reg_speed() Russell King (Oracle)
2026-01-23 11:01 ` [PATCH net-next 10/21] net: stmmac: rk: remove rk3528 RMII clock initialisation Russell King (Oracle)
2026-01-23 11:01 ` [PATCH net-next 11/21] net: stmmac: rk: use rk_encode_wm16() for RGMII clocks Russell King (Oracle)
2026-01-23 11:01 ` [PATCH net-next 12/21] net: stmmac: rk: use rk_encode_wm16() for RMII speed Russell King (Oracle)
2026-01-23 11:01 ` [PATCH net-next 13/21] net: stmmac: rk: use rk_encode_wm16() for RMII clock Russell King (Oracle)
2026-01-23 11:01 ` [PATCH net-next 14/21] net: stmmac: rk: remove need for ->set_speed() method Russell King (Oracle)
2026-01-23 11:01 ` [PATCH net-next 15/21] net: stmmac: rk: convert px30 Russell King (Oracle)
2026-01-23 11:01 ` [PATCH net-next 16/21] net: stmmac: rk: introduce flags indicating support for RGMII/RMII Russell King (Oracle)
2026-01-23 11:01 ` [PATCH net-next 17/21] net: stmmac: rk: replace empty set_to_rmii() with supports_rmii Russell King (Oracle)
2026-01-25 22:16 ` [net-next,17/21] " Jakub Kicinski
2026-01-23 11:01 ` [PATCH net-next 18/21] net: stmmac: rk: rk3328: gmac2phy only supports RMII Russell King (Oracle)
2026-01-25 22:16 ` [net-next,18/21] " Jakub Kicinski
2026-01-25 22:27 ` Russell King (Oracle)
2026-01-25 23:04 ` Jakub Kicinski
2026-01-23 11:01 ` [PATCH net-next 19/21] net: stmmac: rk: rk3528: gmac0 " Russell King (Oracle)
2026-01-25 22:16 ` [net-next,19/21] " Jakub Kicinski
2026-01-23 11:02 ` [PATCH net-next 20/21] net: stmmac: rk: use rk_encode_wm16() for clock selection Russell King (Oracle)
2026-01-25 22:16 ` [net-next,20/21] " Jakub Kicinski
2026-01-23 11:02 ` [PATCH net-next 21/21] net: stmmac: rk: rk3506, rk3528 and kk3588 have rmii_mode in clock register Russell King (Oracle)
2026-01-25 22:16 ` [net-next,21/21] " Jakub Kicinski
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