[PATCH net-next 0/2] extend bit width in the flow director of HNS3 driver

[PATCH net-next 0/2] extend bit width in the flow director of HNS3 driver

[Jijie Shao]

The bit widths of HCLGE_FD_AD_QID and HCLGE_FD_AD_COUNTER_NUM are
increased to support higher specifications.

Note: The hardware already supports the specifications.

Jijie Shao (2):
  net: hns3: extend HCLGE_FD_AD_QID to 11 bits
  net: hns3: extend HCLGE_FD_AD_COUNTER_NUM to 8 bits

 .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h    | 11 +++++++----
 .../net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c   | 11 ++++++++---
 2 files changed, 15 insertions(+), 7 deletions(-)

-- 
2.33.0

[PATCH net-next 1/2] net: hns3: extend HCLGE_FD_AD_QID to 11 bits

[Jijie Shao]

Currently, HCLGE_FD_AD_QID has only 10 bits and supports a
maximum of 1023 queues. However, there are actually scenarios
where the queue_id exceeds 1023.

This patch adds an additional bit to HCLGE_FD_AD_QID to ensure
that queue_id greater than 1023 are supported.

Signed-off-by: Jijie Shao <shaojijie@huawei.com>
---
 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h  | 5 +++--
 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 4 +++-
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
index 416e02e7b995..bc333d8710ac 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
@@ -727,8 +727,8 @@ struct hclge_fd_tcam_config_3_cmd {
 
 #define HCLGE_FD_AD_DROP_B		0
 #define HCLGE_FD_AD_DIRECT_QID_B	1
-#define HCLGE_FD_AD_QID_S		2
-#define HCLGE_FD_AD_QID_M		GENMASK(11, 2)
+#define HCLGE_FD_AD_QID_L_S		2
+#define HCLGE_FD_AD_QID_L_M		GENMASK(11, 2)
 #define HCLGE_FD_AD_USE_COUNTER_B	12
 #define HCLGE_FD_AD_COUNTER_NUM_S	13
 #define HCLGE_FD_AD_COUNTER_NUM_M	GENMASK(19, 13)
@@ -741,6 +741,7 @@ struct hclge_fd_tcam_config_3_cmd {
 #define HCLGE_FD_AD_TC_OVRD_B		16
 #define HCLGE_FD_AD_TC_SIZE_S		17
 #define HCLGE_FD_AD_TC_SIZE_M		GENMASK(20, 17)
+#define HCLGE_FD_AD_QID_H_B		21
 
 struct hclge_fd_ad_config_cmd {
 	u8 stage;
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
index b8e2aa19f9e6..a90f1a91f997 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
@@ -5679,11 +5679,13 @@ static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc,
 		hnae3_set_field(ad_data, HCLGE_FD_AD_TC_SIZE_M,
 				HCLGE_FD_AD_TC_SIZE_S, (u32)action->tc_size);
 	}
+	hnae3_set_bit(ad_data, HCLGE_FD_AD_QID_H_B,
+		      action->queue_id >= HCLGE_TQP_MAX_SIZE_DEV_V2 ? 1 : 0);
 	ad_data <<= 32;
 	hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet);
 	hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B,
 		      action->forward_to_direct_queue);
-	hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S,
+	hnae3_set_field(ad_data, HCLGE_FD_AD_QID_L_M, HCLGE_FD_AD_QID_L_S,
 			action->queue_id);
 	hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter);
 	hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M,
-- 
2.33.0

[PATCH net-next 2/2] net: hns3: extend HCLGE_FD_AD_COUNTER_NUM to 8 bits

[Jijie Shao]

Currently, HCLGE_FD_AD_COUNTER_NUM has only 7 bits and supports a
maximum of 127 counter_id. However, there are actually scenarios
where the counter_id exceeds 127.

This patch adds an additional bit to HCLGE_FD_AD_QID to ensure
that counter_id greater than 127 are supported.

Signed-off-by: Jijie Shao <shaojijie@huawei.com>
---
 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h  | 6 ++++--
 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 7 +++++--
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
index bc333d8710ac..4ce92ddefcde 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
@@ -26,6 +26,7 @@ struct hclge_misc_vector {
 #define HCLGE_TQP_REG_OFFSET		0x80000
 #define HCLGE_TQP_REG_SIZE		0x200
 
+#define HCLGE_FD_COUNTER_MAX_SIZE_DEV_V2	128
 #define HCLGE_TQP_MAX_SIZE_DEV_V2	1024
 #define HCLGE_TQP_EXT_REG_OFFSET	0x100
 
@@ -730,8 +731,8 @@ struct hclge_fd_tcam_config_3_cmd {
 #define HCLGE_FD_AD_QID_L_S		2
 #define HCLGE_FD_AD_QID_L_M		GENMASK(11, 2)
 #define HCLGE_FD_AD_USE_COUNTER_B	12
-#define HCLGE_FD_AD_COUNTER_NUM_S	13
-#define HCLGE_FD_AD_COUNTER_NUM_M	GENMASK(19, 13)
+#define HCLGE_FD_AD_COUNTER_NUM_L_S	13
+#define HCLGE_FD_AD_COUNTER_NUM_L_M	GENMASK(19, 13)
 #define HCLGE_FD_AD_NXT_STEP_B		20
 #define HCLGE_FD_AD_NXT_KEY_S		21
 #define HCLGE_FD_AD_NXT_KEY_M		GENMASK(25, 21)
@@ -742,6 +743,7 @@ struct hclge_fd_tcam_config_3_cmd {
 #define HCLGE_FD_AD_TC_SIZE_S		17
 #define HCLGE_FD_AD_TC_SIZE_M		GENMASK(20, 17)
 #define HCLGE_FD_AD_QID_H_B		21
+#define HCLGE_FD_AD_COUNTER_NUM_H_B	26
 
 struct hclge_fd_ad_config_cmd {
 	u8 stage;
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
index a90f1a91f997..edec994981c7 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
@@ -5681,6 +5681,9 @@ static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc,
 	}
 	hnae3_set_bit(ad_data, HCLGE_FD_AD_QID_H_B,
 		      action->queue_id >= HCLGE_TQP_MAX_SIZE_DEV_V2 ? 1 : 0);
+	hnae3_set_bit(ad_data, HCLGE_FD_AD_COUNTER_NUM_H_B,
+		      action->counter_id >= HCLGE_FD_COUNTER_MAX_SIZE_DEV_V2 ?
+		      1 : 0);
 	ad_data <<= 32;
 	hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet);
 	hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B,
@@ -5688,8 +5691,8 @@ static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc,
 	hnae3_set_field(ad_data, HCLGE_FD_AD_QID_L_M, HCLGE_FD_AD_QID_L_S,
 			action->queue_id);
 	hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter);
-	hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M,
-			HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id);
+	hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_L_M,
+			HCLGE_FD_AD_COUNTER_NUM_L_S, action->counter_id);
 	hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage);
 	hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S,
 			action->next_input_key);
-- 
2.33.0

Re: [PATCH net-next 0/2] extend bit width in the flow director of HNS3 driver

[Simon Horman]

On Fri, Jan 23, 2026 at 05:47:54PM +0800, Jijie Shao wrote:
> The bit widths of HCLGE_FD_AD_QID and HCLGE_FD_AD_COUNTER_NUM are
> increased to support higher specifications.
> 
> Note: The hardware already supports the specifications.

Hi Jijie,

Are there any compatibility issues here?
E.g. new driver with old hardware or firmware?

Re: [PATCH net-next 0/2] extend bit width in the flow director of HNS3 driver

[Jijie Shao]

on 2026/1/26 22:03, Simon Horman wrote:
> On Fri, Jan 23, 2026 at 05:47:54PM +0800, Jijie Shao wrote:
>> The bit widths of HCLGE_FD_AD_QID and HCLGE_FD_AD_COUNTER_NUM are
>> increased to support higher specifications.
>>
>> Note: The hardware already supports the specifications.
> Hi Jijie,
>
> Are there any compatibility issues here?
> E.g. new driver with old hardware or firmware?

Thank you, There are no compatibility issues.

The chip and firmware are supported in V2.
However, the software does not support the extension due to
consistency with older versions(and the customer has not used the extended bits either).

The queue_cnt and counter_cnt specifications of the software are directly or indirectly
queried from the firmware, and the extended bits are not used in the V1 version.

Thanks,
Jijie Shao

Re: [PATCH net-next 0/2] extend bit width in the flow director of HNS3 driver

[Simon Horman]

On Tue, Jan 27, 2026 at 09:50:21AM +0800, Jijie Shao wrote:
> 
> on 2026/1/26 22:03, Simon Horman wrote:
> > On Fri, Jan 23, 2026 at 05:47:54PM +0800, Jijie Shao wrote:
> > > The bit widths of HCLGE_FD_AD_QID and HCLGE_FD_AD_COUNTER_NUM are
> > > increased to support higher specifications.
> > > 
> > > Note: The hardware already supports the specifications.
> > Hi Jijie,
> > 
> > Are there any compatibility issues here?
> > E.g. new driver with old hardware or firmware?
> 
> Thank you, There are no compatibility issues.
> 
> The chip and firmware are supported in V2.
> However, the software does not support the extension due to
> consistency with older versions(and the customer has not used the extended bits either).
> 
> The queue_cnt and counter_cnt specifications of the software are directly
> or indirectly queried from the firmware, and the extended bits are not
> used in the V1 version.
> 

Thanks, I think that addresses my concern.

The code changes themselves look good to me.
So, for the series:

Reviewed-by: Simon Horman <horms@kernel.org>

Re: [PATCH net-next 0/2] extend bit width in the flow director of HNS3 driver

[patchwork-bot+netdevbpf]

Hello:

This series was applied to netdev/net-next.git (main)
by Paolo Abeni <pabeni@redhat.com>:

On Fri, 23 Jan 2026 17:47:54 +0800 you wrote:
> The bit widths of HCLGE_FD_AD_QID and HCLGE_FD_AD_COUNTER_NUM are
> increased to support higher specifications.
> 
> Note: The hardware already supports the specifications.
> 
> Jijie Shao (2):
>   net: hns3: extend HCLGE_FD_AD_QID to 11 bits
>   net: hns3: extend HCLGE_FD_AD_COUNTER_NUM to 8 bits
> 
> [...]

Here is the summary with links:
  - [net-next,1/2] net: hns3: extend HCLGE_FD_AD_QID to 11 bits
    https://git.kernel.org/netdev/net-next/c/878406d4d6ef
  - [net-next,2/2] net: hns3: extend HCLGE_FD_AD_COUNTER_NUM to 8 bits
    https://git.kernel.org/netdev/net-next/c/6a0fc0ea61bd

You are awesome, thank you!
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