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From: Daniel Golle <daniel@makrotopia.org>
To: Vladimir Oltean <olteanv@gmail.com>
Cc: Hauke Mehrtens <hauke@hauke-m.de>, Andrew Lunn <andrew@lunn.ch>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	netdev@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH net-next 1/3] dt-bindings: net: dsa: lantiq,gswip: reference common PHY properties
Date: Wed, 28 Jan 2026 01:47:36 +0000	[thread overview]
Message-ID: <aXlquKmPKzGPBudZ@makrotopia.org> (raw)
In-Reply-To: <20260127222508.gvky6smlrmnj3uix@skbuf>

On Wed, Jan 28, 2026 at 12:25:08AM +0200, Vladimir Oltean wrote:
> On Tue, Jan 27, 2026 at 10:10:58PM +0000, Daniel Golle wrote:
> > Taking a step back I noticed that we need to decide this also for
> > mt7530.
> > 
> > commit bde1ae2d52ab ("net: pcs: pcs-mtk-lynxi: pass SGMIISYS OF node to PCS")
> > currently doesn't pass any fwnode when creating the LynxI PCS.
> > > +               pcs = mtk_pcs_lynxi_create(priv->dev, NULL, regmap,
> > > +                                          MT7531_PHYA_CTRL_SIGNAL3);
> > 
> > However, each PCS does belong to a specific switch port, and it would be
> > advantegous and imho consistent to also assign the ports OF node to the
> > PCS, this would allow to configure the polarities also on the MT7530
> > SerDes ports.
> 
> mt753x_phylink_mac_select_pcs() returns either &priv->pcs[dp->index].pcs
> for TRGMII or priv->ports[dp->index].sgmii_pcs for the rest.
> 
> How would one know (generally speaking) if properties placed in the
> ethernet-port node are for the SGMII PCS or for the other one?

Because of the port number and a fixed assignment of possible external
interface types to each port: On MT7531, port 6 is always connected
to the SerDes PCS. On MT7531AE port 5 is another SerDes PCS, while
on MT7531BE port 5 is (the only) (T)RGMII interface.
So, just like with the MaxLinear GSW1xx port and PCS are tightly
tied together.

  reply	other threads:[~2026-01-28  1:47 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-27 13:18 [PATCH net-next 0/3] net: dsa: mxl-gsw1xx: setup polarities and validate chip Daniel Golle
2026-01-27 13:18 ` [PATCH net-next 1/3] dt-bindings: net: dsa: lantiq,gswip: reference common PHY properties Daniel Golle
2026-01-27 13:29   ` Vladimir Oltean
2026-01-27 14:07     ` Daniel Golle
2026-01-27 15:07       ` Vladimir Oltean
2026-01-27 22:10         ` Daniel Golle
2026-01-27 22:25           ` Vladimir Oltean
2026-01-28  1:47             ` Daniel Golle [this message]
2026-01-27 15:21       ` Andrew Lunn
2026-01-27 16:22         ` Daniel Golle
2026-01-27 13:18 ` [PATCH net-next 2/3] net: dsa: mxl-gsw1xx: configure PCS polarities Daniel Golle
2026-01-27 13:25   ` Vladimir Oltean
2026-01-27 13:18 ` [PATCH net-next 3/3] net: dsa: mxl-gsw1xx: validate chip ID Daniel Golle

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