Re: [RFC PATCH] net: phy: integrate reset-after-clock quirk into phy_init_hw

["Russell King (Oracle)" <linux@armlinux.org.uk>]

On Wed, Jan 28, 2026 at 10:45:32PM +0100, Andrew Lunn wrote:
> On Wed, Jan 28, 2026 at 10:04:03PM +0100, Michael Nazzareno Trimarchi wrote:
> > Hi
> > 
> > On Wed, Jan 28, 2026 at 9:51 PM Andrew Lunn <andrew@lunn.ch> wrote:
> > >
> > > > The issue was with the out-of-band reset coming from the FEC driver
> > > > which doesn't honor the phy state-machine.
> > >
> > > Could you explain this is more details. Is the FEC doing something
> > > wrong?
> > 
> > The fact that the phy should be reset when the clk is provided to it, is not
> > connected at all with the fec. I think that fec_main does not register itself
> > as clock provider, You "should" define the phy to have a clock if this is needed
> > during the restoration and we should not give any "magic" at controller level.
> 
> Do we know which clock the PHY is consuming?
> 
> The FEC has code for the clock "enet_out" which it enables and
> disables. If the PHY is also consuming this clock, we could also make
> it a consumer. The CCF reference counts enables/disables of clocks, so
> if the PHY enables it, the MAC won't be able to disable it.

As I've just mentioned earlier in this thread, there seems to be nothing
special about the LAN8710-like PHYs requiring their XTAL clock to be
running for reset to be functional. The same is true of AR8035 used
on i.MX6 SolidRun platforms, and Marvell 88E151x PHYs that I've looked
at. I would suggest that, in general, _all_ PHYs require their XTAL
clock to be running.

Therefore, this is not a work of the PHY at all.

It is a quirk of the board design to provide the PHY's XTAL clock from
the SoC, and this _seems_ to be common with FEC based systems, probably
because there's an easy way to get the clock from the FEC, thus saving
the cost of a crystal.

I stated how SolidRun handles this quirk entirely in uboot so the kernel
doesn't have to care about this at all, and the kernel doesn't get to
even know that the PHY has a reset GPIO.

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