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From: Simon Horman <horms@kernel.org>
To: Daniel Machon <daniel.machon@microchip.com>
Cc: Andrew Lunn <andrew+netdev@lunn.ch>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Steen Hegelund <Steen.Hegelund@microchip.com>,
	UNGLinuxDriver@microchip.com, netdev@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH net] net: sparx5/lan969x: fix DWRR cost max to match hardware register width
Date: Thu, 12 Feb 2026 17:53:39 +0000	[thread overview]
Message-ID: <aY4TozfU1piv40Nh@horms.kernel.org> (raw)
In-Reply-To: <20260210-sparx5-fix-dwrr-cost-max-v1-1-58fbdbc25652@microchip.com>

On Tue, Feb 10, 2026 at 02:44:01PM +0100, Daniel Machon wrote:
> DWRR (Deficit Weighted Round Robin) scheduling distributes bandwidth
> across traffic classes based on per-queue cost values, where lower cost
> means higher bandwidth share.
> 
> The SPX5_DWRR_COST_MAX constant is 63 (6 bits) but the hardware
> register field HSCH_DWRR_ENTRY_DWRR_COST is GENMASK(24, 20), only
> 5 bits wide (max 31). This causes sparx5_weight_to_hw_cost() to
> compute cost values that silently overflow via FIELD_PREP, resulting
> in incorrect scheduling weights.
> 
> Set SPX5_DWRR_COST_MAX to 31 to match the hardware register width.
> 
> Fixes: 211225428d65 ("net: microchip: sparx5: add support for offloading ets qdisc")
> Signed-off-by: Daniel Machon <daniel.machon@microchip.com>

Reviewed-by: Simon Horman <horms@kernel.org>


  reply	other threads:[~2026-02-12 17:53 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-10 13:44 [PATCH net] net: sparx5/lan969x: fix DWRR cost max to match hardware register width Daniel Machon
2026-02-12 17:53 ` Simon Horman [this message]
2026-02-13  3:10 ` patchwork-bot+netdevbpf

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