From: "Russell King (Oracle)" <linux@armlinux.org.uk>
To: Meghana Malladi <m-malladi@ti.com>
Cc: pabeni@redhat.com, kuba@kernel.org, edumazet@google.com,
davem@davemloft.net, hkallweit1@gmail.com, andrew@lunn.ch,
linux-kernel@vger.kernel.org, netdev@vger.kernel.org, srk@ti.com,
Vignesh Raghavendra <vigneshr@ti.com>,
Roger Quadros <rogerq@kernel.org>,
danishanwar@ti.com
Subject: Re: [PATCH net] net: phy: dp83869: Set auto mdix bit for forced 100Base-Tx mode
Date: Wed, 11 Feb 2026 14:04:48 +0000 [thread overview]
Message-ID: <aYyMgK73UtBd6vqc@shell.armlinux.org.uk> (raw)
In-Reply-To: <b500116b-afdc-4e5b-af4b-6c1e15116111@ti.com>
On Wed, Feb 11, 2026 at 07:23:12PM +0530, Meghana Malladi wrote:
> Hi Russell,
>
> On 2/11/26 18:56, Russell King (Oracle) wrote:
> > On Wed, Feb 11, 2026 at 06:40:32PM +0530, Meghana Malladi wrote:
> > > When using DP83869 in force 100Base-Tx mode, the PHY is required
> > > to have robust Auto-MDIX feature enabled from register 1Eh.
> > > Refer to 7.4.1.2 100BASE-TX section in the TRM [1] for more details.
> > >
> > > [1]: https://www.ti.com/lit/ds/symlink/dp83869hm.pdf
> > > Signed-off-by: Meghana Malladi <m-malladi@ti.com>
> > > ---
> > > drivers/net/phy/dp83869.c | 19 +++++++++++++++++++
> > > 1 file changed, 19 insertions(+)
> > >
> > > diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c
> > > index 1f381d7b13ff..70d759c45c6a 100644
> > > --- a/drivers/net/phy/dp83869.c
> > > +++ b/drivers/net/phy/dp83869.c
> > > @@ -110,6 +110,7 @@
> > > /* CFG4 bits */
> > > #define DP83869_INT_OE BIT(7)
> > > +#define DP83869_CFG4_ENABLE_AUTO_MDIX_100FD BIT(9)
> > > /* OP MODE */
> > > #define DP83869_OP_MODE_MII BIT(5)
> > > @@ -900,6 +901,23 @@ static int dp83869_phy_reset(struct phy_device *phydev)
> > > return dp83869_config_init(phydev);
> > > }
> > > +static void dp83869_link_change_notify(struct phy_device *phydev)
> > > +{
> > > + int cfg4;
> > > +
> > > + /* When using DP83869 in force 100Base-Tx mode, the PHY is required
> > > + * to have robust Auto-MDIX feature enabled
> > > + */
> > > + if (phydev->autoneg == AUTONEG_DISABLE &&
> > > + phydev->speed == SPEED_100 &&
> > > + phydev->duplex == DUPLEX_FULL) {
> > > + cfg4 = phy_read(phydev, DP83869_CFG4);
> > > + if (cfg4 >= 0) {
> > > + cfg4 |= DP83869_CFG4_ENABLE_AUTO_MDIX_100FD;
> > > + phy_write(phydev, DP83869_CFG4, cfg4);
> > > + }
> > > + }
> >
> > Shouldn't this kind of configuration be done via .config_aneg() ?
> >
>
> AFAIK, in case of fixed mode, auto-neg might not be triggered all the time.
> In the phy_ethtool_ksettings_set() function, auto-neg is initiated only if
> the PHY hasn't started. PHY drivers are new to me, please do correct me if I
> am wrong.
In phy_ethtool_ksettings_set():
/* Restart the PHY */
if (phy_is_started(phydev)) {
phydev->state = PHY_UP;
phy_trigger_machine(phydev);
} else {
_phy_start_aneg(phydev);
}
If the PHY is started, then the state machine is triggered. That
will result in phy_state_machine() being called.
This calls _phy_state_machine(), which, as phydev->state is set to
PHY_UP, will set state_work = PHY_STATE_WORK_ANEG. This will then
result in:
if (state_work == PHY_STATE_WORK_ANEG) {
err = _phy_start_aneg(phydev);
func = &_phy_start_aneg;
}
which also results in _phy_start_aneg() being called, and thus the
.config_aneg() method.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
next prev parent reply other threads:[~2026-02-11 14:05 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-11 13:10 [PATCH net] net: phy: dp83869: Set auto mdix bit for forced 100Base-Tx mode Meghana Malladi
2026-02-11 13:26 ` Russell King (Oracle)
2026-02-11 13:53 ` Meghana Malladi
2026-02-11 14:04 ` Andrew Lunn
2026-02-11 14:09 ` Meghana Malladi
2026-02-11 14:04 ` Russell King (Oracle) [this message]
2026-02-11 14:12 ` Andrew Lunn
2026-02-12 6:21 ` Meghana Malladi
2026-02-12 13:06 ` Andrew Lunn
2026-02-15 14:56 ` Malladi, Meghana
2026-02-12 18:40 ` Maxime Chevallier
2026-02-15 14:45 ` [EXTERNAL] " Malladi, Meghana
2026-02-15 17:23 ` Andrew Lunn
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