* [PATCH v6 1/5] net: stmmac: Use helper macro for loop over queue-based arrays
2026-02-25 9:20 [PATCH v6 0/5] Support multi-channel IRQs in stmmac platform drivers Jan Petrous via B4 Relay
@ 2026-02-25 9:20 ` Jan Petrous via B4 Relay
2026-02-25 9:20 ` [PATCH v6 2/5] net: stmmac: platform: read channels irq Jan Petrous via B4 Relay
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Jan Petrous via B4 Relay @ 2026-02-25 9:20 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Maxime Coquelin, Alexandre Torgue, Chester Lin,
Matthias Brugger, Ghennadi Procopciuc, NXP S32 Linux Team,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li
Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, imx,
devicetree, rmk+kernel, Jan Petrous (OSS)
From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
The stmmac driver contains similar pattern for processing queue-based
arrays, ie. interrupt lines, etc. Factor out the for loop and provide
a macro STMMAC_FOREACH_MTL_QUEUE(var, limit).
Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
---
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c | 2 +-
drivers/net/ethernet/stmicro/stmmac/stmmac.h | 3 +++
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 16 ++++++++--------
3 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
index 49893b9fb88c..3890e82c69f6 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
@@ -233,7 +233,7 @@ static void dwxgmac2_prog_mtl_tx_algorithms(struct mac_device_info *hw,
writel(value, ioaddr + XGMAC_MTL_OPMODE);
/* Set ETS if desired */
- for (i = 0; i < MTL_MAX_TX_QUEUES; i++) {
+ STMMAC_FOREACH_MTL_QUEUE(i, MTL_MAX_TX_QUEUES) {
value = readl(ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(i));
value &= ~XGMAC_TSA;
if (ets)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
index 51c96a738151..c972ad8e79f8 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
@@ -382,6 +382,9 @@ enum stmmac_state {
extern const struct dev_pm_ops stmmac_simple_pm_ops;
+#define STMMAC_FOREACH_MTL_QUEUE(var, limit) \
+ for (var = 0; var < (limit); var++)
+
int stmmac_mdio_unregister(struct net_device *ndev);
int stmmac_mdio_register(struct net_device *ndev);
int stmmac_mdio_reset(struct mii_bus *mii);
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index edf0799b7236..b920ca17b2be 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -3875,7 +3875,7 @@ static int stmmac_request_irq_multi_msi(struct net_device *dev)
}
/* Request Rx MSI irq */
- for (i = 0; i < priv->plat->rx_queues_to_use; i++) {
+ STMMAC_FOREACH_MTL_QUEUE(i, priv->plat->rx_queues_to_use) {
if (i >= MTL_MAX_RX_QUEUES)
break;
if (priv->rx_irq[i] == 0)
@@ -3899,7 +3899,7 @@ static int stmmac_request_irq_multi_msi(struct net_device *dev)
}
/* Request Tx MSI irq */
- for (i = 0; i < priv->plat->tx_queues_to_use; i++) {
+ STMMAC_FOREACH_MTL_QUEUE(i, priv->plat->tx_queues_to_use) {
if (i >= MTL_MAX_TX_QUEUES)
break;
if (priv->tx_irq[i] == 0)
@@ -4084,10 +4084,10 @@ static int __stmmac_open(struct net_device *dev,
struct stmmac_dma_conf *dma_conf)
{
struct stmmac_priv *priv = netdev_priv(dev);
+ int ret, i;
u32 chan;
- int ret;
- for (int i = 0; i < MTL_MAX_TX_QUEUES; i++)
+ STMMAC_FOREACH_MTL_QUEUE(i, MTL_MAX_TX_QUEUES)
if (priv->dma_conf.tx_queue[i].tbs & STMMAC_TBS_EN)
dma_conf->tx_queue[i].tbs = priv->dma_conf.tx_queue[i].tbs;
memcpy(&priv->dma_conf, dma_conf, sizeof(*dma_conf));
@@ -7734,9 +7734,9 @@ static int __stmmac_dvr_probe(struct device *device,
priv->device = device;
priv->dev = ndev;
- for (i = 0; i < MTL_MAX_RX_QUEUES; i++)
+ STMMAC_FOREACH_MTL_QUEUE(i, MTL_MAX_RX_QUEUES)
u64_stats_init(&priv->xstats.rxq_stats[i].napi_syncp);
- for (i = 0; i < MTL_MAX_TX_QUEUES; i++) {
+ STMMAC_FOREACH_MTL_QUEUE(i, MTL_MAX_TX_QUEUES) {
u64_stats_init(&priv->xstats.txq_stats[i].q_syncp);
u64_stats_init(&priv->xstats.txq_stats[i].napi_syncp);
}
@@ -7759,9 +7759,9 @@ static int __stmmac_dvr_probe(struct device *device,
priv->sfty_irq = res->sfty_irq;
priv->sfty_ce_irq = res->sfty_ce_irq;
priv->sfty_ue_irq = res->sfty_ue_irq;
- for (i = 0; i < MTL_MAX_RX_QUEUES; i++)
+ STMMAC_FOREACH_MTL_QUEUE(i, MTL_MAX_RX_QUEUES)
priv->rx_irq[i] = res->rx_irq[i];
- for (i = 0; i < MTL_MAX_TX_QUEUES; i++)
+ STMMAC_FOREACH_MTL_QUEUE(i, MTL_MAX_TX_QUEUES)
priv->tx_irq[i] = res->tx_irq[i];
if (!is_zero_ether_addr(res->mac))
--
2.47.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v6 2/5] net: stmmac: platform: read channels irq
2026-02-25 9:20 [PATCH v6 0/5] Support multi-channel IRQs in stmmac platform drivers Jan Petrous via B4 Relay
2026-02-25 9:20 ` [PATCH v6 1/5] net: stmmac: Use helper macro for loop over queue-based arrays Jan Petrous via B4 Relay
@ 2026-02-25 9:20 ` Jan Petrous via B4 Relay
2026-02-25 9:20 ` [PATCH v6 3/5] dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts Jan Petrous via B4 Relay
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Jan Petrous via B4 Relay @ 2026-02-25 9:20 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Maxime Coquelin, Alexandre Torgue, Chester Lin,
Matthias Brugger, Ghennadi Procopciuc, NXP S32 Linux Team,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li
Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, imx,
devicetree, rmk+kernel, Jan Petrous (OSS)
From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
Read IRQ resources for all rx/tx channels, to allow Multi-IRQ mode
for platform glue drivers.
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
---
.../net/ethernet/stmicro/stmmac/stmmac_platform.c | 40 +++++++++++++++++++++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 5c9fd91a1db9..64cb8751b327 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -700,6 +700,9 @@ EXPORT_SYMBOL_GPL(stmmac_pltfr_find_clk);
int stmmac_get_platform_resources(struct platform_device *pdev,
struct stmmac_resources *stmmac_res)
{
+ char name[16];
+ int i;
+
memset(stmmac_res, 0, sizeof(*stmmac_res));
/* Get IRQ information early to have an ability to ask for deferred
@@ -735,7 +738,42 @@ int stmmac_get_platform_resources(struct platform_device *pdev,
stmmac_res->addr = devm_platform_ioremap_resource(pdev, 0);
- return PTR_ERR_OR_ZERO(stmmac_res->addr);
+ if (IS_ERR(stmmac_res->addr))
+ return PTR_ERR(stmmac_res->addr);
+
+ /* RX channels irq */
+ STMMAC_FOREACH_MTL_QUEUE(i, MTL_MAX_RX_QUEUES) {
+ scnprintf(name, sizeof(name), "rx-queue-%d", i);
+ stmmac_res->rx_irq[i] = platform_get_irq_byname_optional(pdev,
+ name);
+ if (stmmac_res->rx_irq[i] <= 0) {
+ if (stmmac_res->rx_irq[i] == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+ dev_dbg(&pdev->dev, "IRQ rx-queue-%d not found\n", i);
+
+ /* Stop on first unset rx-queue-%i property member */
+ stmmac_res->rx_irq[i] = 0;
+ break;
+ }
+ }
+
+ /* TX channels irq */
+ STMMAC_FOREACH_MTL_QUEUE(i, MTL_MAX_TX_QUEUES) {
+ scnprintf(name, sizeof(name), "tx-queue-%d", i);
+ stmmac_res->tx_irq[i] = platform_get_irq_byname_optional(pdev,
+ name);
+ if (stmmac_res->tx_irq[i] <= 0) {
+ if (stmmac_res->tx_irq[i] == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+ dev_dbg(&pdev->dev, "IRQ tx-queue-%d not found\n", i);
+
+ /* Stop on first unset tx-queue-%i property member */
+ stmmac_res->tx_irq[i] = 0;
+ break;
+ }
+ }
+
+ return 0;
}
EXPORT_SYMBOL_GPL(stmmac_get_platform_resources);
--
2.47.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v6 3/5] dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts
2026-02-25 9:20 [PATCH v6 0/5] Support multi-channel IRQs in stmmac platform drivers Jan Petrous via B4 Relay
2026-02-25 9:20 ` [PATCH v6 1/5] net: stmmac: Use helper macro for loop over queue-based arrays Jan Petrous via B4 Relay
2026-02-25 9:20 ` [PATCH v6 2/5] net: stmmac: platform: read channels irq Jan Petrous via B4 Relay
@ 2026-02-25 9:20 ` Jan Petrous via B4 Relay
2026-02-25 9:25 ` Russell King (Oracle)
2026-02-25 9:20 ` [PATCH v6 4/5] arm64: dts: s32: set Ethernet channel irqs Jan Petrous via B4 Relay
2026-02-25 9:20 ` [PATCH v6 5/5] stmmac: s32: enable support for Multi-IRQ mode Jan Petrous via B4 Relay
4 siblings, 1 reply; 8+ messages in thread
From: Jan Petrous via B4 Relay @ 2026-02-25 9:20 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Maxime Coquelin, Alexandre Torgue, Chester Lin,
Matthias Brugger, Ghennadi Procopciuc, NXP S32 Linux Team,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li
Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, imx,
devicetree, rmk+kernel, Jan Petrous (OSS)
From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
The DWMAC IP on NXP S32G/R SoCs has connected queue-based IRQ lines,
set them to allow using Multi-IRQ mode.
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
---
.../devicetree/bindings/net/nxp,s32-dwmac.yaml | 44 +++++++++++++++++++---
1 file changed, 39 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
index 1b2934f3c87c..3a0e41b63c3d 100644
--- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-# Copyright 2021-2024 NXP
+# Copyright 2021-2026 NXP
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml#
@@ -16,6 +16,8 @@ description:
the SoC S32R45 has two instances. The devices can use RGMII/RMII/MII
interface over Pinctrl device or the output can be routed
to the embedded SerDes for SGMII connectivity.
+ The DWMAC instances have connected all RX/TX queues interrupts,
+ enabling load balancing of data traffic across all CPU cores.
properties:
compatible:
@@ -45,10 +47,22 @@ properties:
FlexTimer Modules connect to GMAC_0.
interrupts:
- maxItems: 1
+ minItems: 11
+ maxItems: 11
interrupt-names:
- const: macirq
+ items:
+ - const: macirq
+ - const: tx-queue-0
+ - const: rx-queue-0
+ - const: tx-queue-1
+ - const: rx-queue-1
+ - const: tx-queue-2
+ - const: rx-queue-2
+ - const: tx-queue-3
+ - const: rx-queue-3
+ - const: tx-queue-4
+ - const: rx-queue-4
clocks:
items:
@@ -88,8 +102,28 @@ examples:
<0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */
nxp,phy-sel = <&gpr 0x4>;
interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 0: tx, rx */
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 1: tx, rx */
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 2: tx, rx */
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 3: tx, rx */
+ <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 4: tx, rx */
+ <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq",
+ "tx-queue-0", "rx-queue-0",
+ "tx-queue-1", "rx-queue-1",
+ "tx-queue-2", "rx-queue-2",
+ "tx-queue-3", "rx-queue-3",
+ "tx-queue-4", "rx-queue-4";
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
clocks = <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>;
--
2.47.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v6 3/5] dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts
2026-02-25 9:20 ` [PATCH v6 3/5] dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts Jan Petrous via B4 Relay
@ 2026-02-25 9:25 ` Russell King (Oracle)
2026-02-25 10:37 ` Jan Petrous
0 siblings, 1 reply; 8+ messages in thread
From: Russell King (Oracle) @ 2026-02-25 9:25 UTC (permalink / raw)
To: jan.petrous
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Maxime Coquelin, Alexandre Torgue, Chester Lin,
Matthias Brugger, Ghennadi Procopciuc, NXP S32 Linux Team,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li, netdev,
linux-stm32, linux-arm-kernel, linux-kernel, imx, devicetree
On Wed, Feb 25, 2026 at 10:20:35AM +0100, Jan Petrous via B4 Relay wrote:
> From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
>
> The DWMAC IP on NXP S32G/R SoCs has connected queue-based IRQ lines,
> set them to allow using Multi-IRQ mode.
>
> Reviewed-by: Matthias Brugger <mbrugger@suse.com>
> Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
> Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
> ---
> .../devicetree/bindings/net/nxp,s32-dwmac.yaml | 44 +++++++++++++++++++---
As you have added support for these IRQs into the generic code,
shouldn't the generic dwmac binding doc reflect that this is now
supported?
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v6 3/5] dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts
2026-02-25 9:25 ` Russell King (Oracle)
@ 2026-02-25 10:37 ` Jan Petrous
0 siblings, 0 replies; 8+ messages in thread
From: Jan Petrous @ 2026-02-25 10:37 UTC (permalink / raw)
To: Russell King (Oracle)
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Maxime Coquelin, Alexandre Torgue, Chester Lin,
Matthias Brugger, Ghennadi Procopciuc, NXP S32 Linux Team,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li, netdev,
linux-stm32, linux-arm-kernel, linux-kernel, imx, devicetree
On Wed, Feb 25, 2026 at 09:25:28AM +0000, Russell King (Oracle) wrote:
> On Wed, Feb 25, 2026 at 10:20:35AM +0100, Jan Petrous via B4 Relay wrote:
> > From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
> >
> > The DWMAC IP on NXP S32G/R SoCs has connected queue-based IRQ lines,
> > set them to allow using Multi-IRQ mode.
> >
> > Reviewed-by: Matthias Brugger <mbrugger@suse.com>
> > Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
> > Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
> > ---
> > .../devicetree/bindings/net/nxp,s32-dwmac.yaml | 44 +++++++++++++++++++---
>
> As you have added support for these IRQs into the generic code,
> shouldn't the generic dwmac binding doc reflect that this is now
> supported?
>
Hi Russell,
the generic yaml has such interrupt names already declared:
https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/net/snps%2Cdwmac.yaml#L142
Here is the current interrupt snippet:
interrupt-names:
minItems: 1
maxItems: 19
items:
oneOf:
- description: Combined signal for various interrupt events
const: macirq
- description: The interrupt to manage the remote wake-up packet detection
const: eth_wake_irq
- description: The interrupt that occurs when Rx exits the LPI state
const: eth_lpi
- description: The interrupt that occurs when HW safety error triggered
const: sfty
- description: Per channel receive completion interrupt
pattern: '^rx-queue-[0-7]$'
- description: Per channel transmit completion interrupt
pattern: '^tx-queue-[0-7]$'
- description: PPS interrupt
pattern: '^ptp-pps-[0-3]$'
BR.
/Jan
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v6 4/5] arm64: dts: s32: set Ethernet channel irqs
2026-02-25 9:20 [PATCH v6 0/5] Support multi-channel IRQs in stmmac platform drivers Jan Petrous via B4 Relay
` (2 preceding siblings ...)
2026-02-25 9:20 ` [PATCH v6 3/5] dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts Jan Petrous via B4 Relay
@ 2026-02-25 9:20 ` Jan Petrous via B4 Relay
2026-02-25 9:20 ` [PATCH v6 5/5] stmmac: s32: enable support for Multi-IRQ mode Jan Petrous via B4 Relay
4 siblings, 0 replies; 8+ messages in thread
From: Jan Petrous via B4 Relay @ 2026-02-25 9:20 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Maxime Coquelin, Alexandre Torgue, Chester Lin,
Matthias Brugger, Ghennadi Procopciuc, NXP S32 Linux Team,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li
Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, imx,
devicetree, rmk+kernel, Jan Petrous (OSS)
From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
The GMAC Ethernet controller found on S32G2/S32G3 and S32R45
contains up to 5 RX and 5 TX channels.
It can operate in two interrupt modes:
1) Sharing IRQ mode: only MAC IRQ line is used
for all channels.
2) Multiple IRQ mode: every channel uses two IRQ lines,
one for RX and second for TX.
Specify all IRQ twins for all channels.
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
---
arch/arm64/boot/dts/freescale/s32g2.dtsi | 26 +++++++++++++++++++++++---
arch/arm64/boot/dts/freescale/s32g3.dtsi | 26 +++++++++++++++++++++++---
2 files changed, 46 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 51d00dac12de..5a553d503137 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -3,7 +3,7 @@
* NXP S32G2 SoC family
*
* Copyright (c) 2021 SUSE LLC
- * Copyright 2017-2021, 2024-2025 NXP
+ * Copyright 2017-2021, 2024-2026 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -732,8 +732,28 @@ gmac0: ethernet@4033c000 {
reg = <0x4033c000 0x2000>, /* gmac IP */
<0x4007c004 0x4>; /* GMAC_0_CTRL_STS */
interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 0: tx, rx */
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 1: tx, rx */
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 2: tx, rx */
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 3: tx, rx */
+ <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 4: tx, rx */
+ <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq",
+ "tx-queue-0", "rx-queue-0",
+ "tx-queue-1", "rx-queue-1",
+ "tx-queue-2", "rx-queue-2",
+ "tx-queue-3", "rx-queue-3",
+ "tx-queue-4", "rx-queue-4";
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index e314f3c7d61d..b43e6f001f4d 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
- * Copyright 2021-2025 NXP
+ * Copyright 2021-2026 NXP
*
* Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
* Ciprian Costea <ciprianmarian.costea@nxp.com>
@@ -809,8 +809,28 @@ gmac0: ethernet@4033c000 {
reg = <0x4033c000 0x2000>, /* gmac IP */
<0x4007c004 0x4>; /* GMAC_0_CTRL_STS */
interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 0: tx, rx */
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 1: tx, rx */
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 2: tx, rx */
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 3: tx, rx */
+ <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ /* CHN 4: tx, rx */
+ <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq",
+ "tx-queue-0", "rx-queue-0",
+ "tx-queue-1", "rx-queue-1",
+ "tx-queue-2", "rx-queue-2",
+ "tx-queue-3", "rx-queue-3",
+ "tx-queue-4", "rx-queue-4";
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
status = "disabled";
--
2.47.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v6 5/5] stmmac: s32: enable support for Multi-IRQ mode
2026-02-25 9:20 [PATCH v6 0/5] Support multi-channel IRQs in stmmac platform drivers Jan Petrous via B4 Relay
` (3 preceding siblings ...)
2026-02-25 9:20 ` [PATCH v6 4/5] arm64: dts: s32: set Ethernet channel irqs Jan Petrous via B4 Relay
@ 2026-02-25 9:20 ` Jan Petrous via B4 Relay
4 siblings, 0 replies; 8+ messages in thread
From: Jan Petrous via B4 Relay @ 2026-02-25 9:20 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Maxime Coquelin, Alexandre Torgue, Chester Lin,
Matthias Brugger, Ghennadi Procopciuc, NXP S32 Linux Team,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li
Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, imx,
devicetree, rmk+kernel, Jan Petrous (OSS)
From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
Based on previous changes in platform driver, the vendor
glue driver can enable Multi-IRQ mode, if needed.
To get enabled Multi-IRQ mode for dwmac-s32, the driver checks:
1) property of 'snps,mtl-xx-config' subnode
defines 'snps,xx-queues-to-use' bigger then one, ie:
ethernet@4033c000 {
compatible = "nxp,s32g2-dwmac";
...
snps,mtl-rx-config = <&mtl_rx_setup>;
...
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <2>;
};
2) queue based IRQs are set, ie:
ethernet@4033c000 {
compatible = "nxp,s32g2-dwmac";
...
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
/* CHN 0: tx, rx */
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
/* CHN 1: tx, rx */
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq",
"tx-queue-0", "rx-queue-0",
"tx-queue-1", "rx-queue-1";
If those prerequisites are met, the driver switch to Multi-IRQ mode,
using per-queue IRQs for rx/tx data pathr:
[ 1.387045] s32-dwmac 4033c000.ethernet: Multi-IRQ mode (per queue IRQs) selected
Now the driver owns all queues IRQs:
root@s32g399aevb3:~# grep eth /proc/interrupts
29: 0 0 0 0 0 0 0 0 GICv3 89 Level eth0:mac
30: 0 0 0 0 0 0 0 0 GICv3 91 Level eth0:rx-0
31: 0 0 0 0 0 0 0 0 GICv3 93 Level eth0:rx-1
32: 0 0 0 0 0 0 0 0 GICv3 95 Level eth0:rx-2
33: 0 0 0 0 0 0 0 0 GICv3 97 Level eth0:rx-3
34: 0 0 0 0 0 0 0 0 GICv3 99 Level eth0:rx-4
35: 0 0 0 0 0 0 0 0 GICv3 90 Level eth0:tx-0
36: 0 0 0 0 0 0 0 0 GICv3 92 Level eth0:tx-1
37: 0 0 0 0 0 0 0 0 GICv3 94 Level eth0:tx-2
38: 0 0 0 0 0 0 0 0 GICv3 96 Level eth0:tx-3
39: 0 0 0 0 0 0 0 0 GICv3 98 Level eth0:tx-4
Otherwise, if one of the prerequisite don't met, the driver
continue with MAC IRQ mode:
[ 1.387045] s32-dwmac 4033c000.ethernet: MAC IRQ mode selected
And only MAC IRQ will be attached:
root@s32g399aevb3:~# grep eth /proc/interrupts
29: 0 0 0 0 0 0 0 0 GICv3 89 Level eth0:mac
What represents the original MAC IRQ mode and is fully backward
compatible.
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c | 36 ++++++++++++++++++++++++-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
index af594a096676..03e014c10d3f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
@@ -2,7 +2,7 @@
/*
* NXP S32G/R GMAC glue layer
*
- * Copyright 2019-2024 NXP
+ * Copyright 2019-2026 NXP
*
*/
@@ -110,6 +110,37 @@ static void s32_gmac_exit(struct device *dev, void *priv)
clk_disable_unprepare(gmac->rx_clk);
}
+static void s32_gmac_validate_multi_irq(struct device *dev,
+ struct plat_stmmacenet_data *plat,
+ struct stmmac_resources *res)
+{
+ int i;
+
+ /* RX IRQs */
+ STMMAC_FOREACH_MTL_QUEUE(i, plat->rx_queues_to_use) {
+ if (res->rx_irq[i] <= 0) {
+ dev_dbg(dev, "Missing RX queue %d interrupt\n", i);
+ goto no_multi_irq;
+ }
+ }
+
+ /* TX IRQs */
+ STMMAC_FOREACH_MTL_QUEUE(i, plat->tx_queues_to_use) {
+ if (res->tx_irq[i] <= 0) {
+ dev_dbg(dev, "Missing TX queue %d interrupt\n", i);
+ goto no_multi_irq;
+ }
+ }
+
+ plat->flags |= STMMAC_FLAG_MULTI_MSI_EN;
+ dev_info(dev, "Multi-IRQ mode (per queue IRQs) selected\n");
+ return;
+
+no_multi_irq:
+ plat->flags &= ~STMMAC_FLAG_MULTI_MSI_EN;
+ dev_info(dev, "MAC IRQ mode selected\n");
+}
+
static int s32_dwmac_probe(struct platform_device *pdev)
{
struct plat_stmmacenet_data *plat;
@@ -165,6 +196,9 @@ static int s32_dwmac_probe(struct platform_device *pdev)
plat->core_type = DWMAC_CORE_GMAC4;
plat->pmt = 1;
plat->flags |= STMMAC_FLAG_SPH_DISABLE;
+
+ s32_gmac_validate_multi_irq(dev, plat, &res);
+
plat->rx_fifo_size = 20480;
plat->tx_fifo_size = 20480;
--
2.47.0
^ permalink raw reply related [flat|nested] 8+ messages in thread