From: Simon Horman <horms@kernel.org>
To: Ivan Vecera <ivecera@redhat.com>
Cc: netdev@vger.kernel.org,
Prathosh Satish <Prathosh.Satish@microchip.com>,
Vadim Fedorenko <vadim.fedorenko@linux.dev>,
Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
Jiri Pirko <jiri@resnulli.us>, Paolo Abeni <pabeni@redhat.com>,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH net] dpll: zl3073x: fix REF_PHASE_OFFSET_COMP register width for some chip IDs
Date: Mon, 23 Feb 2026 17:50:41 +0000 [thread overview]
Message-ID: <aZyTcWMAIzVOSz09@horms.kernel.org> (raw)
In-Reply-To: <20260220155755.448185-1-ivecera@redhat.com>
On Fri, Feb 20, 2026 at 04:57:54PM +0100, Ivan Vecera wrote:
> The REF_PHASE_OFFSET_COMP register is 48-bit wide on most zl3073x chip
> variants, but only 32-bit wide on chip IDs 0x0E30, 0x0E93..0x0E97 and
> 0x1F60. The driver unconditionally uses 48-bit read/write operations,
> which on 32-bit variants causes reading 2 bytes past the register
> boundary (corrupting the value) and writing 2 bytes into the adjacent
> register.
>
> Fix this by storing the chip ID in the device structure during probe
> and adding a helper to detect the affected variants. Use the correct
> register width for read/write operations and the matching sign extension
> bit (31 vs 47) when interpreting the phase compensation value.
>
> Fixes: 6287262f761e ("dpll: zl3073x: Add support to adjust phase")
> Signed-off-by: Ivan Vecera <ivecera@redhat.com>
Reviewed-by: Simon Horman <horms@kernel.org>
next prev parent reply other threads:[~2026-02-23 17:50 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-20 15:57 [PATCH net] dpll: zl3073x: fix REF_PHASE_OFFSET_COMP register width for some chip IDs Ivan Vecera
2026-02-23 17:50 ` Simon Horman [this message]
2026-02-24 1:40 ` patchwork-bot+netdevbpf
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