From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from vps0.lunn.ch (vps0.lunn.ch [156.67.10.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D44019AD5C; Sun, 3 May 2026 03:50:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=156.67.10.101 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777780251; cv=none; b=J+VDqeCTUPuJI/jaL/5GM7yy0Aure9RMK78R9s8c6/+mjecghRPZuILPJ877X8UuQyD3VvErI9JlTE9VsARqSzRLjX/KtZCmVCMKs/JPPUJ37jkmNi6bxabNdpwJhCit/kC2euVlYUKwYHmLjOd5ziNaPvt1lxzC7xA7CT/rze8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777780251; c=relaxed/simple; bh=KkhqH+enIGlDSe9wpYpqRmRgrfu9Qk/ZTE4eris/8Sc=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=YNSbYWA2lfHLDsEevH6fAZSuPSOSiXibqJSsR7Q5xc7Ycw9EvLDnGHS2YB7jSnq3FvmZSiGRECCUvJCgrv+gi8uOA1bKNUO7aEvymevVoRWZBzHqVuinSp/bfEAw7UbTHR4/db5Tyrd/VfcupjQB19xHfboQjMCV0WhKyMaE6I0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch; spf=pass smtp.mailfrom=lunn.ch; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b=j1MpHy9V; arc=none smtp.client-ip=156.67.10.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lunn.ch Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="j1MpHy9V" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=KLkq4GgpHcZIZ9V0bLeLbrvyjtYFqPx7kxg5KQcjpck=; b=j1MpHy9V5i9l9+BKoELUgjp6g/ WACT0v4chUJ+WkillWjstNQgm7aq+y7Ch3mJaDf72tq5dD+BBAhL6Q2lQ24dWPXyOj+fTWG3aflJX DMOOMZiyegGm/dozODK+0GgW79Gv61zhMF3JHMRh9VeSn8zk48pRJmtW3KZ16OngQcZw=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1wJNqm-0015PB-20; Sun, 03 May 2026 05:50:36 +0200 Date: Sun, 3 May 2026 05:50:36 +0200 From: Andrew Lunn To: ciprian.regus@analog.com Cc: Parthiban Veerasooran , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Jonathan Corbet , Shuah Khan , Heiner Kallweit , Russell King , Rob Herring , Krzysztof Kozlowski , Conor Dooley , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH net-next 2/5] net: ethernet: oa_tc6: Allow custom mii_bus Message-ID: References: <20260503-adin1140-driver-v1-0-dd043cdd88f0@analog.com> <20260503-adin1140-driver-v1-2-dd043cdd88f0@analog.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260503-adin1140-driver-v1-2-dd043cdd88f0@analog.com> > @@ -538,32 +539,37 @@ static int oa_tc6_mdiobus_register(struct oa_tc6 *tc6) > { > int ret; > > - tc6->mdiobus = mdiobus_alloc(); > if (!tc6->mdiobus) { > - netdev_err(tc6->netdev, "MDIO bus alloc failed\n"); > - return -ENOMEM; > + tc6->mdiobus = mdiobus_alloc(); > + if (!tc6->mdiobus) { > + netdev_err(tc6->netdev, "MDIO bus alloc failed\n"); > + return -ENOMEM; > + } > + > + tc6->mdiobus->read = oa_tc6_mdiobus_read; > + tc6->mdiobus->write = oa_tc6_mdiobus_write; > + /* OPEN Alliance 10BASE-T1x compliance MAC-PHYs will have both C22 and > + * C45 registers space. If the PHY is discovered via C22 bus protocol it > + * assumes it uses C22 protocol and always uses C22 registers indirect > + * access to access C45 registers. This is because, we don't have a > + * clean separation between C22/C45 register space and C22/C45 MDIO bus > + * protocols. Resulting, PHY C45 registers direct access can't be used > + * which can save multiple SPI bus access. To support this feature, PHY > + * drivers can set .read_mmd/.write_mmd in the PHY driver to call > + * .read_c45/.write_c45. Ex: drivers/net/phy/microchip_t1s.c > + */ > + tc6->mdiobus->read_c45 = oa_tc6_mdiobus_read_c45; > + tc6->mdiobus->write_c45 = oa_tc6_mdiobus_write_c45; > + > + tc6->own_mdiobus = true; > } > > tc6->mdiobus->priv = tc6; > - tc6->mdiobus->read = oa_tc6_mdiobus_read; > - tc6->mdiobus->write = oa_tc6_mdiobus_write; > - /* OPEN Alliance 10BASE-T1x compliance MAC-PHYs will have both C22 and > - * C45 registers space. If the PHY is discovered via C22 bus protocol it > - * assumes it uses C22 protocol and always uses C22 registers indirect > - * access to access C45 registers. This is because, we don't have a > - * clean separation between C22/C45 register space and C22/C45 MDIO bus > - * protocols. Resulting, PHY C45 registers direct access can't be used > - * which can save multiple SPI bus access. To support this feature, PHY > - * drivers can set .read_mmd/.write_mmd in the PHY driver to call > - * .read_c45/.write_c45. Ex: drivers/net/phy/microchip_t1s.c > - */ > - tc6->mdiobus->read_c45 = oa_tc6_mdiobus_read_c45; > - tc6->mdiobus->write_c45 = oa_tc6_mdiobus_write_c45; > - tc6->mdiobus->name = "oa-tc6-mdiobus"; > tc6->mdiobus->parent = tc6->dev; > + tc6->mdiobus->name = "oa-tc6-mdiobus"; > > snprintf(tc6->mdiobus->id, ARRAY_SIZE(tc6->mdiobus->id), "%s", > - dev_name(&tc6->spi->dev)); > + dev_name(&tc6->spi->dev)); > > ret = mdiobus_register(tc6->mdiobus); > if (ret) { > @@ -577,19 +583,30 @@ static int oa_tc6_mdiobus_register(struct oa_tc6 *tc6) > > static void oa_tc6_mdiobus_unregister(struct oa_tc6 *tc6) > { > + if (!tc6->mdiobus) > + return; > + > mdiobus_unregister(tc6->mdiobus); > - mdiobus_free(tc6->mdiobus); > + > + if (tc6->own_mdiobus) > + mdiobus_free(tc6->mdiobus); > } > > static int oa_tc6_phy_init(struct oa_tc6 *tc6) > { > int ret; > > - ret = oa_tc6_check_phy_reg_direct_access_capability(tc6); > - if (ret) { > - netdev_err(tc6->netdev, > - "Direct PHY register access is not supported by the MAC-PHY\n"); > - return ret; > + /* If the driver provided a mii_bus, it is also responsible for > + * implementing the bus access methods, so we don't have to worry > + * about checking the PHY access mode. > + */ > + if (!tc6->mdiobus) { > + ret = oa_tc6_check_phy_reg_direct_access_capability(tc6); > + if (ret) { > + netdev_err(tc6->netdev, > + "Direct PHY register access is not supported by the MAC-PHY\n"); > + return ret; > + } This all seems pretty invasive and ugly. Please could you think what happens if instead of passing in an mdiobus, you pass a phydev. Is the change to the core simpler and cleaner? Andrew