[PATCH net-next 0/2] Introduce Airoha AN8801R series Gigabit Ethernet PHY driver

[PATCH net-next 0/2] Introduce Airoha AN8801R series Gigabit Ethernet PHY driver

[Louis-Alexis Eyraud]

This series introduces the Airoha AN8801R Gigabit Ethernet PHY initial
support.

The Airoha AN8801R is a low power single-port Ethernet PHY Transceiver
with Single-port serdes interface for 1000Base-X/RGMII.
This chip is compliant with 10Base-T, 100Base-TX and 1000Base-T IEEE
802.3(u,ab) and supports:
  - Energy Efficient Ethernet (802.3az)
  - Full Duplex Control Flow (802.3x)
  - auto-negotiation
  - crossover detect and autocorrection,
  - Wake-on-LAN with Magic Packet
  - Jumbo Frame up to 9 Kilobytes.
This PHY also supports up to three user-configurable LEDs, which are
usually used for LAN Activity, 100M, 1000M indication.

The series provides the devicetree binding and the driver that have been
written by AngeloGioacchino Del Regno, based on downstream
implementation ([1]). The driver allows setting up PHY LEDs, 10/100M,
1000M speeds, and Wake on LAN and PHY interrupts.

The series is based on net-next kernel tree (sha1: ed0abfe93fd1) and
I have tested it on Mediatek Genio 720-EVK board (that integrates an
Airoha AN8801RIN/A Ethernet PHY) with early board hardware enablement
patches.

[1]: https://gitlab.com/mediatek/aiot/bsp/linux/-/blob/mtk-v6.6/drivers/net/phy/an8801.c

Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
AngeloGioacchino Del Regno (2):
      dt-bindings: net: Add support for Airoha AN8801/R GbE PHY
      net: phy: Introduce Airoha AN8801/R Gigabit Ethernet PHY driver

 .../devicetree/bindings/net/airoha,an8801.yaml     |   81 ++
 drivers/net/phy/Kconfig                            |    5 +
 drivers/net/phy/Makefile                           |    1 +
 drivers/net/phy/air_an8801.c                       | 1059 ++++++++++++++++++++
 4 files changed, 1146 insertions(+)
---
base-commit: ed0abfe93fd135dac223e87a3c945017b1fa8bfc
change-id: 20260303-add-airoha-an8801-support-57d544a4afed

Best regards,
-- 
Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>

[PATCH net-next 1/2] dt-bindings: net: Add support for Airoha AN8801/R GbE PHY

[Louis-Alexis Eyraud]

From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Add a new binding to support the Airoha AN8801R Series Gigabit
Ethernet PHY.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
 .../devicetree/bindings/net/airoha,an8801.yaml     | 81 ++++++++++++++++++++++
 1 file changed, 81 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/airoha,an8801.yaml b/Documentation/devicetree/bindings/net/airoha,an8801.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..f251c9d2fbbed3675c9fd7ff22174049a13a7b5e
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/airoha,an8801.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/airoha,an8801.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha AN8801R Series PHY
+
+maintainers:
+  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+
+description:
+  The Airoha AN8801R is a low power single-port Ethernet PHY Transceiver
+  with Single-port serdes interface for 1000Base-X/RGMII; this chip is
+  compliant with 10Base-T, 100Base-TX and 1000Base-T IEEE 802.3(u,ab)
+  and supports Energy Efficient Ethernet (802.3az), Full Duplex Control
+  Flow (802.3x), auto-negotiation, crossover detect and autocorrection,
+  Wake-on-LAN with Magic Packet, and Jumbo Frame up to 9 Kilobytes.
+  This PHY also supports up to three user-configurable LEDs, which are
+  usually used for LAN Activity, 100M, 1000M indication.
+
+allOf:
+  - $ref: ethernet-phy.yaml#
+
+properties:
+  compatible:
+    enum:
+      - ethernet-phy-idc0ff.0421
+
+  reg:
+    maxItems: 1
+
+  leds: true
+
+required:
+  - reg
+  - leds
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/leds/common.h>
+
+    mdio {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        ethernet-phy@0 {
+            compatible = "ethernet-phy-idc0ff.0421";
+            reg = <0>;
+
+            leds {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                led@0 {
+                    reg = <0>;
+                    color = <LED_COLOR_ID_GREEN>;
+                    function = LED_FUNCTION_LAN;
+                    default-state = "keep";
+                };
+
+                led@1 {
+                    reg = <1>;
+                    color = <LED_COLOR_ID_GREEN>;
+                    function = LED_FUNCTION_LAN;
+                    function-enumerator = <1>;
+                    default-state = "keep";
+                };
+
+                led@2 {
+                    reg = <2>;
+                    color = <LED_COLOR_ID_YELLOW>;
+                    function = LED_FUNCTION_LAN;
+                    function-enumerator = <2>;
+                    default-state = "keep";
+                };
+            };
+        };
+    };

-- 
2.53.0

Re: [PATCH net-next 1/2] dt-bindings: net: Add support for Airoha AN8801/R GbE PHY

[Maxime Chevallier]

Hi Louis-Alexis,

On 04/03/2026 10:35, Louis-Alexis Eyraud wrote:
> From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> 
> Add a new binding to support the Airoha AN8801R Series Gigabit
> Ethernet PHY.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
> ---
>  .../devicetree/bindings/net/airoha,an8801.yaml     | 81 ++++++++++++++++++++++
>  1 file changed, 81 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/net/airoha,an8801.yaml b/Documentation/devicetree/bindings/net/airoha,an8801.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..f251c9d2fbbed3675c9fd7ff22174049a13a7b5e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/airoha,an8801.yaml
> @@ -0,0 +1,81 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/airoha,an8801.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Airoha AN8801R Series PHY
> +
> +maintainers:
> +  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> +
> +description:
> +  The Airoha AN8801R is a low power single-port Ethernet PHY Transceiver
> +  with Single-port serdes interface for 1000Base-X/RGMII; this chip is
> +  compliant with 10Base-T, 100Base-TX and 1000Base-T IEEE 802.3(u,ab)
> +  and supports Energy Efficient Ethernet (802.3az), Full Duplex Control
> +  Flow (802.3x), auto-negotiation, crossover detect and autocorrection,
> +  Wake-on-LAN with Magic Packet, and Jumbo Frame up to 9 Kilobytes.
> +  This PHY also supports up to three user-configurable LEDs, which are
> +  usually used for LAN Activity, 100M, 1000M indication.
> +
> +allOf:
> +  - $ref: ethernet-phy.yaml#
> +
> +properties:
> +  compatible:
> +    enum:
> +      - ethernet-phy-idc0ff.0421
> +
> +  reg:
> +    maxItems: 1
> +
> +  leds: true
> +
> +required:
> +  - reg
> +  - leds

Seems odd to me that leds are required. Any reason for that ?

Maxime

Re: [PATCH net-next 1/2] dt-bindings: net: Add support for Airoha AN8801/R GbE PHY

[Louis-Alexis Eyraud]

Hi Maxime,

On Wed, 2026-03-04 at 11:14 +0100, Maxime Chevallier wrote:
> Hi Louis-Alexis,
> 
> On 04/03/2026 10:35, Louis-Alexis Eyraud wrote:
> > From: AngeloGioacchino Del Regno
> > <angelogioacchino.delregno@collabora.com>
> > 
> > Add a new binding to support the Airoha AN8801R Series Gigabit
> > Ethernet PHY.
> > 
> > Signed-off-by: AngeloGioacchino Del Regno
> > <angelogioacchino.delregno@collabora.com>
> > Signed-off-by: Louis-Alexis Eyraud
> > <louisalexis.eyraud@collabora.com>
> > ---
> >  .../devicetree/bindings/net/airoha,an8801.yaml     | 81
> > ++++++++++++++++++++++
> >  1 file changed, 81 insertions(+)
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/net/airoha,an8801.yaml
> > b/Documentation/devicetree/bindings/net/airoha,an8801.yaml
> > new file mode 100644
> > index
> > 0000000000000000000000000000000000000000..f251c9d2fbbed3675c9fd7ff2
> > 2174049a13a7b5e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/net/airoha,an8801.yaml
> > @@ -0,0 +1,81 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/net/airoha,an8801.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Airoha AN8801R Series PHY
> > +
> > +maintainers:
> > +  - AngeloGioacchino Del Regno
> > <angelogioacchino.delregno@collabora.com>
> > +
> > +description:
> > +  The Airoha AN8801R is a low power single-port Ethernet PHY
> > Transceiver
> > +  with Single-port serdes interface for 1000Base-X/RGMII; this
> > chip is
> > +  compliant with 10Base-T, 100Base-TX and 1000Base-T IEEE
> > 802.3(u,ab)
> > +  and supports Energy Efficient Ethernet (802.3az), Full Duplex
> > Control
> > +  Flow (802.3x), auto-negotiation, crossover detect and
> > autocorrection,
> > +  Wake-on-LAN with Magic Packet, and Jumbo Frame up to 9
> > Kilobytes.
> > +  This PHY also supports up to three user-configurable LEDs, which
> > are
> > +  usually used for LAN Activity, 100M, 1000M indication.
> > +
> > +allOf:
> > +  - $ref: ethernet-phy.yaml#
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - ethernet-phy-idc0ff.0421
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  leds: true
> > +
> > +required:
> > +  - reg
> > +  - leds
> 
> Seems odd to me that leds are required. Any reason for that ?
> 
> Maxime
I agree having the leds as required property is unneeded.
I'll change it in v2.

Regards,
Louis-Alexis

Re: [PATCH net-next 1/2] dt-bindings: net: Add support for Airoha AN8801/R GbE PHY

[Rob Herring (Arm)]

On Wed, 04 Mar 2026 10:35:28 +0100, Louis-Alexis Eyraud wrote:
> From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> 
> Add a new binding to support the Airoha AN8801R Series Gigabit
> Ethernet PHY.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
> ---
>  .../devicetree/bindings/net/airoha,an8801.yaml     | 81 ++++++++++++++++++++++
>  1 file changed, 81 insertions(+)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH net-next 2/2] net: phy: Introduce Airoha AN8801/R Gigabit Ethernet PHY driver

[Louis-Alexis Eyraud]

From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Introduce a driver for the Airoha AN8801R Series Gigabit Ethernet
PHY; this currently supports setting up PHY LEDs, 10/100M, 1000M
speeds, and Wake on LAN and PHY interrupts.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
 drivers/net/phy/Kconfig      |    5 +
 drivers/net/phy/Makefile     |    1 +
 drivers/net/phy/air_an8801.c | 1059 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 1065 insertions(+)

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 7b73332a13d9520582fb45780528de4e17496f5e..53f451479509b7c11999beaf91ae08ed4ed01e86 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -96,6 +96,11 @@ config AS21XXX_PHY
 	  AS21210PB1 that all register with the PHY ID 0x7500 0x7500
 	  before the firmware is loaded.
 
+config AIR_AN8801_PHY
+	tristate "Airoha AN8801 Gigabit PHY"
+	help
+	  Currently supports the Airoha AN8801R PHY.
+
 config AIR_EN8811H_PHY
 	tristate "Airoha EN8811H 2.5 Gigabit PHY"
 	select PHY_COMMON_PROPS
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 3a34917adea72d03342a8a4ef703ee5d087d229e..83516da36c9ffa4e3b077717e9fc375e38ab2ea5 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -29,6 +29,7 @@ obj-y				+= $(sfp-obj-y) $(sfp-obj-m)
 
 obj-$(CONFIG_ADIN_PHY)		+= adin.o
 obj-$(CONFIG_ADIN1100_PHY)	+= adin1100.o
+obj-$(CONFIG_AIR_AN8801_PHY)	+= air_an8801.o
 obj-$(CONFIG_AIR_EN8811H_PHY)   += air_en8811h.o
 obj-$(CONFIG_AMD_PHY)		+= amd.o
 obj-$(CONFIG_AMCC_QT2025_PHY)	+= qt2025.o
diff --git a/drivers/net/phy/air_an8801.c b/drivers/net/phy/air_an8801.c
new file mode 100644
index 0000000000000000000000000000000000000000..86828c7d9716ee45832483d74f01f2764fcda408
--- /dev/null
+++ b/drivers/net/phy/air_an8801.c
@@ -0,0 +1,1059 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for the Airoha AN8801 Gigabit PHY.
+ *
+ * Copyright (C) 2025 Airoha Technology Corp.
+ * Copyright (C) 2025 Collabora Ltd.
+ *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/of.h>
+#include <linux/phy.h>
+
+#define AN8801R_PHY_ID			0xc0ff0421
+
+/* MII Registers */
+#define AIR_EXT_PAGE_ACCESS		0x1f
+#define   AIR_PHY_PAGE_STANDARD		0
+#define   AIR_PHY_PAGE_EXTENDED_1	1
+#define   AIR_PHY_PAGE_EXTENDED_4	4
+
+/* MII Registers - Airoha Page 1 */
+#define AN8801_EXT_REG_PHY		0x14
+#define   AN8801_EXT_PHY_STATUS0	GENMASK(1, 0)
+#define   AN8801_EXT_PHY_DOWNSHIFT_CTL	GENMASK(3, 2) /* 2 to 5 1G auto-neg attempts (0..3) */
+#define   AN8801_EXT_PHY_DOWNSHIFT_EN	BIT(4)
+#define   AN8801_EXT_PHY_CTRL0		BIT(5)
+#define   AN8801_EXT_PHY_STATUS1	GENMASK(8, 6)
+#define   AN8801_EXT_PHY_CTRL1		GENMASK(14, 9)
+
+/* MII Registers - Airoha Page 4 */
+#define AN8801_PBUS_ACCESS		BIT(28)
+#define AN8801_PBUS_EPHY_ACCESS		BIT(24)
+#define AN8801_PBUS_CL22_ACCESS		BIT(23)
+
+#define AIR_BPBUS_MODE			0x10
+#define AIR_BPBUS_WR_ADDR_HIGH		0x11
+#define AIR_BPBUS_WR_ADDR_LOW		0x12
+#define AIR_BPBUS_WR_DATA_HIGH		0x13
+#define AIR_BPBUS_WR_DATA_LOW		0x14
+#define AIR_BPBUS_RD_ADDR_HIGH		0x15
+#define AIR_BPBUS_RD_ADDR_LOW		0x16
+#define AIR_BPBUS_RD_DATA_HIGH		0x17
+#define AIR_BPBUS_RD_DATA_LOW		0x18
+
+/* BPBUS Registers */
+#define AN8801_BPBUS_REG_LED_GPIO	0x54
+#define AN8801_BPBUS_REG_LED_ID_SEL	0x58
+#define   LED_ID_GPIO_SEL(led, gpio)	((led) << ((gpio) * 3))
+#define AN8801_BPBUS_REG_GPIO_MODE	0x70
+#define AN8801_BPBUS_REG_PHY_IRQ_GPIO	0x7c
+#define   AN8801_PHY_IRQ_GPIO_NUM_MASK	GENMASK(19, 16)
+#define   AN8801_PHY_IRQ_GPIO_NUM	1
+
+#define AN8801_BPBUS_REG_CKO		0x1a4
+#define AN8801_CKO_OUTPUT_MODE_AUTO	3
+
+#define AN8801_BPBUS_REG_LINK_MODE	0x5054
+#define  AN8801_BPBUS_LINK_MODE_1000	BIT(0)
+
+#define AN8801_BPBUS_REG_BYPASS_PTP	0x21c004
+#define   AN8801_BYP_PTP_SGMII_TO_GPHY	BIT(8)
+#define   AN8801_BYP_PTP_RGMII_TO_GPHY	BIT(0)
+
+#define AN8801_BPBUS_REG_TXDLY_STEP	0x21c024
+#define   RGMII_DELAY_STEP_MASK		GENMASK(2, 0)
+#define   RGMII_TXDELAY_FORCE_MODE	BIT(24)
+
+#define AN8801_BPBUS_REG_RXDLY_STEP	0x21c02c
+#define   RGMII_RXDELAY_ALIGN		BIT(4)
+#define   RGMII_RXDELAY_FORCE_MODE	BIT(24)
+
+#define AN8801_BPBUS_REG_EFIFO_CTL(x)	(0x270004 + (0x100 * (x))) /* 0..2 */
+#define   AN8801_EFIFO_ALL_EN		GENMASK(7, 0)
+#define   AN8801_EFIFO_RX_EN		BIT(0)
+#define   AN8801_EFIFO_TX_EN		BIT(1)
+#define   AN8801_EFIFO_RX_CLK_EN	BIT(2)
+#define   AN8801_EFIFO_TX_CLK_EN	BIT(3)
+#define   AN8801_EFIFO_RX_EEE_EN	BIT(4)
+#define   AN8801_EFIFO_TX_EEE_EN	BIT(5)
+#define   AN8801_EFIFO_RX_ODD_NIBBLE_EN	BIT(6)
+#define   AN8801_EFIFO_TX_ODD_NIBBLE_EN	BIT(7)
+
+#define AN8801_BPBUS_REG_WOL_MAC_16_47	0x285114
+#define AN8801_BPBUS_REG_WOL_MAC_0_15	0x285118
+
+#define AN8801_BPBUS_REG_WAKEUP_CTL1	0x285400
+#define   AN8801_WOL_WAKE_MAGIC_EN	GENMASK(3, 1)
+
+#define AN8801_BPBUS_REG_WAKEUP_CTL2	0x285404
+#define   AN8801_WAKE_OUT_TYPE_PULSE	BIT(0) /* Set/Unset: Pulse/Static */
+#define   AN8801_WAKE_OUT_POLARITY_NEG	BIT(1) /* Set/Unset: Negative/Positive */
+#define   AN8801_WAKE_OUT_WIDTH		GENMASK(2, 3)
+#define    AN8801_WAKE_OUT_84MS		0
+#define    AN8801_WAKE_OUT_168MS	1
+#define    AN8801_WAKE_OUT_336MS	2
+#define    AN8801_WAKE_OUT_672MS	3
+#define   AN8801_WAKE_OUT_EN		BIT(4)
+#define   AN8801_PME_WAKEUP_CLR		BIT(8)
+
+#define AN8801_BPBUS_REG_WAKE_IRQ_EN	0x285700
+#define AN8801_BPBUS_REG_WAKE_IRQ_STS	0x285704
+#define   AN8801_IRQ_WAKE_LNKCHG	BIT(0) /* Wake on link change */
+#define   AN8801_IRQ_WAKE_UNIPKT	BIT(1) /* Wake on unicast packet */
+#define   AN8801_IRQ_WAKE_MULPKT	BIT(2) /* Wake on multicast packet */
+#define   AN8801_IRQ_WAKE_BCPKT		BIT(3) /* Wake on broadcast packet */
+#define   AN8801_IRQ_WAKE_MAGICPKT	BIT(4) /* Wake on magic packet */
+#define   AN8801_IRQ_WAKE_ALL		GENMASK(4, 0)
+
+/* MDIO_MMD_VEND1 Registers */
+#define AN8801_PHY_TX_PAIR_DLY_SEL_GBE	0x13
+#define   AN8801_PHY_PAIR_DLY_SEL_A_GBE	GENMASK(14, 12)
+#define   AN8801_PHY_PAIR_DLY_SEL_B_GBE	GENMASK(10, 8)
+#define   AN8801_PHY_PAIR_DLY_SEL_C_GBE	GENMASK(6, 4)
+#define   AN8801_PHY_PAIR_DLY_SEL_D_GBE	GENMASK(2, 0)
+#define AN8801_PHY_RXADC_CTRL		0xd8
+#define   AN8801_PHY_RXADC_SAMP_PHSEL_A	BIT(12)
+#define   AN8801_PHY_RXADC_SAMP_PHSEL_B	BIT(8)
+#define   AN8801_PHY_RXADC_SAMP_PHSEL_C	BIT(4)
+#define   AN8801_PHY_RXADC_SAMP_PHSEL_D	BIT(0)
+#define AN8801_PHY_RXADC_REV_0		0xd9
+#define   AN8801_PHY_RXADC_REV_MASK_A	GENMASK(15, 8)
+#define   AN8801_PHY_RXADC_REV_MASK_B	GENMASK(7, 0)
+#define AN8801_PHY_RXADC_REV_1		0xda
+#define   AN8801_PHY_RXADC_REV_MASK_C	GENMASK(15, 8)
+#define   AN8801_PHY_RXADC_REV_MASK_D	GENMASK(7, 0)
+
+/* MDIO_MMD_VEND2 Registers */
+#define LED_BCR				0x21
+#define   LED_BCR_MODE_MASK		GENMASK(1, 0)
+#define   LED_BCR_TIME_TEST		BIT(2)
+#define   LED_BCR_CLK_EN		BIT(3)
+#define   LED_BCR_EVT_ALL		BIT(4)
+#define   LED_BCR_EXT_CTRL		BIT(15)
+#define   LED_BCR_MODE_DISABLE		0
+#define   LED_BCR_MODE_2LED		1
+#define   LED_BCR_MODE_3LED_1		2
+#define   LED_BCR_MODE_3LED_2		3
+
+#define LED_ON_DUR			0x22
+#define   LED_ON_DUR_MASK		GENMASK(15, 0)
+
+#define LED_BLINK_DUR			0x23
+#define   LED_BLINK_DUR_MASK		GENMASK(15, 0)
+
+#define LED_ON_CTRL(i)			(0x24 + ((i) * 2))
+#define   LED_ON_EVT_MASK		GENMASK(6, 0)
+#define   LED_ON_EVT_LINK_1000M		BIT(0)
+#define   LED_ON_EVT_LINK_100M		BIT(1)
+#define   LED_ON_EVT_LINK_10M		BIT(2)
+#define   LED_ON_EVT_LINK_DN		BIT(3)
+#define   LED_ON_EVT_FDX		BIT(4)
+#define   LED_ON_EVT_HDX		BIT(5)
+#define   LED_ON_EVT_FORCE		BIT(6)
+#define   LED_ON_POL			BIT(14)
+#define   LED_ON_EN			BIT(15)
+
+#define LED_BLINK_CTRL(i)		(0x25 + ((i) * 2))
+#define LED_BLINK_EVT_MASK		GENMASK(9, 0)
+#define LED_BLINK_EVT_1000M_TX		BIT(0)
+#define LED_BLINK_EVT_1000M_RX		BIT(1)
+#define LED_BLINK_EVT_100M_TX		BIT(2)
+#define LED_BLINK_EVT_100M_RX		BIT(3)
+#define LED_BLINK_EVT_10M_TX		BIT(4)
+#define LED_BLINK_EVT_10M_RX		BIT(5)
+#define LED_BLINK_EVT_COLLISION		BIT(6)
+#define LED_BLINK_EVT_RX_CRC_ERR	BIT(7)
+#define LED_BLINK_EVT_RX_IDLE_ERR	BIT(8)
+#define LED_BLINK_EVT_FORCE		BIT(9)
+
+#define AN8801R_NUM_LEDS		3
+#define AN8801_PERIOD_SHIFT		15
+#define AN8801_PERIOD_UNIT		32768 /* (1 << AN8801_PERIOD_SHIFT) */
+#define AN8801_MAX_PERIOD_MS		2147
+
+#define LED_BLINK_DURATION_UNIT		780
+#define LED_BLINK_DURATION(f)		(LED_BLINK_DURATION_UNIT << (f))
+
+#define AN8801_LED_DURATION_UNIT_US	32768
+
+#define AN8801_REG_PHY_INTERNAL0	0x600
+#define AN8801_REG_PHY_INTERNAL1	0x601
+#define   AN8801_PHY_INTFUNC_MASK	GENMASK(15, 0) /* PHY internal functions */
+
+enum an8801r_led_fn {
+	AN8801R_LED_FN_NONE,
+	AN8801R_LED_FN_LINK,
+	AN8801R_LED_FN_ACTIVITY,
+	AN8801R_LED_FN_MAX,
+};
+
+static int an8801r_read_page(struct phy_device *phydev)
+{
+	return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
+}
+
+static int an8801r_write_page(struct phy_device *phydev, int page)
+{
+	return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
+}
+
+static int __air_buckpbus_reg_write(struct phy_device *phydev,
+				    u32 addr, u32 data)
+{
+	int ret;
+
+	addr |= AN8801_PBUS_ACCESS;
+
+	ret = __phy_write(phydev, AIR_BPBUS_MODE, MII_MMD_CTRL_ADDR);
+	if (ret < 0)
+		return ret;
+
+	ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH, upper_16_bits(addr));
+	if (ret < 0)
+		return ret;
+
+	ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW, lower_16_bits(addr));
+	if (ret < 0)
+		return ret;
+
+	ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH, upper_16_bits(data));
+	if (ret < 0)
+		return ret;
+
+	ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW, lower_16_bits(data));
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static int __air_buckpbus_reg_read(struct phy_device *phydev,
+				   u32 addr, u32 *data)
+{
+	int pbus_data_l, pbus_data_h;
+	int ret;
+
+	addr |= AN8801_PBUS_ACCESS;
+
+	ret = __phy_write(phydev, AIR_BPBUS_MODE, MII_MMD_CTRL_ADDR);
+	if (ret < 0)
+		return ret;
+
+	ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH, upper_16_bits(addr));
+	if (ret < 0)
+		return ret;
+
+	ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW, lower_16_bits(addr));
+	if (ret < 0)
+		return ret;
+
+	ret = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
+	if (pbus_data_h < 0)
+		return pbus_data_h;
+
+	pbus_data_l = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
+	if (pbus_data_l < 0)
+		return pbus_data_l;
+
+	*data = (pbus_data_h << 16) | pbus_data_l;
+	return 0;
+}
+
+static int air_buckpbus_reg_rmw(struct phy_device *phydev,
+				u32 addr, u32 mask, u32 set)
+{
+	u32 data_old, data_new;
+	int prev_page, ret;
+
+	prev_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
+	if (prev_page < 0)
+		return prev_page;
+
+	ret = __air_buckpbus_reg_read(phydev, addr, &data_old);
+	if (ret)
+		return phy_restore_page(phydev, prev_page, ret);
+
+	data_new = data_old & ~mask;
+	data_new |= set;
+	if (data_new != data_old)
+		ret = __air_buckpbus_reg_write(phydev, addr, data_new);
+
+	return phy_restore_page(phydev, prev_page, ret);
+}
+
+static int air_buckpbus_reg_set_bits(struct phy_device *phydev,
+				     u32 addr, u32 mask)
+{
+	return air_buckpbus_reg_rmw(phydev, addr, mask, mask);
+}
+
+static int air_buckpbus_reg_clear_bits(struct phy_device *phydev,
+				       u32 addr, u32 mask)
+{
+	return air_buckpbus_reg_rmw(phydev, addr, mask, 0);
+}
+
+static int air_buckpbus_reg_write(struct phy_device *phydev, u32 addr, u32 data)
+{
+	int prev_page, ret = 0;
+
+	prev_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
+	if (prev_page < 0)
+		return prev_page;
+
+	ret = __air_buckpbus_reg_write(phydev, addr, data);
+
+	return phy_restore_page(phydev, prev_page, ret);
+}
+
+static int air_buckpbus_reg_read(struct phy_device *phydev, u32 addr, u32 *data)
+{
+	int prev_page, ret;
+
+	prev_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
+	if (prev_page < 0)
+		return prev_page;
+
+	ret = __air_buckpbus_reg_read(phydev, addr, data);
+
+	return phy_restore_page(phydev, prev_page, ret);
+}
+
+static u32 an8801r_led_blink_ms_to_hw(unsigned long req_ms)
+{
+	u32 req_ns, regval;
+
+	if (req_ms > AN8801_MAX_PERIOD_MS)
+		req_ms = AN8801_MAX_PERIOD_MS;
+
+	req_ns = req_ms * 1000000;
+
+	/* Round to the nearest period unit... */
+	regval = req_ns + (AN8801_PERIOD_UNIT / 2);
+
+	/* ...and now divide by the full period */
+	regval >>= AN8801_PERIOD_SHIFT;
+
+	return regval;
+}
+
+static int an8801r_led_blink_set(struct phy_device *phydev, u8 index,
+				 unsigned long *delay_on,
+				 unsigned long *delay_off)
+{
+	u32 hw_delay_on, hw_delay_off;
+	bool blink;
+	int ret;
+
+	if (index >= AN8801R_NUM_LEDS)
+		return -EINVAL;
+
+	if (delay_on && delay_off) {
+		blink = true;
+
+		if (*delay_on == 0 || *delay_off == 0) {
+			*delay_on = 64;
+			*delay_off = 64;
+		}
+
+		hw_delay_on = an8801r_led_blink_ms_to_hw(*delay_on);
+		hw_delay_off = an8801r_led_blink_ms_to_hw(*delay_off);
+	} else {
+		blink = false;
+	}
+
+	if (blink) {
+		ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_DUR,
+				    LED_BLINK_DURATION(hw_delay_on));
+		if (ret)
+			goto error;
+
+		ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LED_ON_DUR,
+				    LED_BLINK_DURATION(hw_delay_off) >> 1);
+		if (ret)
+			goto error;
+	}
+
+	ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+			     LED_ON_EN, blink ? LED_ON_EN : 0);
+	if (ret)
+		return ret;
+
+	return 0;
+error:
+	phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+		       LED_ON_EN, 0);
+	return ret;
+}
+
+static int an8801r_led_brightness_set(struct phy_device *phydev, u8 index,
+				      enum led_brightness value)
+{
+	int ret;
+
+	if (index >= AN8801R_NUM_LEDS)
+		return -EINVAL;
+
+	ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+			     LED_ON_EVT_MASK,
+			     (value == LED_OFF) ? 0 : LED_ON_EVT_FORCE);
+	if (ret)
+		return ret;
+
+	return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+			      LED_ON_EN, (value == LED_OFF) ? 0 : LED_ON_EN);
+}
+
+static int an8801r_led_hw_control_get(struct phy_device *phydev, u8 index,
+				      unsigned long *rules)
+{
+	int on, blink;
+
+	on = phy_read_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index));
+	if (on < 0)
+		return on;
+
+	blink = phy_read_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_CTRL(index));
+	if (blink < 0)
+		return blink;
+
+	if (FIELD_GET(LED_ON_EVT_LINK_10M, on))
+		__set_bit(TRIGGER_NETDEV_LINK_10, rules);
+
+	if (FIELD_GET(LED_ON_EVT_LINK_100M, on))
+		__set_bit(TRIGGER_NETDEV_LINK_100, rules);
+
+	if (FIELD_GET(LED_ON_EVT_LINK_1000M, on))
+		__set_bit(TRIGGER_NETDEV_LINK_1000, rules);
+
+	if (FIELD_GET(LED_ON_EVT_LINK_10M, on) &&
+	    FIELD_GET(LED_ON_EVT_LINK_100M, on) &&
+	    FIELD_GET(LED_ON_EVT_LINK_1000M, on))
+		__set_bit(TRIGGER_NETDEV_LINK, rules);
+
+	if (FIELD_GET(LED_BLINK_EVT_10M_RX, blink) ||
+	    FIELD_GET(LED_BLINK_EVT_100M_RX, blink) ||
+	    FIELD_GET(LED_BLINK_EVT_1000M_RX, blink))
+		__set_bit(TRIGGER_NETDEV_RX, rules);
+
+	if (FIELD_GET(LED_BLINK_EVT_10M_TX, blink) ||
+	    FIELD_GET(LED_BLINK_EVT_100M_TX, blink) ||
+	    FIELD_GET(LED_BLINK_EVT_1000M_TX, blink))
+		__set_bit(TRIGGER_NETDEV_TX, rules);
+
+	if (FIELD_GET(LED_BLINK_EVT_RX_CRC_ERR, blink))
+		__set_bit(TRIGGER_NETDEV_RX_ERR, rules);
+
+	return 0;
+}
+
+static int an8801r_led_trig_to_hw(unsigned long rules, u16 *on, u16 *blink)
+{
+	if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
+		*on |= LED_ON_EVT_LINK_10M;
+
+	if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
+		*on |= LED_ON_EVT_LINK_100M;
+
+	if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
+		*on |= LED_ON_EVT_LINK_1000M;
+
+	if (test_bit(TRIGGER_NETDEV_LINK, &rules)) {
+		*on |= LED_ON_EVT_LINK_10M;
+		*on |= LED_ON_EVT_LINK_100M;
+		*on |= LED_ON_EVT_LINK_1000M;
+	}
+
+	if (test_bit(TRIGGER_NETDEV_RX, &rules)) {
+		*blink |= LED_BLINK_EVT_10M_RX;
+		*blink |= LED_BLINK_EVT_100M_RX;
+		*blink |= LED_BLINK_EVT_1000M_RX;
+	}
+
+	if (test_bit(TRIGGER_NETDEV_TX, &rules)) {
+		*blink |= LED_BLINK_EVT_10M_TX;
+		*blink |= LED_BLINK_EVT_100M_TX;
+		*blink |= LED_BLINK_EVT_1000M_TX;
+	}
+
+	if (test_bit(TRIGGER_NETDEV_RX_ERR, &rules))
+		*blink |= LED_BLINK_EVT_RX_CRC_ERR;
+
+	if (rules && !*on && !*blink)
+		return -EOPNOTSUPP;
+
+	return 0;
+}
+
+static int an8801r_led_hw_is_supported(struct phy_device *phydev, u8 index,
+				       unsigned long rules)
+{
+	u16 on = 0, blink = 0;
+
+	if (index >= AN8801R_NUM_LEDS)
+		return -EINVAL;
+
+	return an8801r_led_trig_to_hw(rules, &on, &blink);
+}
+
+static int an8801r_led_hw_control_set(struct phy_device *phydev, u8 index,
+				      unsigned long rules)
+{
+	u16 on = 0, blink = 0;
+	int ret;
+
+	if (index >= AN8801R_NUM_LEDS)
+		return -EINVAL;
+
+	ret = an8801r_led_trig_to_hw(rules, &on, &blink);
+	if (ret)
+		return ret;
+
+	ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+			     LED_ON_EVT_MASK, on);
+	if (ret)
+		return ret;
+
+	ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_CTRL(index),
+			     LED_BLINK_EVT_MASK, blink);
+
+	if (ret)
+		return ret;
+
+	return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+			      LED_ON_EN, on | blink ? LED_ON_EN : 0);
+}
+
+static int an8801r_led_polarity_set(struct phy_device *phydev, int index,
+				    unsigned long modes)
+{
+	unsigned long mode;
+	bool active_high;
+
+	if (index >= AN8801R_NUM_LEDS)
+		return -EINVAL;
+
+	for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
+		switch (mode) {
+		case PHY_LED_ACTIVE_HIGH:
+			active_high = true;
+			break;
+		case PHY_LED_ACTIVE_LOW:
+			active_high = false;
+			break;
+		default:
+			return -EINVAL;
+		}
+	}
+
+	return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index),
+			      LED_ON_POL, active_high ? LED_ON_POL : 0);
+}
+
+static int an8801r_led_init(struct phy_device *phydev, u8 *led_cfg)
+{
+	int led_id, ret;
+
+	/* Set LED BCR Enable */
+	ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, LED_BCR,
+			       LED_BCR_EXT_CTRL | LED_BCR_CLK_EN);
+	if (ret)
+		return ret;
+
+	for (led_id = 0; led_id < AN8801R_NUM_LEDS; led_id++) {
+		unsigned long led_trigger = 0;
+		u32 led_gpio = led_id + 1;
+
+		switch (led_cfg[led_id]) {
+		case AN8801R_LED_FN_LINK:
+			led_trigger = BIT(TRIGGER_NETDEV_LINK);
+			break;
+		case AN8801R_LED_FN_ACTIVITY:
+			led_trigger = BIT(TRIGGER_NETDEV_RX) |
+				    BIT(TRIGGER_NETDEV_TX);
+			break;
+		default:
+			led_trigger = 0;
+			break;
+		}
+
+		ret = air_buckpbus_reg_set_bits(phydev,
+						AN8801_BPBUS_REG_LED_GPIO,
+						BIT(led_gpio));
+		if (ret)
+			return ret;
+
+		ret = air_buckpbus_reg_set_bits(phydev,
+						AN8801_BPBUS_REG_LED_ID_SEL,
+						LED_ID_GPIO_SEL(led_id,
+								led_gpio));
+		if (ret)
+			return ret;
+
+		ret = air_buckpbus_reg_clear_bits(phydev,
+						  AN8801_BPBUS_REG_GPIO_MODE,
+						  BIT(led_gpio));
+		if (ret)
+			return ret;
+
+		if (!led_trigger)
+			continue;
+
+		ret = an8801r_led_hw_control_set(phydev, led_id, led_trigger);
+		if (ret)
+			return ret;
+	}
+	return 0;
+}
+
+static int an8801r_ack_interrupt(struct phy_device *phydev)
+{
+	u32 reg_val;
+	int ret;
+
+	/* Reset WOL status */
+	ret = air_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKEUP_CTL2,
+				     AN8801_PME_WAKEUP_CLR |
+				     AN8801_WAKE_OUT_POLARITY_NEG);
+	if (ret)
+		return ret;
+
+	ret = air_buckpbus_reg_read(phydev, AN8801_BPBUS_REG_WAKEUP_CTL1,
+				    &reg_val);
+	if (ret)
+		return ret;
+
+	ret = air_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKEUP_CTL1, 0);
+	if (ret)
+		return ret;
+
+	ret = air_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKEUP_CTL1,
+				     reg_val | BIT(4));
+	if (ret)
+		return ret;
+
+	ret = air_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKEUP_CTL2,
+				     AN8801_WAKE_OUT_POLARITY_NEG |
+				     AN8801_WAKE_OUT_EN);
+	if (ret)
+		return ret;
+
+	/* Clear the interrupts by writing the reg */
+	ret = air_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKE_IRQ_STS,
+				     AN8801_IRQ_WAKE_ALL);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int an8801r_config_intr(struct phy_device *phydev)
+{
+	int ret;
+
+	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
+		u32 val = FIELD_PREP(AN8801_PHY_IRQ_GPIO_NUM_MASK,
+				     AN8801_PHY_IRQ_GPIO_NUM);
+
+		ret = air_buckpbus_reg_write(phydev,
+					     AN8801_BPBUS_REG_PHY_IRQ_GPIO,
+					     val);
+		if (ret)
+			return ret;
+
+		ret = air_buckpbus_reg_set_bits(phydev,
+						AN8801_BPBUS_REG_WAKE_IRQ_EN,
+						AN8801_IRQ_WAKE_LNKCHG);
+		if (ret)
+			return ret;
+	} else {
+		ret = air_buckpbus_reg_write(phydev,
+					     AN8801_BPBUS_REG_PHY_IRQ_GPIO, 0);
+		if (ret)
+			return ret;
+
+		ret = air_buckpbus_reg_clear_bits(phydev,
+						  AN8801_BPBUS_REG_WAKE_IRQ_EN,
+						  AN8801_IRQ_WAKE_LNKCHG);
+		if (ret)
+			return ret;
+	}
+
+	return an8801r_ack_interrupt(phydev);
+}
+
+static int an8801r_did_interrupt(struct phy_device *phydev)
+{
+	u32 irq_en, irq_status;
+	int ret;
+
+	ret = air_buckpbus_reg_read(phydev, AN8801_BPBUS_REG_WAKE_IRQ_EN,
+				    &irq_en);
+	if (ret)
+		return ret;
+
+	ret = air_buckpbus_reg_read(phydev, AN8801_BPBUS_REG_WAKE_IRQ_STS,
+				    &irq_status);
+	if (ret)
+		return ret;
+
+	if (irq_status & AN8801_IRQ_WAKE_MAGICPKT)
+		return 0;
+
+	if ((irq_en & AN8801_IRQ_WAKE_LNKCHG) &&
+	    (irq_status & AN8801_IRQ_WAKE_LNKCHG))
+		return 0;
+
+	return -EINVAL;
+}
+
+static irqreturn_t an8801r_handle_interrupt(struct phy_device *phydev)
+{
+	int ret;
+
+	ret = an8801r_did_interrupt(phydev);
+	if (ret)
+		return IRQ_NONE;
+
+	ret = an8801r_ack_interrupt(phydev);
+	if (ret)
+		return IRQ_NONE;
+
+	phy_trigger_machine(phydev);
+
+	return IRQ_HANDLED;
+}
+
+static void an8801r_get_wol(struct phy_device *phydev,
+			    struct ethtool_wolinfo *wol)
+{
+	u32 reg_val;
+
+	air_buckpbus_reg_read(phydev, AN8801_BPBUS_REG_WAKEUP_CTL1, &reg_val);
+
+	wol->supported = WAKE_MAGIC;
+
+	if (reg_val & AN8801_WOL_WAKE_MAGIC_EN)
+		wol->wolopts |= WAKE_MAGIC;
+	else
+		wol->wolopts &= ~WAKE_MAGIC;
+}
+
+static int an8801r_set_wol(struct phy_device *phydev,
+			   struct ethtool_wolinfo *wol)
+{
+	struct net_device *attach_dev = phydev->attached_dev;
+	const unsigned char *macaddr = attach_dev->dev_addr;
+	u32 reg_val;
+	int ret;
+
+	if (wol->wolopts & WAKE_MAGIC) {
+		/* MAC bits 16..47 */
+		reg_val = (macaddr[2] << 24) | (macaddr[3] << 16);
+		reg_val |= (macaddr[4] << 8) | (macaddr[5]);
+
+		ret = air_buckpbus_reg_write(phydev,
+					     AN8801_BPBUS_REG_WOL_MAC_16_47,
+					     reg_val);
+		if (ret)
+			return ret;
+
+		/* MAC bits 0..15 */
+		reg_val = (macaddr[0] << 8) | (macaddr[1]);
+
+		ret = air_buckpbus_reg_write(phydev,
+					     AN8801_BPBUS_REG_WOL_MAC_0_15,
+					     reg_val);
+		if (ret)
+			return ret;
+
+		ret = air_buckpbus_reg_set_bits(phydev,
+						AN8801_BPBUS_REG_WAKEUP_CTL1,
+						AN8801_WOL_WAKE_MAGIC_EN);
+		if (ret)
+			return ret;
+
+		ret = air_buckpbus_reg_set_bits(phydev,
+						AN8801_BPBUS_REG_WAKE_IRQ_EN,
+						AN8801_IRQ_WAKE_MAGICPKT);
+		if (ret)
+			return ret;
+	} else {
+		ret = air_buckpbus_reg_clear_bits(phydev,
+						  AN8801_BPBUS_REG_WAKEUP_CTL1,
+						  AN8801_WOL_WAKE_MAGIC_EN);
+		if (ret)
+			return ret;
+
+		ret = air_buckpbus_reg_clear_bits(phydev,
+						  AN8801_BPBUS_REG_WAKE_IRQ_EN,
+						  AN8801_IRQ_WAKE_MAGICPKT);
+		if (ret)
+			return ret;
+	}
+
+	return an8801r_ack_interrupt(phydev);
+}
+
+static int an8801r_of_init_leds(struct phy_device *phydev, u8 *led_cfg)
+{
+	struct device *dev = &phydev->mdio.dev;
+	struct device_node *np = dev->of_node;
+	struct device_node *leds;
+	u32 function_enum_idx;
+	int ret;
+
+	if (!np)
+		return 0;
+
+	/* If devicetree is present, leds configuration is required */
+	leds = of_get_child_by_name(np, "leds");
+	if (!leds)
+		return -ENOENT;
+
+	for_each_available_child_of_node_scoped(leds, led) {
+		u32 led_idx;
+
+		ret = of_property_read_u32(led, "reg", &led_idx);
+		if (ret)
+			goto out;
+
+		if (led_idx >= AN8801R_NUM_LEDS) {
+			ret = -EINVAL;
+			goto out;
+		}
+
+		ret = of_property_read_u32(led, "function-enumerator",
+					   &function_enum_idx);
+		if (ret)
+			function_enum_idx = AN8801R_LED_FN_NONE;
+
+		if (function_enum_idx >= AN8801R_LED_FN_MAX) {
+			ret = -EINVAL;
+			goto out;
+		}
+
+		led_cfg[led_idx] = function_enum_idx;
+	}
+out:
+	of_node_put(leds);
+	return ret;
+}
+
+static int an8801r_rgmii_rxdelay(struct phy_device *phydev, u16 delay_steps)
+{
+	u32 reg_val;
+
+	if (delay_steps > RGMII_DELAY_STEP_MASK)
+		return -EINVAL;
+
+	reg_val = delay_steps & RGMII_DELAY_STEP_MASK;
+	reg_val |= RGMII_RXDELAY_ALIGN;
+	reg_val |= RGMII_RXDELAY_FORCE_MODE;
+
+	return air_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_RXDLY_STEP,
+				      reg_val);
+}
+
+static int an8801r_rgmii_txdelay(struct phy_device *phydev, u16 delay_steps)
+{
+	u32 reg_val;
+
+	if (delay_steps > RGMII_DELAY_STEP_MASK)
+		return -EINVAL;
+
+	reg_val = delay_steps & RGMII_DELAY_STEP_MASK;
+	reg_val |= RGMII_TXDELAY_FORCE_MODE;
+
+	return air_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_TXDLY_STEP,
+				      reg_val);
+}
+
+static int an8801r_rgmii_delay_config(struct phy_device *phydev)
+{
+	switch (phydev->interface) {
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		return an8801r_rgmii_txdelay(phydev, 4);
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+		return an8801r_rgmii_rxdelay(phydev, 0);
+	case PHY_INTERFACE_MODE_RGMII_ID:
+		return an8801r_rgmii_txdelay(phydev, 4);
+		return an8801r_rgmii_rxdelay(phydev, 0);
+	case PHY_INTERFACE_MODE_RGMII:
+	default:
+		return 0;
+	}
+}
+
+static int an8801r_config_init(struct phy_device *phydev)
+{
+	u8 led_default_function[AN8801R_NUM_LEDS] = { 0 };
+	int prev_page, ret;
+
+	ret = an8801r_of_init_leds(phydev, led_default_function);
+	if (ret)
+		return ret;
+
+	/* Disable Low Power Mode (LPM) */
+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AN8801_REG_PHY_INTERNAL0,
+			    FIELD_PREP(AN8801_PHY_INTFUNC_MASK, 0x1e));
+	if (ret)
+		return ret;
+
+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AN8801_REG_PHY_INTERNAL1,
+			    FIELD_PREP(AN8801_PHY_INTFUNC_MASK, 0x2));
+	if (ret)
+		return ret;
+
+	/* Disable EEE by default */
+	ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
+	if (ret)
+		return ret;
+
+	prev_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_1);
+	if (prev_page < 0)
+		return prev_page;
+
+	/* Set the PHY to perform auto-downshift after 3 auto-negotiation
+	 * attempts
+	 */
+	__phy_write(phydev, AN8801_EXT_REG_PHY,
+		    FIELD_PREP(AN8801_EXT_PHY_CTRL1, 0x1d) |
+		    FIELD_PREP(AN8801_EXT_PHY_DOWNSHIFT_CTL, 1) |
+		    AN8801_EXT_PHY_DOWNSHIFT_EN);
+
+	ret = phy_restore_page(phydev, prev_page, ret);
+	if (ret)
+		return ret;
+
+	ret = air_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_BYPASS_PTP,
+				     AN8801_BYP_PTP_RGMII_TO_GPHY);
+	if (ret)
+		return ret;
+
+	ret = air_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_EFIFO_CTL(0),
+				     AN8801_EFIFO_RX_EN | AN8801_EFIFO_TX_EN |
+				     AN8801_EFIFO_RX_CLK_EN |
+				     AN8801_EFIFO_TX_CLK_EN |
+				     AN8801_EFIFO_RX_EEE_EN |
+				     AN8801_EFIFO_TX_EEE_EN);
+	if (ret)
+		return ret;
+
+	ret = air_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_EFIFO_CTL(1),
+				     AN8801_EFIFO_ALL_EN);
+	if (ret)
+		return ret;
+
+	ret = air_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_EFIFO_CTL(2),
+				     AN8801_EFIFO_ALL_EN);
+	if (ret)
+		return ret;
+
+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,
+			    AN8801_PHY_TX_PAIR_DLY_SEL_GBE,
+			    FIELD_PREP(AN8801_PHY_PAIR_DLY_SEL_A_GBE, 4) |
+			    FIELD_PREP(AN8801_PHY_PAIR_DLY_SEL_C_GBE, 4));
+	if (ret)
+		return ret;
+
+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8801_PHY_RXADC_CTRL,
+			    AN8801_PHY_RXADC_SAMP_PHSEL_A |
+			    AN8801_PHY_RXADC_SAMP_PHSEL_C);
+	if (ret)
+		return ret;
+
+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8801_PHY_RXADC_REV_0,
+			    FIELD_PREP(AN8801_PHY_RXADC_REV_MASK_A, 1));
+	if (ret)
+		return ret;
+
+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8801_PHY_RXADC_REV_1,
+			    FIELD_PREP(AN8801_PHY_RXADC_REV_MASK_C, 1));
+	if (ret)
+		return ret;
+
+	ret = an8801r_rgmii_delay_config(phydev);
+	if (ret)
+		return ret;
+
+	ret = air_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_CKO,
+				     AN8801_CKO_OUTPUT_MODE_AUTO);
+	if (ret)
+		return ret;
+
+	ret = an8801r_led_init(phydev, led_default_function);
+	if (ret) {
+		phydev_err(phydev, "Cannot initialize LEDs: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int an8801r_read_status(struct phy_device *phydev)
+{
+	int prev_speed, ret;
+	u32 val;
+
+	prev_speed = phydev->speed;
+
+	ret = genphy_read_status(phydev);
+	if (ret)
+		return ret;
+
+	if (!phydev->link)
+		return 0;
+
+	if (prev_speed != phydev->speed) {
+		val = phydev->speed == SPEED_1000 ?
+		      AN8801_BPBUS_LINK_MODE_1000 : 0;
+
+		return air_buckpbus_reg_rmw(phydev, AN8801_BPBUS_REG_LINK_MODE,
+					    AN8801_BPBUS_LINK_MODE_1000, val);
+	};
+
+	return 0;
+}
+
+static struct phy_driver airoha_driver[] = {
+{
+	PHY_ID_MATCH_MODEL(AN8801R_PHY_ID),
+	.name			= "Airoha AN8801R",
+	.features		= PHY_GBIT_FEATURES,
+	.config_init		= an8801r_config_init,
+	.suspend		= genphy_suspend,
+	.resume			= genphy_resume,
+	.config_aneg		= genphy_config_aneg,
+	.read_status		= an8801r_read_status,
+	.config_intr		= an8801r_config_intr,
+	.handle_interrupt	= an8801r_handle_interrupt,
+	.set_wol		= an8801r_set_wol,
+	.get_wol		= an8801r_get_wol,
+	.read_page		= an8801r_read_page,
+	.write_page		= an8801r_write_page,
+	.led_brightness_set	= an8801r_led_brightness_set,
+	.led_blink_set		= an8801r_led_blink_set,
+	.led_hw_is_supported	= an8801r_led_hw_is_supported,
+	.led_hw_control_set	= an8801r_led_hw_control_set,
+	.led_hw_control_get	= an8801r_led_hw_control_get,
+	.led_polarity_set	= an8801r_led_polarity_set,
+} };
+module_phy_driver(airoha_driver);
+
+static struct mdio_device_id __maybe_unused an8801_tbl[] = {
+	{ PHY_ID_MATCH_MODEL(AN8801R_PHY_ID) },
+	{ }
+};
+MODULE_DEVICE_TABLE(mdio, an8801_tbl);
+
+MODULE_DESCRIPTION("Airoha AN8801 PHY driver");
+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
+MODULE_LICENSE("GPL");

-- 
2.53.0

Re: [PATCH net-next 2/2] net: phy: Introduce Airoha AN8801/R Gigabit Ethernet PHY driver

[Maxime Chevallier]

Hi Louis-Alexis

On 04/03/2026 10:35, Louis-Alexis Eyraud wrote:
> From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> 
> Introduce a driver for the Airoha AN8801R Series Gigabit Ethernet
> PHY; this currently supports setting up PHY LEDs, 10/100M, 1000M
> speeds, and Wake on LAN and PHY interrupts.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
> ---
>  drivers/net/phy/Kconfig      |    5 +
>  drivers/net/phy/Makefile     |    1 +
>  drivers/net/phy/air_an8801.c | 1059 ++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 1065 insertions(+)
> 
> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> index 7b73332a13d9520582fb45780528de4e17496f5e..53f451479509b7c11999beaf91ae08ed4ed01e86 100644
> --- a/drivers/net/phy/Kconfig
> +++ b/drivers/net/phy/Kconfig
> @@ -96,6 +96,11 @@ config AS21XXX_PHY
>  	  AS21210PB1 that all register with the PHY ID 0x7500 0x7500
>  	  before the firmware is loaded.
>  
> +config AIR_AN8801_PHY
> +	tristate "Airoha AN8801 Gigabit PHY"
> +	help
> +	  Currently supports the Airoha AN8801R PHY.
> +
>  config AIR_EN8811H_PHY
>  	tristate "Airoha EN8811H 2.5 Gigabit PHY"
>  	select PHY_COMMON_PROPS
> diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
> index 3a34917adea72d03342a8a4ef703ee5d087d229e..83516da36c9ffa4e3b077717e9fc375e38ab2ea5 100644
> --- a/drivers/net/phy/Makefile
> +++ b/drivers/net/phy/Makefile
> @@ -29,6 +29,7 @@ obj-y				+= $(sfp-obj-y) $(sfp-obj-m)
>  
>  obj-$(CONFIG_ADIN_PHY)		+= adin.o
>  obj-$(CONFIG_ADIN1100_PHY)	+= adin1100.o
> +obj-$(CONFIG_AIR_AN8801_PHY)	+= air_an8801.o
>  obj-$(CONFIG_AIR_EN8811H_PHY)   += air_en8811h.o
>  obj-$(CONFIG_AMD_PHY)		+= amd.o
>  obj-$(CONFIG_AMCC_QT2025_PHY)	+= qt2025.o
> diff --git a/drivers/net/phy/air_an8801.c b/drivers/net/phy/air_an8801.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..86828c7d9716ee45832483d74f01f2764fcda408
> --- /dev/null
> +++ b/drivers/net/phy/air_an8801.c
> @@ -0,0 +1,1059 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Driver for the Airoha AN8801 Gigabit PHY.
> + *
> + * Copyright (C) 2025 Airoha Technology Corp.
> + * Copyright (C) 2025 Collabora Ltd.
> + *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/bitops.h>
> +#include <linux/delay.h>
> +#include <linux/errno.h>
> +#include <linux/init.h>
> +#include <linux/netdevice.h>
> +#include <linux/of.h>
> +#include <linux/phy.h>
> +
> +#define AN8801R_PHY_ID			0xc0ff0421
> +
> +/* MII Registers */
> +#define AIR_EXT_PAGE_ACCESS		0x1f
> +#define   AIR_PHY_PAGE_STANDARD		0
> +#define   AIR_PHY_PAGE_EXTENDED_1	1
> +#define   AIR_PHY_PAGE_EXTENDED_4	4
> +
> +/* MII Registers - Airoha Page 1 */
> +#define AN8801_EXT_REG_PHY		0x14
> +#define   AN8801_EXT_PHY_STATUS0	GENMASK(1, 0)
> +#define   AN8801_EXT_PHY_DOWNSHIFT_CTL	GENMASK(3, 2) /* 2 to 5 1G auto-neg attempts (0..3) */
> +#define   AN8801_EXT_PHY_DOWNSHIFT_EN	BIT(4)
> +#define   AN8801_EXT_PHY_CTRL0		BIT(5)
> +#define   AN8801_EXT_PHY_STATUS1	GENMASK(8, 6)
> +#define   AN8801_EXT_PHY_CTRL1		GENMASK(14, 9)
> +
> +/* MII Registers - Airoha Page 4 */
> +#define AN8801_PBUS_ACCESS		BIT(28)
> +#define AN8801_PBUS_EPHY_ACCESS		BIT(24)
> +#define AN8801_PBUS_CL22_ACCESS		BIT(23)
> +
> +#define AIR_BPBUS_MODE			0x10
> +#define AIR_BPBUS_WR_ADDR_HIGH		0x11
> +#define AIR_BPBUS_WR_ADDR_LOW		0x12
> +#define AIR_BPBUS_WR_DATA_HIGH		0x13
> +#define AIR_BPBUS_WR_DATA_LOW		0x14
> +#define AIR_BPBUS_RD_ADDR_HIGH		0x15
> +#define AIR_BPBUS_RD_ADDR_LOW		0x16
> +#define AIR_BPBUS_RD_DATA_HIGH		0x17
> +#define AIR_BPBUS_RD_DATA_LOW		0x18
> +
> +/* BPBUS Registers */
> +#define AN8801_BPBUS_REG_LED_GPIO	0x54
> +#define AN8801_BPBUS_REG_LED_ID_SEL	0x58
> +#define   LED_ID_GPIO_SEL(led, gpio)	((led) << ((gpio) * 3))
> +#define AN8801_BPBUS_REG_GPIO_MODE	0x70
> +#define AN8801_BPBUS_REG_PHY_IRQ_GPIO	0x7c
> +#define   AN8801_PHY_IRQ_GPIO_NUM_MASK	GENMASK(19, 16)
> +#define   AN8801_PHY_IRQ_GPIO_NUM	1
> +
> +#define AN8801_BPBUS_REG_CKO		0x1a4
> +#define AN8801_CKO_OUTPUT_MODE_AUTO	3
> +
> +#define AN8801_BPBUS_REG_LINK_MODE	0x5054
> +#define  AN8801_BPBUS_LINK_MODE_1000	BIT(0)
> +
> +#define AN8801_BPBUS_REG_BYPASS_PTP	0x21c004
> +#define   AN8801_BYP_PTP_SGMII_TO_GPHY	BIT(8)
> +#define   AN8801_BYP_PTP_RGMII_TO_GPHY	BIT(0)
> +
> +#define AN8801_BPBUS_REG_TXDLY_STEP	0x21c024
> +#define   RGMII_DELAY_STEP_MASK		GENMASK(2, 0)
> +#define   RGMII_TXDELAY_FORCE_MODE	BIT(24)
> +
> +#define AN8801_BPBUS_REG_RXDLY_STEP	0x21c02c
> +#define   RGMII_RXDELAY_ALIGN		BIT(4)
> +#define   RGMII_RXDELAY_FORCE_MODE	BIT(24)
> +
> +#define AN8801_BPBUS_REG_EFIFO_CTL(x)	(0x270004 + (0x100 * (x))) /* 0..2 */
> +#define   AN8801_EFIFO_ALL_EN		GENMASK(7, 0)
> +#define   AN8801_EFIFO_RX_EN		BIT(0)
> +#define   AN8801_EFIFO_TX_EN		BIT(1)
> +#define   AN8801_EFIFO_RX_CLK_EN	BIT(2)
> +#define   AN8801_EFIFO_TX_CLK_EN	BIT(3)
> +#define   AN8801_EFIFO_RX_EEE_EN	BIT(4)
> +#define   AN8801_EFIFO_TX_EEE_EN	BIT(5)
> +#define   AN8801_EFIFO_RX_ODD_NIBBLE_EN	BIT(6)
> +#define   AN8801_EFIFO_TX_ODD_NIBBLE_EN	BIT(7)
> +
> +#define AN8801_BPBUS_REG_WOL_MAC_16_47	0x285114
> +#define AN8801_BPBUS_REG_WOL_MAC_0_15	0x285118
> +
> +#define AN8801_BPBUS_REG_WAKEUP_CTL1	0x285400
> +#define   AN8801_WOL_WAKE_MAGIC_EN	GENMASK(3, 1)
> +
> +#define AN8801_BPBUS_REG_WAKEUP_CTL2	0x285404
> +#define   AN8801_WAKE_OUT_TYPE_PULSE	BIT(0) /* Set/Unset: Pulse/Static */
> +#define   AN8801_WAKE_OUT_POLARITY_NEG	BIT(1) /* Set/Unset: Negative/Positive */
> +#define   AN8801_WAKE_OUT_WIDTH		GENMASK(2, 3)
> +#define    AN8801_WAKE_OUT_84MS		0
> +#define    AN8801_WAKE_OUT_168MS	1
> +#define    AN8801_WAKE_OUT_336MS	2
> +#define    AN8801_WAKE_OUT_672MS	3
> +#define   AN8801_WAKE_OUT_EN		BIT(4)
> +#define   AN8801_PME_WAKEUP_CLR		BIT(8)
> +
> +#define AN8801_BPBUS_REG_WAKE_IRQ_EN	0x285700
> +#define AN8801_BPBUS_REG_WAKE_IRQ_STS	0x285704
> +#define   AN8801_IRQ_WAKE_LNKCHG	BIT(0) /* Wake on link change */
> +#define   AN8801_IRQ_WAKE_UNIPKT	BIT(1) /* Wake on unicast packet */
> +#define   AN8801_IRQ_WAKE_MULPKT	BIT(2) /* Wake on multicast packet */
> +#define   AN8801_IRQ_WAKE_BCPKT		BIT(3) /* Wake on broadcast packet */
> +#define   AN8801_IRQ_WAKE_MAGICPKT	BIT(4) /* Wake on magic packet */
> +#define   AN8801_IRQ_WAKE_ALL		GENMASK(4, 0)
> +
> +/* MDIO_MMD_VEND1 Registers */
> +#define AN8801_PHY_TX_PAIR_DLY_SEL_GBE	0x13
> +#define   AN8801_PHY_PAIR_DLY_SEL_A_GBE	GENMASK(14, 12)
> +#define   AN8801_PHY_PAIR_DLY_SEL_B_GBE	GENMASK(10, 8)
> +#define   AN8801_PHY_PAIR_DLY_SEL_C_GBE	GENMASK(6, 4)
> +#define   AN8801_PHY_PAIR_DLY_SEL_D_GBE	GENMASK(2, 0)
> +#define AN8801_PHY_RXADC_CTRL		0xd8
> +#define   AN8801_PHY_RXADC_SAMP_PHSEL_A	BIT(12)
> +#define   AN8801_PHY_RXADC_SAMP_PHSEL_B	BIT(8)
> +#define   AN8801_PHY_RXADC_SAMP_PHSEL_C	BIT(4)
> +#define   AN8801_PHY_RXADC_SAMP_PHSEL_D	BIT(0)
> +#define AN8801_PHY_RXADC_REV_0		0xd9
> +#define   AN8801_PHY_RXADC_REV_MASK_A	GENMASK(15, 8)
> +#define   AN8801_PHY_RXADC_REV_MASK_B	GENMASK(7, 0)
> +#define AN8801_PHY_RXADC_REV_1		0xda
> +#define   AN8801_PHY_RXADC_REV_MASK_C	GENMASK(15, 8)
> +#define   AN8801_PHY_RXADC_REV_MASK_D	GENMASK(7, 0)
> +
> +/* MDIO_MMD_VEND2 Registers */
> +#define LED_BCR				0x21
> +#define   LED_BCR_MODE_MASK		GENMASK(1, 0)
> +#define   LED_BCR_TIME_TEST		BIT(2)
> +#define   LED_BCR_CLK_EN		BIT(3)
> +#define   LED_BCR_EVT_ALL		BIT(4)
> +#define   LED_BCR_EXT_CTRL		BIT(15)
> +#define   LED_BCR_MODE_DISABLE		0
> +#define   LED_BCR_MODE_2LED		1
> +#define   LED_BCR_MODE_3LED_1		2
> +#define   LED_BCR_MODE_3LED_2		3
> +
> +#define LED_ON_DUR			0x22
> +#define   LED_ON_DUR_MASK		GENMASK(15, 0)
> +
> +#define LED_BLINK_DUR			0x23
> +#define   LED_BLINK_DUR_MASK		GENMASK(15, 0)
> +
> +#define LED_ON_CTRL(i)			(0x24 + ((i) * 2))
> +#define   LED_ON_EVT_MASK		GENMASK(6, 0)
> +#define   LED_ON_EVT_LINK_1000M		BIT(0)
> +#define   LED_ON_EVT_LINK_100M		BIT(1)
> +#define   LED_ON_EVT_LINK_10M		BIT(2)
> +#define   LED_ON_EVT_LINK_DN		BIT(3)
> +#define   LED_ON_EVT_FDX		BIT(4)
> +#define   LED_ON_EVT_HDX		BIT(5)
> +#define   LED_ON_EVT_FORCE		BIT(6)
> +#define   LED_ON_POL			BIT(14)
> +#define   LED_ON_EN			BIT(15)
> +
> +#define LED_BLINK_CTRL(i)		(0x25 + ((i) * 2))
> +#define LED_BLINK_EVT_MASK		GENMASK(9, 0)
> +#define LED_BLINK_EVT_1000M_TX		BIT(0)
> +#define LED_BLINK_EVT_1000M_RX		BIT(1)
> +#define LED_BLINK_EVT_100M_TX		BIT(2)
> +#define LED_BLINK_EVT_100M_RX		BIT(3)
> +#define LED_BLINK_EVT_10M_TX		BIT(4)
> +#define LED_BLINK_EVT_10M_RX		BIT(5)
> +#define LED_BLINK_EVT_COLLISION		BIT(6)
> +#define LED_BLINK_EVT_RX_CRC_ERR	BIT(7)
> +#define LED_BLINK_EVT_RX_IDLE_ERR	BIT(8)
> +#define LED_BLINK_EVT_FORCE		BIT(9)
> +
> +#define AN8801R_NUM_LEDS		3
> +#define AN8801_PERIOD_SHIFT		15
> +#define AN8801_PERIOD_UNIT		32768 /* (1 << AN8801_PERIOD_SHIFT) */
> +#define AN8801_MAX_PERIOD_MS		2147
> +
> +#define LED_BLINK_DURATION_UNIT		780
> +#define LED_BLINK_DURATION(f)		(LED_BLINK_DURATION_UNIT << (f))
> +
> +#define AN8801_LED_DURATION_UNIT_US	32768
> +
> +#define AN8801_REG_PHY_INTERNAL0	0x600
> +#define AN8801_REG_PHY_INTERNAL1	0x601
> +#define   AN8801_PHY_INTFUNC_MASK	GENMASK(15, 0) /* PHY internal functions */
> +
> +enum an8801r_led_fn {
> +	AN8801R_LED_FN_NONE,
> +	AN8801R_LED_FN_LINK,
> +	AN8801R_LED_FN_ACTIVITY,
> +	AN8801R_LED_FN_MAX,
> +};
> +
> +static int an8801r_read_page(struct phy_device *phydev)
> +{
> +	return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
> +}
> +
> +static int an8801r_write_page(struct phy_device *phydev, int page)
> +{
> +	return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
> +}
> +
> +static int __air_buckpbus_reg_write(struct phy_device *phydev,
> +				    u32 addr, u32 data)
> +{
> +	int ret;
> +
> +	addr |= AN8801_PBUS_ACCESS;
> +
> +	ret = __phy_write(phydev, AIR_BPBUS_MODE, MII_MMD_CTRL_ADDR);
> +	if (ret < 0)
> +		return ret;
> +
> +	ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH, upper_16_bits(addr));
> +	if (ret < 0)
> +		return ret;
> +
> +	ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW, lower_16_bits(addr));
> +	if (ret < 0)
> +		return ret;
> +
> +	ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH, upper_16_bits(data));
> +	if (ret < 0)
> +		return ret;
> +
> +	ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW, lower_16_bits(data));
> +	if (ret < 0)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +static int __air_buckpbus_reg_read(struct phy_device *phydev,
> +				   u32 addr, u32 *data)
> +{
> +	int pbus_data_l, pbus_data_h;
> +	int ret;
> +
> +	addr |= AN8801_PBUS_ACCESS;
> +
> +	ret = __phy_write(phydev, AIR_BPBUS_MODE, MII_MMD_CTRL_ADDR);
> +	if (ret < 0)
> +		return ret;
> +
> +	ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH, upper_16_bits(addr));
> +	if (ret < 0)
> +		return ret;
> +
> +	ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW, lower_16_bits(addr));
> +	if (ret < 0)
> +		return ret;
> +
> +	ret = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
> +	if (pbus_data_h < 0)
> +		return pbus_data_h;
> +
> +	pbus_data_l = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
> +	if (pbus_data_l < 0)
> +		return pbus_data_l;
> +
> +	*data = (pbus_data_h << 16) | pbus_data_l;
> +	return 0;
> +}
> +
> +static int air_buckpbus_reg_rmw(struct phy_device *phydev,
> +				u32 addr, u32 mask, u32 set)
> +{
> +	u32 data_old, data_new;
> +	int prev_page, ret;
> +
> +	prev_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
> +	if (prev_page < 0)
> +		return prev_page;
> +
> +	ret = __air_buckpbus_reg_read(phydev, addr, &data_old);
> +	if (ret)
> +		return phy_restore_page(phydev, prev_page, ret);
> +
> +	data_new = data_old & ~mask;
> +	data_new |= set;
> +	if (data_new != data_old)
> +		ret = __air_buckpbus_reg_write(phydev, addr, data_new);
> +
> +	return phy_restore_page(phydev, prev_page, ret);
> +}
> +
> +static int air_buckpbus_reg_set_bits(struct phy_device *phydev,
> +				     u32 addr, u32 mask)
> +{
> +	return air_buckpbus_reg_rmw(phydev, addr, mask, mask);
> +}
> +
> +static int air_buckpbus_reg_clear_bits(struct phy_device *phydev,
> +				       u32 addr, u32 mask)
> +{
> +	return air_buckpbus_reg_rmw(phydev, addr, mask, 0);
> +}
> +
> +static int air_buckpbus_reg_write(struct phy_device *phydev, u32 addr, u32 data)
> +{
> +	int prev_page, ret = 0;
> +
> +	prev_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
> +	if (prev_page < 0)
> +		return prev_page;
> +
> +	ret = __air_buckpbus_reg_write(phydev, addr, data);
> +
> +	return phy_restore_page(phydev, prev_page, ret);
> +}
> +
> +static int air_buckpbus_reg_read(struct phy_device *phydev, u32 addr, u32 *data)
> +{
> +	int prev_page, ret;
> +
> +	prev_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
> +	if (prev_page < 0)
> +		return prev_page;
> +
> +	ret = __air_buckpbus_reg_read(phydev, addr, data);
> +
> +	return phy_restore_page(phydev, prev_page, ret);
> +}
These buckplus accessors look very similar to what's in the existing air_en8811h.c
driver, any chance the code can be shared ?

[...]


> +static int an8801r_rgmii_rxdelay(struct phy_device *phydev, u16 delay_steps)
> +{
> +	u32 reg_val;
> +
> +	if (delay_steps > RGMII_DELAY_STEP_MASK)
> +		return -EINVAL;
> +
> +	reg_val = delay_steps & RGMII_DELAY_STEP_MASK;
> +	reg_val |= RGMII_RXDELAY_ALIGN;
> +	reg_val |= RGMII_RXDELAY_FORCE_MODE;
> +
> +	return air_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_RXDLY_STEP,
> +				      reg_val);
> +}
> +
> +static int an8801r_rgmii_txdelay(struct phy_device *phydev, u16 delay_steps)
> +{
> +	u32 reg_val;
> +
> +	if (delay_steps > RGMII_DELAY_STEP_MASK)
> +		return -EINVAL;
> +
> +	reg_val = delay_steps & RGMII_DELAY_STEP_MASK;
> +	reg_val |= RGMII_TXDELAY_FORCE_MODE;
> +
> +	return air_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_TXDLY_STEP,
> +				      reg_val);
> +}
> +
> +static int an8801r_rgmii_delay_config(struct phy_device *phydev)
> +{
> +	switch (phydev->interface) {
> +	case PHY_INTERFACE_MODE_RGMII_TXID:
> +		return an8801r_rgmii_txdelay(phydev, 4);
> +	case PHY_INTERFACE_MODE_RGMII_RXID:
> +		return an8801r_rgmii_rxdelay(phydev, 0);
> +	case PHY_INTERFACE_MODE_RGMII_ID:
> +		return an8801r_rgmii_txdelay(phydev, 4);
> +		return an8801r_rgmii_rxdelay(phydev, 0);
> +	case PHY_INTERFACE_MODE_RGMII:
> +	default:
> +		return 0;
> +	}

Can you elaborate on these values for the steps ? Why is it 4 for TX internal delays, but 0 for RX delays ?

Maxime

Re: [PATCH net-next 2/2] net: phy: Introduce Airoha AN8801/R Gigabit Ethernet PHY driver

[Louis-Alexis Eyraud]

Hi Maxime,

On Wed, 2026-03-04 at 10:58 +0100, Maxime Chevallier wrote:
> Hi Louis-Alexis
> 
> On 04/03/2026 10:35, Louis-Alexis Eyraud wrote:
> > From: AngeloGioacchino Del Regno
> > <angelogioacchino.delregno@collabora.com>
> > 
> > Introduce a driver for the Airoha AN8801R Series Gigabit Ethernet
> > PHY; this currently supports setting up PHY LEDs, 10/100M, 1000M
> > speeds, and Wake on LAN and PHY interrupts.
> > 
> > Signed-off-by: AngeloGioacchino Del Regno
> > <angelogioacchino.delregno@collabora.com>
> > Signed-off-by: Louis-Alexis Eyraud
> > <louisalexis.eyraud@collabora.com>
> > ---
> >  drivers/net/phy/Kconfig      |    5 +
> >  drivers/net/phy/Makefile     |    1 +
> >  drivers/net/phy/air_an8801.c | 1059
> > ++++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 1065 insertions(+)
> > 
> > diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> > index
> > 7b73332a13d9520582fb45780528de4e17496f5e..53f451479509b7c11999beaf9
> > 1ae08ed4ed01e86 100644
> > --- a/drivers/net/phy/Kconfig
> > +++ b/drivers/net/phy/Kconfig
> > @@ -96,6 +96,11 @@ config AS21XXX_PHY
> >  	  AS21210PB1 that all register with the PHY ID 0x7500
> > 0x7500
> >  	  before the firmware is loaded.
> >  
> > +config AIR_AN8801_PHY
> > +	tristate "Airoha AN8801 Gigabit PHY"
> > +	help
> > +	  Currently supports the Airoha AN8801R PHY.
> > +
> >  config AIR_EN8811H_PHY
> >  	tristate "Airoha EN8811H 2.5 Gigabit PHY"
> >  	select PHY_COMMON_PROPS
> > diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
> > index
> > 3a34917adea72d03342a8a4ef703ee5d087d229e..83516da36c9ffa4e3b077717e
> > 9fc375e38ab2ea5 100644
> > --- a/drivers/net/phy/Makefile
> > +++ b/drivers/net/phy/Makefile
> > @@ -29,6 +29,7 @@ obj-y				+= $(sfp-obj-y)
> > $(sfp-obj-m)
> >  
> >  obj-$(CONFIG_ADIN_PHY)		+= adin.o
> >  obj-$(CONFIG_ADIN1100_PHY)	+= adin1100.o
> > +obj-$(CONFIG_AIR_AN8801_PHY)	+= air_an8801.o
> >  obj-$(CONFIG_AIR_EN8811H_PHY)   += air_en8811h.o
> >  obj-$(CONFIG_AMD_PHY)		+= amd.o
> >  obj-$(CONFIG_AMCC_QT2025_PHY)	+= qt2025.o
> > diff --git a/drivers/net/phy/air_an8801.c
> > b/drivers/net/phy/air_an8801.c
> > new file mode 100644
> > index
> > 0000000000000000000000000000000000000000..86828c7d9716ee45832483d74
> > f01f2764fcda408
> > --- /dev/null
> > +++ b/drivers/net/phy/air_an8801.c
> > @@ -0,0 +1,1059 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Driver for the Airoha AN8801 Gigabit PHY.
> > + *
> > + * Copyright (C) 2025 Airoha Technology Corp.
> > + * Copyright (C) 2025 Collabora Ltd.
> > + *                    AngeloGioacchino Del Regno
> > <angelogioacchino.delregno@collabora.com>
> > + */
> > +
> > +#include <linux/bitfield.h>
> > +#include <linux/bitops.h>
> > +#include <linux/delay.h>
> > +#include <linux/errno.h>
> > +#include <linux/init.h>
> > +#include <linux/netdevice.h>
> > +#include <linux/of.h>
> > +#include <linux/phy.h>
> > +
> > +#define AN8801R_PHY_ID			0xc0ff0421
> > +
> > +/* MII Registers */
> > +#define AIR_EXT_PAGE_ACCESS		0x1f
> > +#define   AIR_PHY_PAGE_STANDARD		0
> > +#define   AIR_PHY_PAGE_EXTENDED_1	1
> > +#define   AIR_PHY_PAGE_EXTENDED_4	4
> > +
> > +/* MII Registers - Airoha Page 1 */
> > +#define AN8801_EXT_REG_PHY		0x14
> > +#define   AN8801_EXT_PHY_STATUS0	GENMASK(1, 0)
> > +#define   AN8801_EXT_PHY_DOWNSHIFT_CTL	GENMASK(3, 2) /* 2 to 5 1G
> > auto-neg attempts (0..3) */
> > +#define   AN8801_EXT_PHY_DOWNSHIFT_EN	BIT(4)
> > +#define   AN8801_EXT_PHY_CTRL0		BIT(5)
> > +#define   AN8801_EXT_PHY_STATUS1	GENMASK(8, 6)
> > +#define   AN8801_EXT_PHY_CTRL1		GENMASK(14, 9)
> > +
> > +/* MII Registers - Airoha Page 4 */
> > +#define AN8801_PBUS_ACCESS		BIT(28)
> > +#define AN8801_PBUS_EPHY_ACCESS		BIT(24)
> > +#define AN8801_PBUS_CL22_ACCESS		BIT(23)
> > +
> > +#define AIR_BPBUS_MODE			0x10
> > +#define AIR_BPBUS_WR_ADDR_HIGH		0x11
> > +#define AIR_BPBUS_WR_ADDR_LOW		0x12
> > +#define AIR_BPBUS_WR_DATA_HIGH		0x13
> > +#define AIR_BPBUS_WR_DATA_LOW		0x14
> > +#define AIR_BPBUS_RD_ADDR_HIGH		0x15
> > +#define AIR_BPBUS_RD_ADDR_LOW		0x16
> > +#define AIR_BPBUS_RD_DATA_HIGH		0x17
> > +#define AIR_BPBUS_RD_DATA_LOW		0x18
> > +
> > +/* BPBUS Registers */
> > +#define AN8801_BPBUS_REG_LED_GPIO	0x54
> > +#define AN8801_BPBUS_REG_LED_ID_SEL	0x58
> > +#define   LED_ID_GPIO_SEL(led, gpio)	((led) << ((gpio) * 3))
> > +#define AN8801_BPBUS_REG_GPIO_MODE	0x70
> > +#define AN8801_BPBUS_REG_PHY_IRQ_GPIO	0x7c
> > +#define   AN8801_PHY_IRQ_GPIO_NUM_MASK	GENMASK(19, 16)
> > +#define   AN8801_PHY_IRQ_GPIO_NUM	1
> > +
> > +#define AN8801_BPBUS_REG_CKO		0x1a4
> > +#define AN8801_CKO_OUTPUT_MODE_AUTO	3
> > +
> > +#define AN8801_BPBUS_REG_LINK_MODE	0x5054
> > +#define  AN8801_BPBUS_LINK_MODE_1000	BIT(0)
> > +
> > +#define AN8801_BPBUS_REG_BYPASS_PTP	0x21c004
> > +#define   AN8801_BYP_PTP_SGMII_TO_GPHY	BIT(8)
> > +#define   AN8801_BYP_PTP_RGMII_TO_GPHY	BIT(0)
> > +
> > +#define AN8801_BPBUS_REG_TXDLY_STEP	0x21c024
> > +#define   RGMII_DELAY_STEP_MASK		GENMASK(2, 0)
> > +#define   RGMII_TXDELAY_FORCE_MODE	BIT(24)
> > +
> > +#define AN8801_BPBUS_REG_RXDLY_STEP	0x21c02c
> > +#define   RGMII_RXDELAY_ALIGN		BIT(4)
> > +#define   RGMII_RXDELAY_FORCE_MODE	BIT(24)
> > +
> > +#define AN8801_BPBUS_REG_EFIFO_CTL(x)	(0x270004 + (0x100 * (x)))
> > /* 0..2 */
> > +#define   AN8801_EFIFO_ALL_EN		GENMASK(7, 0)
> > +#define   AN8801_EFIFO_RX_EN		BIT(0)
> > +#define   AN8801_EFIFO_TX_EN		BIT(1)
> > +#define   AN8801_EFIFO_RX_CLK_EN	BIT(2)
> > +#define   AN8801_EFIFO_TX_CLK_EN	BIT(3)
> > +#define   AN8801_EFIFO_RX_EEE_EN	BIT(4)
> > +#define   AN8801_EFIFO_TX_EEE_EN	BIT(5)
> > +#define   AN8801_EFIFO_RX_ODD_NIBBLE_EN	BIT(6)
> > +#define   AN8801_EFIFO_TX_ODD_NIBBLE_EN	BIT(7)
> > +
> > +#define AN8801_BPBUS_REG_WOL_MAC_16_47	0x285114
> > +#define AN8801_BPBUS_REG_WOL_MAC_0_15	0x285118
> > +
> > +#define AN8801_BPBUS_REG_WAKEUP_CTL1	0x285400
> > +#define   AN8801_WOL_WAKE_MAGIC_EN	GENMASK(3, 1)
> > +
> > +#define AN8801_BPBUS_REG_WAKEUP_CTL2	0x285404
> > +#define   AN8801_WAKE_OUT_TYPE_PULSE	BIT(0) /* Set/Unset:
> > Pulse/Static */
> > +#define   AN8801_WAKE_OUT_POLARITY_NEG	BIT(1) /* Set/Unset:
> > Negative/Positive */
> > +#define   AN8801_WAKE_OUT_WIDTH		GENMASK(2, 3)
> > +#define    AN8801_WAKE_OUT_84MS		0
> > +#define    AN8801_WAKE_OUT_168MS	1
> > +#define    AN8801_WAKE_OUT_336MS	2
> > +#define    AN8801_WAKE_OUT_672MS	3
> > +#define   AN8801_WAKE_OUT_EN		BIT(4)
> > +#define   AN8801_PME_WAKEUP_CLR		BIT(8)
> > +
> > +#define AN8801_BPBUS_REG_WAKE_IRQ_EN	0x285700
> > +#define AN8801_BPBUS_REG_WAKE_IRQ_STS	0x285704
> > +#define   AN8801_IRQ_WAKE_LNKCHG	BIT(0) /* Wake on link
> > change */
> > +#define   AN8801_IRQ_WAKE_UNIPKT	BIT(1) /* Wake on unicast
> > packet */
> > +#define   AN8801_IRQ_WAKE_MULPKT	BIT(2) /* Wake on
> > multicast packet */
> > +#define   AN8801_IRQ_WAKE_BCPKT		BIT(3) /* Wake on
> > broadcast packet */
> > +#define   AN8801_IRQ_WAKE_MAGICPKT	BIT(4) /* Wake on magic
> > packet */
> > +#define   AN8801_IRQ_WAKE_ALL		GENMASK(4, 0)
> > +
> > +/* MDIO_MMD_VEND1 Registers */
> > +#define AN8801_PHY_TX_PAIR_DLY_SEL_GBE	0x13
> > +#define   AN8801_PHY_PAIR_DLY_SEL_A_GBE	GENMASK(14, 12)
> > +#define   AN8801_PHY_PAIR_DLY_SEL_B_GBE	GENMASK(10, 8)
> > +#define   AN8801_PHY_PAIR_DLY_SEL_C_GBE	GENMASK(6, 4)
> > +#define   AN8801_PHY_PAIR_DLY_SEL_D_GBE	GENMASK(2, 0)
> > +#define AN8801_PHY_RXADC_CTRL		0xd8
> > +#define   AN8801_PHY_RXADC_SAMP_PHSEL_A	BIT(12)
> > +#define   AN8801_PHY_RXADC_SAMP_PHSEL_B	BIT(8)
> > +#define   AN8801_PHY_RXADC_SAMP_PHSEL_C	BIT(4)
> > +#define   AN8801_PHY_RXADC_SAMP_PHSEL_D	BIT(0)
> > +#define AN8801_PHY_RXADC_REV_0		0xd9
> > +#define   AN8801_PHY_RXADC_REV_MASK_A	GENMASK(15, 8)
> > +#define   AN8801_PHY_RXADC_REV_MASK_B	GENMASK(7, 0)
> > +#define AN8801_PHY_RXADC_REV_1		0xda
> > +#define   AN8801_PHY_RXADC_REV_MASK_C	GENMASK(15, 8)
> > +#define   AN8801_PHY_RXADC_REV_MASK_D	GENMASK(7, 0)
> > +
> > +/* MDIO_MMD_VEND2 Registers */
> > +#define LED_BCR				0x21
> > +#define   LED_BCR_MODE_MASK		GENMASK(1, 0)
> > +#define   LED_BCR_TIME_TEST		BIT(2)
> > +#define   LED_BCR_CLK_EN		BIT(3)
> > +#define   LED_BCR_EVT_ALL		BIT(4)
> > +#define   LED_BCR_EXT_CTRL		BIT(15)
> > +#define   LED_BCR_MODE_DISABLE		0
> > +#define   LED_BCR_MODE_2LED		1
> > +#define   LED_BCR_MODE_3LED_1		2
> > +#define   LED_BCR_MODE_3LED_2		3
> > +
> > +#define LED_ON_DUR			0x22
> > +#define   LED_ON_DUR_MASK		GENMASK(15, 0)
> > +
> > +#define LED_BLINK_DUR			0x23
> > +#define   LED_BLINK_DUR_MASK		GENMASK(15, 0)
> > +
> > +#define LED_ON_CTRL(i)			(0x24 + ((i) * 2))
> > +#define   LED_ON_EVT_MASK		GENMASK(6, 0)
> > +#define   LED_ON_EVT_LINK_1000M		BIT(0)
> > +#define   LED_ON_EVT_LINK_100M		BIT(1)
> > +#define   LED_ON_EVT_LINK_10M		BIT(2)
> > +#define   LED_ON_EVT_LINK_DN		BIT(3)
> > +#define   LED_ON_EVT_FDX		BIT(4)
> > +#define   LED_ON_EVT_HDX		BIT(5)
> > +#define   LED_ON_EVT_FORCE		BIT(6)
> > +#define   LED_ON_POL			BIT(14)
> > +#define   LED_ON_EN			BIT(15)
> > +
> > +#define LED_BLINK_CTRL(i)		(0x25 + ((i) * 2))
> > +#define LED_BLINK_EVT_MASK		GENMASK(9, 0)
> > +#define LED_BLINK_EVT_1000M_TX		BIT(0)
> > +#define LED_BLINK_EVT_1000M_RX		BIT(1)
> > +#define LED_BLINK_EVT_100M_TX		BIT(2)
> > +#define LED_BLINK_EVT_100M_RX		BIT(3)
> > +#define LED_BLINK_EVT_10M_TX		BIT(4)
> > +#define LED_BLINK_EVT_10M_RX		BIT(5)
> > +#define LED_BLINK_EVT_COLLISION		BIT(6)
> > +#define LED_BLINK_EVT_RX_CRC_ERR	BIT(7)
> > +#define LED_BLINK_EVT_RX_IDLE_ERR	BIT(8)
> > +#define LED_BLINK_EVT_FORCE		BIT(9)
> > +
> > +#define AN8801R_NUM_LEDS		3
> > +#define AN8801_PERIOD_SHIFT		15
> > +#define AN8801_PERIOD_UNIT		32768 /* (1 <<
> > AN8801_PERIOD_SHIFT) */
> > +#define AN8801_MAX_PERIOD_MS		2147
> > +
> > +#define LED_BLINK_DURATION_UNIT		780
> > +#define LED_BLINK_DURATION(f)		(LED_BLINK_DURATION_UNIT
> > << (f))
> > +
> > +#define AN8801_LED_DURATION_UNIT_US	32768
> > +
> > +#define AN8801_REG_PHY_INTERNAL0	0x600
> > +#define AN8801_REG_PHY_INTERNAL1	0x601
> > +#define   AN8801_PHY_INTFUNC_MASK	GENMASK(15, 0) /* PHY
> > internal functions */
> > +
> > +enum an8801r_led_fn {
> > +	AN8801R_LED_FN_NONE,
> > +	AN8801R_LED_FN_LINK,
> > +	AN8801R_LED_FN_ACTIVITY,
> > +	AN8801R_LED_FN_MAX,
> > +};
> > +
> > +static int an8801r_read_page(struct phy_device *phydev)
> > +{
> > +	return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
> > +}
> > +
> > +static int an8801r_write_page(struct phy_device *phydev, int page)
> > +{
> > +	return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
> > +}
> > +
> > +static int __air_buckpbus_reg_write(struct phy_device *phydev,
> > +				    u32 addr, u32 data)
> > +{
> > +	int ret;
> > +
> > +	addr |= AN8801_PBUS_ACCESS;
> > +
> > +	ret = __phy_write(phydev, AIR_BPBUS_MODE,
> > MII_MMD_CTRL_ADDR);
> > +	if (ret < 0)
> > +		return ret;
> > +
> > +	ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_HIGH,
> > upper_16_bits(addr));
> > +	if (ret < 0)
> > +		return ret;
> > +
> > +	ret = __phy_write(phydev, AIR_BPBUS_WR_ADDR_LOW,
> > lower_16_bits(addr));
> > +	if (ret < 0)
> > +		return ret;
> > +
> > +	ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_HIGH,
> > upper_16_bits(data));
> > +	if (ret < 0)
> > +		return ret;
> > +
> > +	ret = __phy_write(phydev, AIR_BPBUS_WR_DATA_LOW,
> > lower_16_bits(data));
> > +	if (ret < 0)
> > +		return ret;
> > +
> > +	return 0;
> > +}
> > +
> > +static int __air_buckpbus_reg_read(struct phy_device *phydev,
> > +				   u32 addr, u32 *data)
> > +{
> > +	int pbus_data_l, pbus_data_h;
> > +	int ret;
> > +
> > +	addr |= AN8801_PBUS_ACCESS;
> > +
> > +	ret = __phy_write(phydev, AIR_BPBUS_MODE,
> > MII_MMD_CTRL_ADDR);
> > +	if (ret < 0)
> > +		return ret;
> > +
> > +	ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH,
> > upper_16_bits(addr));
> > +	if (ret < 0)
> > +		return ret;
> > +
> > +	ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW,
> > lower_16_bits(addr));
> > +	if (ret < 0)
> > +		return ret;
> > +
> > +	ret = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
> > +	if (pbus_data_h < 0)
> > +		return pbus_data_h;
> > +
> > +	pbus_data_l = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
> > +	if (pbus_data_l < 0)
> > +		return pbus_data_l;
> > +
> > +	*data = (pbus_data_h << 16) | pbus_data_l;
> > +	return 0;
> > +}
> > +
> > +static int air_buckpbus_reg_rmw(struct phy_device *phydev,
> > +				u32 addr, u32 mask, u32 set)
> > +{
> > +	u32 data_old, data_new;
> > +	int prev_page, ret;
> > +
> > +	prev_page = phy_select_page(phydev,
> > AIR_PHY_PAGE_EXTENDED_4);
> > +	if (prev_page < 0)
> > +		return prev_page;
> > +
> > +	ret = __air_buckpbus_reg_read(phydev, addr, &data_old);
> > +	if (ret)
> > +		return phy_restore_page(phydev, prev_page, ret);
> > +
> > +	data_new = data_old & ~mask;
> > +	data_new |= set;
> > +	if (data_new != data_old)
> > +		ret = __air_buckpbus_reg_write(phydev, addr,
> > data_new);
> > +
> > +	return phy_restore_page(phydev, prev_page, ret);
> > +}
> > +
> > +static int air_buckpbus_reg_set_bits(struct phy_device *phydev,
> > +				     u32 addr, u32 mask)
> > +{
> > +	return air_buckpbus_reg_rmw(phydev, addr, mask, mask);
> > +}
> > +
> > +static int air_buckpbus_reg_clear_bits(struct phy_device *phydev,
> > +				       u32 addr, u32 mask)
> > +{
> > +	return air_buckpbus_reg_rmw(phydev, addr, mask, 0);
> > +}
> > +
> > +static int air_buckpbus_reg_write(struct phy_device *phydev, u32
> > addr, u32 data)
> > +{
> > +	int prev_page, ret = 0;
> > +
> > +	prev_page = phy_select_page(phydev,
> > AIR_PHY_PAGE_EXTENDED_4);
> > +	if (prev_page < 0)
> > +		return prev_page;
> > +
> > +	ret = __air_buckpbus_reg_write(phydev, addr, data);
> > +
> > +	return phy_restore_page(phydev, prev_page, ret);
> > +}
> > +
> > +static int air_buckpbus_reg_read(struct phy_device *phydev, u32
> > addr, u32 *data)
> > +{
> > +	int prev_page, ret;
> > +
> > +	prev_page = phy_select_page(phydev,
> > AIR_PHY_PAGE_EXTENDED_4);
> > +	if (prev_page < 0)
> > +		return prev_page;
> > +
> > +	ret = __air_buckpbus_reg_read(phydev, addr, data);
> > +
> > +	return phy_restore_page(phydev, prev_page, ret);
> > +}
> These buckplus accessors look very similar to what's in the existing
> air_en8811h.c
> driver, any chance the code can be shared ?
> 
The buckpbus accessors functions of air_en8811h driver have indeed very
close function sequences and the defines usages to the ones in the
an8801 patches.
The main difference I see is this patch accessors do an additional
operation by setting AN8801_PBUS_ACCESS bit on the address. But it can
be done another way, so the en8811h accessors can be used without
modifications.
The existing buckpbus accessors seemed also rather generic, in
exception of air_write_buf. It may need to be modified to remove
firmware data type if it needs to be factorized (currently no need for
an8801 code).

For test purposes, I've tried to factorize the air_en8811h reg_read,
reg_write and reg_modify in a common module (similar to the existing
bcm-phy-lib used by Broadcom PHY drivers) and use them in this new
driver.
It seems to work with only a few modifications in the an8801 driver
patch and it removes these new reg_read, reg_write and reg_rmw, and a
dozen of duplicated defines.
The air_phy_read_page/air_phy_write_page implemented by air_en8811h
could also be commonized too.

Would the creation of a new Airoha PHY common module (for instance
air_phy_lib) in separate patches be the right way for this code
factorization? Or is a there an alternative solution?
> [...]
> 
> 
> > +static int an8801r_rgmii_rxdelay(struct phy_device *phydev, u16
> > delay_steps)
> > +{
> > +	u32 reg_val;
> > +
> > +	if (delay_steps > RGMII_DELAY_STEP_MASK)
> > +		return -EINVAL;
> > +
> > +	reg_val = delay_steps & RGMII_DELAY_STEP_MASK;
> > +	reg_val |= RGMII_RXDELAY_ALIGN;
> > +	reg_val |= RGMII_RXDELAY_FORCE_MODE;
> > +
> > +	return air_buckpbus_reg_write(phydev,
> > AN8801_BPBUS_REG_RXDLY_STEP,
> > +				      reg_val);
> > +}
> > +
> > +static int an8801r_rgmii_txdelay(struct phy_device *phydev, u16
> > delay_steps)
> > +{
> > +	u32 reg_val;
> > +
> > +	if (delay_steps > RGMII_DELAY_STEP_MASK)
> > +		return -EINVAL;
> > +
> > +	reg_val = delay_steps & RGMII_DELAY_STEP_MASK;
> > +	reg_val |= RGMII_TXDELAY_FORCE_MODE;
> > +
> > +	return air_buckpbus_reg_write(phydev,
> > AN8801_BPBUS_REG_TXDLY_STEP,
> > +				      reg_val);
> > +}
> > +
> > +static int an8801r_rgmii_delay_config(struct phy_device *phydev)
> > +{
> > +	switch (phydev->interface) {
> > +	case PHY_INTERFACE_MODE_RGMII_TXID:
> > +		return an8801r_rgmii_txdelay(phydev, 4);
> > +	case PHY_INTERFACE_MODE_RGMII_RXID:
> > +		return an8801r_rgmii_rxdelay(phydev, 0);
> > +	case PHY_INTERFACE_MODE_RGMII_ID:
> > +		return an8801r_rgmii_txdelay(phydev, 4);
> > +		return an8801r_rgmii_rxdelay(phydev, 0);
> > +	case PHY_INTERFACE_MODE_RGMII:
> > +	default:
> > +		return 0;
> > +	}
> 
> Can you elaborate on these values for the steps ? Why is it 4 for TX
> internal delays, but 0 for RX delays ?
I tried to find about those values and what they mean. 
The values are indeed odd, you would expect something more similar for
both rx and tx.
They come from the downstream drivers (kernel and u-boot as well) that
set them without much explanation. I did not find any info in the data
sheet I have.

I am going to look further into this.

Regards,
Louis-Alexis
> 
> Maxime

Re: [PATCH net-next 2/2] net: phy: Introduce Airoha AN8801/R Gigabit Ethernet PHY driver

[Andrew Lunn]

> +static int an8801r_did_interrupt(struct phy_device *phydev)
> +{
> +	u32 irq_en, irq_status;
> +	int ret;
> +
> +	ret = air_buckpbus_reg_read(phydev, AN8801_BPBUS_REG_WAKE_IRQ_EN,
> +				    &irq_en);
> +	if (ret)
> +		return ret;
> +
> +	ret = air_buckpbus_reg_read(phydev, AN8801_BPBUS_REG_WAKE_IRQ_STS,
> +				    &irq_status);
> +	if (ret)
> +		return ret;
> +
> +	if (irq_status & AN8801_IRQ_WAKE_MAGICPKT)
> +		return 0;

With a name like an8801r_did_interrupt() you would expect the return
value to be some value of True, if there was an interrupt. I would
suggest either a different name, or return 1. Maybe also add a
kerneldoc header indicating the return values, since it is probably
not going to be standard.

> +static void an8801r_get_wol(struct phy_device *phydev,
> +			    struct ethtool_wolinfo *wol)
> +{
> +	u32 reg_val;
> +
> +	air_buckpbus_reg_read(phydev, AN8801_BPBUS_REG_WAKEUP_CTL1, &reg_val);
> +
> +	wol->supported = WAKE_MAGIC;

How does WoL work on this device. Only via interrupts? If so, maybe
you should only return WAKE_MAGIC as supported if there is a valid
interrupt?

> +static int an8801r_rgmii_delay_config(struct phy_device *phydev)
> +{
> +	switch (phydev->interface) {
> +	case PHY_INTERFACE_MODE_RGMII_TXID:
> +		return an8801r_rgmii_txdelay(phydev, 4);
> +	case PHY_INTERFACE_MODE_RGMII_RXID:
> +		return an8801r_rgmii_rxdelay(phydev, 0);
> +	case PHY_INTERFACE_MODE_RGMII_ID:
> +		return an8801r_rgmii_txdelay(phydev, 4);
> +		return an8801r_rgmii_rxdelay(phydev, 0);

The parameters look very odd here. 4 means 2ns, but 0 also means 0ns?
Can this API be improved?

Also, PHY_INTERFACE_MODE_RGMII_TXID means 2ns delay for TX, but it
also means 0ns delay for RX. The code appears to be missing this
second part.


> +	case PHY_INTERFACE_MODE_RGMII:

And here you should be disabling all delays. We have seen boards where
the strapping is wrong, the PHY boots in RGMII_ID, but RGMII is
required, and so the driver must fully implement
PHY_INTERFACE_MODE_RGMII disabling the delays.

> +static int an8801r_config_init(struct phy_device *phydev)
> +{
> +	u8 led_default_function[AN8801R_NUM_LEDS] = { 0 };
> +	int prev_page, ret;
> +
> +	ret = an8801r_of_init_leds(phydev, led_default_function);
> +	if (ret)
> +		return ret;
> +
> +	/* Disable Low Power Mode (LPM) */
> +	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AN8801_REG_PHY_INTERNAL0,
> +			    FIELD_PREP(AN8801_PHY_INTFUNC_MASK, 0x1e));
> +	if (ret)
> +		return ret;
> +
> +	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AN8801_REG_PHY_INTERNAL1,
> +			    FIELD_PREP(AN8801_PHY_INTFUNC_MASK, 0x2));
> +	if (ret)
> +		return ret;
> +
> +	/* Disable EEE by default */
> +	ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
> +	if (ret)
> +		return ret;

Why? If EEE is broken, this is not sufficient to stop a user
re-enabling it.

> +static int an8801r_read_status(struct phy_device *phydev)
> +{
> +	int prev_speed, ret;
> +	u32 val;
> +
> +	prev_speed = phydev->speed;
> +
> +	ret = genphy_read_status(phydev);
> +	if (ret)
> +		return ret;

You configure the PHY to support downshift. If it has performed a
downshift, does it report the actual speed in the usual registers read
by genphy_read_status(), or is it necessary to read a vendor register?

> +static struct phy_driver airoha_driver[] = {
> +{
> +	PHY_ID_MATCH_MODEL(AN8801R_PHY_ID),
> +	.name			= "Airoha AN8801R",
> +	.features		= PHY_GBIT_FEATURES,

Should not be needed, if the PHY enumerates its capabilities
correctly.

    Andrew

---
pw-bot: cr

Re: [PATCH net-next 2/2] net: phy: Introduce Airoha AN8801/R Gigabit Ethernet PHY driver

[Louis-Alexis Eyraud]

Hi Andrew,

On Wed, 2026-03-04 at 15:59 +0100, Andrew Lunn wrote:
> > +static int an8801r_did_interrupt(struct phy_device *phydev)
> > +{
> > +	u32 irq_en, irq_status;
> > +	int ret;
> > +
> > +	ret = air_buckpbus_reg_read(phydev,
> > AN8801_BPBUS_REG_WAKE_IRQ_EN,
> > +				    &irq_en);
> > +	if (ret)
> > +		return ret;
> > +
> > +	ret = air_buckpbus_reg_read(phydev,
> > AN8801_BPBUS_REG_WAKE_IRQ_STS,
> > +				    &irq_status);
> > +	if (ret)
> > +		return ret;
> > +
> > +	if (irq_status & AN8801_IRQ_WAKE_MAGICPKT)
> > +		return 0;
> 
> With a name like an8801r_did_interrupt() you would expect the return
> value to be some value of True, if there was an interrupt. I would
> suggest either a different name, or return 1. Maybe also add a
> kerneldoc header indicating the return values, since it is probably
> not going to be standard.
> 
The function name was not great and confusing.

While reworking the interrupt handling for WoL support for v2, I merged
the function with the an8801r_handle_interrupt function (to process
differently the Magic Packet and Link Change interrupts) so this
function won't be in v2.
 
> > +static void an8801r_get_wol(struct phy_device *phydev,
> > +			    struct ethtool_wolinfo *wol)
> > +{
> > +	u32 reg_val;
> > +
> > +	air_buckpbus_reg_read(phydev,
> > AN8801_BPBUS_REG_WAKEUP_CTL1, &reg_val);
> > +
> > +	wol->supported = WAKE_MAGIC;
> 
> How does WoL work on this device. Only via interrupts? If so, maybe
> you should only return WAKE_MAGIC as supported if there is a valid
> interrupt?
> 
Yes, the WoL works via interrupts and indeed it lacks the interrupt
validity check.

In v2, following the RTL8211F wake-on-lan support example given to me
by Russell in his review, I'll fix this by adding a check using
device_can_wakeup in an8801r_get_wol and an8801r_set_wol functions and
adding a probe function (there was none in v1) to mark the PHY device
as wakeup capable if it has a valid interrupt and if the wakeup-source
property is present in the devicetree for the device node.

> > +static int an8801r_rgmii_delay_config(struct phy_device *phydev)
> > +{
> > +	switch (phydev->interface) {
> > +	case PHY_INTERFACE_MODE_RGMII_TXID:
> > +		return an8801r_rgmii_txdelay(phydev, 4);
> > +	case PHY_INTERFACE_MODE_RGMII_RXID:
> > +		return an8801r_rgmii_rxdelay(phydev, 0);
> > +	case PHY_INTERFACE_MODE_RGMII_ID:
> > +		return an8801r_rgmii_txdelay(phydev, 4);
> > +		return an8801r_rgmii_rxdelay(phydev, 0);
> 
> The parameters look very odd here. 4 means 2ns, but 0 also means 0ns?
> Can this API be improved?
From the info I finally got about these magic values, the differences
between the RX and TX values for the default insert delays can be
explained by the additional RGMII_RXDELAY_ALIGN bit setting when
writing the RX delay register (AN8801_BPBUS_REG_RXDLY_STEP), done by
an8801r_rgmii_rxdelay function because it adds an extra offset.

For TX, the 4 value is the delay step value that is the closest to 2ns
(1.883ns). But For RX, setting the step value to 0 and setting the
RGMII_RXDELAY_ALIGN bit too, inserts a 1.992ns delay. Without align
bit, it would indeed be -0.008ns.

Those delays are also inserted because the an8801r_rgmii_rxdelay and
an8801r_rgmii_txdelay function set the force mode bit
(RGMII_RXDELAY_FORCE_MODE / RGMII_TXDELAY_FORCE_MODE). 
If this bit is unset, it prevents inserting a delay.

> Also, PHY_INTERFACE_MODE_RGMII_TXID means 2ns delay for TX, but it
> also means 0ns delay for RX. The code appears to be missing this
> second part.
> 
There is indeed a bug with this double return in
PHY_INTERFACE_MODE_RGMII_ID case so the RX delay is not inserted.

> > +	case PHY_INTERFACE_MODE_RGMII:
> 
> And here you should be disabling all delays. We have seen boards
> where
> the strapping is wrong, the PHY boots in RGMII_ID, but RGMII is
> required, and so the driver must fully implement
> PHY_INTERFACE_MODE_RGMII disabling the delays.
> 
You're right it is also missing the delay disabling part.

The an8801r_rgmii_txdelay and an8801r_rgmii_rxdelay function don't
allow to disable them since they always set force mode bit and because
the 0 values does not completely mean no inserted delay.
Their implementations should be modify to be able to do that.

For v2, I've reworked the an8801r_rgmii_delay_config and
an8801r_rgmii_rx/txdelay to handle properly all RGMII configuration
cases and I hope in a simpler manner.

> > +static int an8801r_config_init(struct phy_device *phydev)
> > +{
> > +	u8 led_default_function[AN8801R_NUM_LEDS] = { 0 };
> > +	int prev_page, ret;
> > +
> > +	ret = an8801r_of_init_leds(phydev, led_default_function);
> > +	if (ret)
> > +		return ret;
> > +
> > +	/* Disable Low Power Mode (LPM) */
> > +	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
> > AN8801_REG_PHY_INTERNAL0,
> > +			    FIELD_PREP(AN8801_PHY_INTFUNC_MASK,
> > 0x1e));
> > +	if (ret)
> > +		return ret;
> > +
> > +	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
> > AN8801_REG_PHY_INTERNAL1,
> > +			    FIELD_PREP(AN8801_PHY_INTFUNC_MASK,
> > 0x2));
> > +	if (ret)
> > +		return ret;
> > +
> > +	/* Disable EEE by default */
> > +	ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
> > 0);
> > +	if (ret)
> > +		return ret;
> 
> Why? If EEE is broken, this is not sufficient to stop a user
> re-enabling it.
> 
I've tested by removing these lines and EEE seems working fine.
I'll remove them in v2.

> > +static int an8801r_read_status(struct phy_device *phydev)
> > +{
> > +	int prev_speed, ret;
> > +	u32 val;
> > +
> > +	prev_speed = phydev->speed;
> > +
> > +	ret = genphy_read_status(phydev);
> > +	if (ret)
> > +		return ret;
> 
> You configure the PHY to support downshift. If it has performed a
> downshift, does it report the actual speed in the usual registers
> read
> by genphy_read_status(), or is it necessary to read a vendor
> register?
From the tests I've done, I got the actual speed read correctly by
genphy_read_status function.
I did a test by adding in this function the vendor register reading at
the same time and comparing it and did not get a discrepancy too when
switching with ethtool between different speed configurations.

Would it be more reliable to use the vendor register instead?

> 
> > +static struct phy_driver airoha_driver[] = {
> > +{
> > +	PHY_ID_MATCH_MODEL(AN8801R_PHY_ID),
> > +	.name			= "Airoha AN8801R",
> > +	.features		= PHY_GBIT_FEATURES,
> 
> Should not be needed, if the PHY enumerates its capabilities
> correctly.
I confirm it is not needed, I'll remove it in v2.

Thanks for the review.

Regards,
Louis-Alexis

> 
>     Andrew
> 
> ---
> pw-bot: cr

Re: [PATCH net-next 2/2] net: phy: Introduce Airoha AN8801/R Gigabit Ethernet PHY driver

[Andrew Lunn]

> > You configure the PHY to support downshift. If it has performed a
> > downshift, does it report the actual speed in the usual registers
> > read
> > by genphy_read_status(), or is it necessary to read a vendor
> > register?
> >From the tests I've done, I got the actual speed read correctly by
> genphy_read_status function.
> I did a test by adding in this function the vendor register reading at
> the same time and comparing it and did not get a discrepancy too when
> switching with ethtool between different speed configurations.
> 
> Would it be more reliable to use the vendor register instead?

It is unusual to report the actually speed in BMSR etc, which is why i
asked. But if it works, this is fine.

       Andrew

Re: [PATCH net-next 2/2] net: phy: Introduce Airoha AN8801/R Gigabit Ethernet PHY driver

[Russell King (Oracle)]

On Wed, Mar 04, 2026 at 10:35:29AM +0100, Louis-Alexis Eyraud wrote:
> +static void an8801r_get_wol(struct phy_device *phydev,
> +			    struct ethtool_wolinfo *wol)
> +{
> +	u32 reg_val;
> +
> +	air_buckpbus_reg_read(phydev, AN8801_BPBUS_REG_WAKEUP_CTL1, &reg_val);
> +
> +	wol->supported = WAKE_MAGIC;
> +
> +	if (reg_val & AN8801_WOL_WAKE_MAGIC_EN)
> +		wol->wolopts |= WAKE_MAGIC;
> +	else
> +		wol->wolopts &= ~WAKE_MAGIC;

Please only support WoL if you know that the PHY has been wired up in
such a way to allow it to actually wake the system. The PHY itself
merely supporting WoL is insufficient.

Please look at my recent change to realtek_main.c in commit
b826bf795564 ("net: phy: realtek: fix RTL8211F wake-on-lan support")
to see a possible way to achieve this.

> +static int an8801r_config_init(struct phy_device *phydev)
> +{
> +	u8 led_default_function[AN8801R_NUM_LEDS] = { 0 };
> +	int prev_page, ret;
> +
> +	ret = an8801r_of_init_leds(phydev, led_default_function);
> +	if (ret)
> +		return ret;
> +
> +	/* Disable Low Power Mode (LPM) */
> +	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AN8801_REG_PHY_INTERNAL0,
> +			    FIELD_PREP(AN8801_PHY_INTFUNC_MASK, 0x1e));
> +	if (ret)
> +		return ret;
> +
> +	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AN8801_REG_PHY_INTERNAL1,
> +			    FIELD_PREP(AN8801_PHY_INTFUNC_MASK, 0x2));
> +	if (ret)
> +		return ret;
> +
> +	/* Disable EEE by default */
> +	ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
> +	if (ret)
> +		return ret;

Are you sure this is safe, e.g. over a suspend/resume, and doesn't
cause the hardware vs software state to desync?

> +
> +	prev_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_1);
> +	if (prev_page < 0)
> +		return prev_page;

No, this is buggy. Please read the phy_select_page() documentation to
find out why.

> +
> +	/* Set the PHY to perform auto-downshift after 3 auto-negotiation
> +	 * attempts
> +	 */
> +	__phy_write(phydev, AN8801_EXT_REG_PHY,
> +		    FIELD_PREP(AN8801_EXT_PHY_CTRL1, 0x1d) |
> +		    FIELD_PREP(AN8801_EXT_PHY_DOWNSHIFT_CTL, 1) |
> +		    AN8801_EXT_PHY_DOWNSHIFT_EN);
> +
> +	ret = phy_restore_page(phydev, prev_page, ret);
> +	if (ret)
> +		return ret;

However, the bug could've been avoided by using the appropriate
accessor:

	ret = phy_write_paged(phydev, AIR_PHY_PAGE_EXTENDED_1,
			      AN8801_EXT_REG_PHY,
			      FIELD_PREP(AN8801_EXT_PHY_CTRL1, 0x1d) |
			      FIELD_PREP(AN8801_EXT_PHY_DOWNSHIFT_CTL, 1) |
			      AN8801_EXT_PHY_DOWNSHIFT_EN);
	if (ret < 0)
		return ret;

> +static int an8801r_read_status(struct phy_device *phydev)
> +{
> +	int prev_speed, ret;
> +	u32 val;
> +
> +	prev_speed = phydev->speed;
> +
> +	ret = genphy_read_status(phydev);
> +	if (ret)
> +		return ret;
> +
> +	if (!phydev->link)
> +		return 0;
> +
> +	if (prev_speed != phydev->speed) {

Maybe:

	if (phydev->link && prev_speed != phydev->speed) {

?

Thanks.

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Re: [PATCH net-next 2/2] net: phy: Introduce Airoha AN8801/R Gigabit Ethernet PHY driver

[Louis-Alexis Eyraud]

Hi Russell,

On Wed, 2026-03-04 at 16:32 +0000, Russell King (Oracle) wrote:
> On Wed, Mar 04, 2026 at 10:35:29AM +0100, Louis-Alexis Eyraud wrote:
> > +static void an8801r_get_wol(struct phy_device *phydev,
> > +			    struct ethtool_wolinfo *wol)
> > +{
> > +	u32 reg_val;
> > +
> > +	air_buckpbus_reg_read(phydev,
> > AN8801_BPBUS_REG_WAKEUP_CTL1, &reg_val);
> > +
> > +	wol->supported = WAKE_MAGIC;
> > +
> > +	if (reg_val & AN8801_WOL_WAKE_MAGIC_EN)
> > +		wol->wolopts |= WAKE_MAGIC;
> > +	else
> > +		wol->wolopts &= ~WAKE_MAGIC;
> 
> Please only support WoL if you know that the PHY has been wired up in
> such a way to allow it to actually wake the system. The PHY itself
> merely supporting WoL is insufficient.
> 
> Please look at my recent change to realtek_main.c in commit
> b826bf795564 ("net: phy: realtek: fix RTL8211F wake-on-lan support")
> to see a possible way to achieve this.
> 
First, sorry for the delay, and thank you for pointing out this commit.

It indeed showed me what the WoL implementation for this PHY driver was
missing, not only for the get_wol/set_wol but also elsewhere in the
driver.

So for v2, I've reworked in a similar way the get_wol/set_wol, the
interrupt handling (to process differently the magic packet and the
link change interrupts) and also added custom probe, suspend and resume
callbacks (to be able to disable link change interrupt during suspend
time and enable it again after resume if the user has enabled the WoL
setting, like you did for RTL8211F).

I had a bit of trouble make it work right. At first I could not read
properly the PHY buckpbus registers in the suspend callback, and adding
a delay at resume time was needed as a workaround to make the WoL
behaviour work consistently. But in the end I found out it was the
Ethernet interface pinctrl config for sleep state in my board
devicetree that caused me those issues.
It works fine now without any workaround.

> > +static int an8801r_config_init(struct phy_device *phydev)
> > +{
> > +	u8 led_default_function[AN8801R_NUM_LEDS] = { 0 };
> > +	int prev_page, ret;
> > +
> > +	ret = an8801r_of_init_leds(phydev, led_default_function);
> > +	if (ret)
> > +		return ret;
> > +
> > +	/* Disable Low Power Mode (LPM) */
> > +	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
> > AN8801_REG_PHY_INTERNAL0,
> > +			    FIELD_PREP(AN8801_PHY_INTFUNC_MASK,
> > 0x1e));
> > +	if (ret)
> > +		return ret;
> > +
> > +	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
> > AN8801_REG_PHY_INTERNAL1,
> > +			    FIELD_PREP(AN8801_PHY_INTFUNC_MASK,
> > 0x2));
> > +	if (ret)
> > +		return ret;
> > +
> > +	/* Disable EEE by default */
> > +	ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
> > 0);
> > +	if (ret)
> > +		return ret;
> 
> Are you sure this is safe, e.g. over a suspend/resume, and doesn't
> cause the hardware vs software state to desync? 
While reworking PHY WoL support, I've tested removing this EEE
disabling done during driver initial config and I did not notice any
particular issue, especially during suspend/resume sequences. Still
unsure why the downstream driver disabled it in first place.

The EEE support seems working fine too from what ethtool reports on my
board, so I'll remove the lines from v2.
> 
> > +
> > +	prev_page = phy_select_page(phydev,
> > AIR_PHY_PAGE_EXTENDED_1);
> > +	if (prev_page < 0)
> > +		return prev_page;
> 
> No, this is buggy. Please read the phy_select_page() documentation to
> find out why.
> 
> > +
> > +	/* Set the PHY to perform auto-downshift after 3 auto-
> > negotiation
> > +	 * attempts
> > +	 */
> > +	__phy_write(phydev, AN8801_EXT_REG_PHY,
> > +		    FIELD_PREP(AN8801_EXT_PHY_CTRL1, 0x1d) |
> > +		    FIELD_PREP(AN8801_EXT_PHY_DOWNSHIFT_CTL, 1) |
> > +		    AN8801_EXT_PHY_DOWNSHIFT_EN);
> > +
> > +	ret = phy_restore_page(phydev, prev_page, ret);
> > +	if (ret)
> > +		return ret;
> 
> However, the bug could've been avoided by using the appropriate
> accessor:
> 
> 	ret = phy_write_paged(phydev, AIR_PHY_PAGE_EXTENDED_1,
> 			      AN8801_EXT_REG_PHY,
> 			      FIELD_PREP(AN8801_EXT_PHY_CTRL1, 0x1d)
> |
> 			     
> FIELD_PREP(AN8801_EXT_PHY_DOWNSHIFT_CTL, 1) |
> 			      AN8801_EXT_PHY_DOWNSHIFT_EN);
> 	if (ret < 0)
> 		return ret;
thanks for catching this bug.
I've replaced for v2 the __phy_write call by phy_write_paged cas you
suggested.
> > +static int an8801r_read_status(struct phy_device *phydev)
> > +{
> > +	int prev_speed, ret;
> > +	u32 val;
> > +
> > +	prev_speed = phydev->speed;
> > +
> > +	ret = genphy_read_status(phydev);
> > +	if (ret)
> > +		return ret;
> > +
> > +	if (!phydev->link)
> > +		return 0;
> > +
> > +	if (prev_speed != phydev->speed) {
> 
> Maybe:
> 
> 	if (phydev->link && prev_speed != phydev->speed) {
> 
> ?
Ack.

Thanks again for the review.

Regards,
Louis-Alexis
> 
> Thanks.

Re: [PATCH net-next 2/2] net: phy: Introduce Airoha AN8801/R Gigabit Ethernet PHY driver

[kernel test robot]

Hi Louis-Alexis,

kernel test robot noticed the following build warnings:

[auto build test WARNING on ed0abfe93fd135dac223e87a3c945017b1fa8bfc]

url:    https://github.com/intel-lab-lkp/linux/commits/Louis-Alexis-Eyraud/dt-bindings-net-Add-support-for-Airoha-AN8801-R-GbE-PHY/20260304-174023
base:   ed0abfe93fd135dac223e87a3c945017b1fa8bfc
patch link:    https://lore.kernel.org/r/20260304-add-airoha-an8801-support-v1-2-0ae4ee5a2f9d%40collabora.com
patch subject: [PATCH net-next 2/2] net: phy: Introduce Airoha AN8801/R Gigabit Ethernet PHY driver
config: sparc64-allmodconfig (https://download.01.org/0day-ci/archive/20260305/202603050606.eulVmYcb-lkp@intel.com/config)
compiler: clang version 23.0.0git (https://github.com/llvm/llvm-project 9a109fbb6e184ec9bcce10615949f598f4c974a9)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260305/202603050606.eulVmYcb-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603050606.eulVmYcb-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/net/phy/air_an8801.c:258:6: warning: variable 'pbus_data_h' is uninitialized when used here [-Wuninitialized]
     258 |         if (pbus_data_h < 0)
         |             ^~~~~~~~~~~
   drivers/net/phy/air_an8801.c:240:30: note: initialize the variable 'pbus_data_h' to silence this warning
     240 |         int pbus_data_l, pbus_data_h;
         |                                     ^
         |                                      = 0
   1 warning generated.


vim +/pbus_data_h +258 drivers/net/phy/air_an8801.c

   236	
   237	static int __air_buckpbus_reg_read(struct phy_device *phydev,
   238					   u32 addr, u32 *data)
   239	{
   240		int pbus_data_l, pbus_data_h;
   241		int ret;
   242	
   243		addr |= AN8801_PBUS_ACCESS;
   244	
   245		ret = __phy_write(phydev, AIR_BPBUS_MODE, MII_MMD_CTRL_ADDR);
   246		if (ret < 0)
   247			return ret;
   248	
   249		ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_HIGH, upper_16_bits(addr));
   250		if (ret < 0)
   251			return ret;
   252	
   253		ret = __phy_write(phydev, AIR_BPBUS_RD_ADDR_LOW, lower_16_bits(addr));
   254		if (ret < 0)
   255			return ret;
   256	
   257		ret = __phy_read(phydev, AIR_BPBUS_RD_DATA_HIGH);
 > 258		if (pbus_data_h < 0)
   259			return pbus_data_h;
   260	
   261		pbus_data_l = __phy_read(phydev, AIR_BPBUS_RD_DATA_LOW);
   262		if (pbus_data_l < 0)
   263			return pbus_data_l;
   264	
   265		*data = (pbus_data_h << 16) | pbus_data_l;
   266		return 0;
   267	}
   268	

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https://github.com/intel/lkp-tests/wiki