From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 092FB293B75; Wed, 18 Mar 2026 21:23:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773869035; cv=none; b=soSQzeoh3vQRFRfiH2+ZQ2fUnh+BXeO2oqT55vDfMv+psSblvihNK3EJhHswnI8AY4IOR3qxIkotsuPoxD3bxlyl+2ELuOyMz0bgEOvs1LDD5I/VzrHi7R1ucAOhTd1GGvXwrJgd9JWX2oyoizKRs3K97VUtWdlladLxbiOO5EI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773869035; c=relaxed/simple; bh=diJ9QPPY6KW09PwuO6V9voRGxd18I3VD+Tg2MitGWWU=; h=Date:From:To:CC:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=Vc++L/GMen1W64az9mb0LO0LKUeGvpZk9cva5A0sFZj6p3/iT7pskwjQeZ5zdNkOQyN5I1Sg77+0ynBnXiMS7DKZdiRDCrzxhqoJDLv5ZVvGRWQZgg+GI1a+FyARpCJE6eGUtwXQtj3+D/GcAUK/vQ4pwkBHWVhe0Z0Rp9oxmmo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=wf3x76I2; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="wf3x76I2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1773869034; x=1805405034; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=diJ9QPPY6KW09PwuO6V9voRGxd18I3VD+Tg2MitGWWU=; b=wf3x76I2cZ5jkqsHA221WKYqlZD55zInLdt1ONPAVqVKqlZwufEFpLBZ hO7N/UznKRkXZZV1Uh+nCXSQaq87nTjheqB1CqgvDtO86uaeUKQOEr3AL hMYm1dCqp8L7Oo5V0m1tHfYp11+teCEacOznmFa2bR1Iuwjp7tNAj88v1 RTjF7s5hcQ7BvfofVQrQEXAYChT4xvGQGkLO2kAFtN0nt6p3bu5MLv3O7 nBdD94EQMS1ZOgO+Lf01XmKNGwunNHNL7mmfpdX714B1k81mL3BPKtXSH I6pUfj7tT/jZowigaO0WBNfqjo1JRiMnnOr18emXnSsVejSDLIMBb30bX Q==; X-CSE-ConnectionGUID: fmMH9kipSzyI1CxnMFzQBQ== X-CSE-MsgGUID: pae+xRSJQsmKA7b9gwOPtQ== X-IronPort-AV: E=Sophos;i="6.23,128,1770620400"; d="scan'208";a="54865784" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 18 Mar 2026 14:23:53 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Wed, 18 Mar 2026 14:23:27 -0700 Received: from bby-cbu-swbuild03.eng.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58 via Frontend Transport; Wed, 18 Mar 2026 14:23:24 -0700 Date: Wed, 18 Mar 2026 14:23:23 -0700 From: Charles Perry To: Conor Dooley CC: Charles Perry , , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , "Paolo Abeni" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , , Subject: Re: [PATCH net-next 1/2] dt-bindings: net: document Microchip PIC64-HPSC/HX MDIO controller Message-ID: References: <20260317184610.315852-1-charles.perry@microchip.com> <20260317184610.315852-2-charles.perry@microchip.com> <20260318-suspense-arming-fe118c3f15c6@spud> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260318-suspense-arming-fe118c3f15c6@spud> On Wed, Mar 18, 2026 at 05:48:08PM +0000, Conor Dooley wrote: > On Tue, Mar 17, 2026 at 11:46:09AM -0700, Charles Perry wrote: > > This MDIO hardware is based on a Microsemi design supported in Linux by > > mdio-mscc-miim.c. However, The register interface is completely different > > with pic64hpsc, hence the need for separate documentation. > > > > The hardware supports C22 and C45. > > > > The documentation recommends an input clock of 156.25MHz and a prescaler > > of 39, which yields an MDIO clock of 1.95MHz. > > > > The hardware supports an interrupt pin to signal transaction completion > > which is not strictly needed as the software can also poll a "TRIGGER" > > bit for this. > > > > Signed-off-by: Charles Perry > > --- > > .../net/microchip,pic64hpsc-mdio.yaml | 61 +++++++++++++++++++ > > 1 file changed, 61 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/net/microchip,pic64hpsc-mdio.yaml > > > > diff --git a/Documentation/devicetree/bindings/net/microchip,pic64hpsc-mdio.yaml b/Documentation/devicetree/bindings/net/microchip,pic64hpsc-mdio.yaml > > new file mode 100644 > > index 000000000000..21c76199c11b > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/net/microchip,pic64hpsc-mdio.yaml > > @@ -0,0 +1,61 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/net/microchip,pic64hpsc-mdio.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Microchip PIC64-HPSC/HX MDIO controller > > + > > +maintainers: > > + - Charles Perry > > + > > +description: | > > + Microchip PIC64-HPSC/HX SoCs have two MDIO bus controller. This MDIO bus > > + controller supports C22 and C45 register access. It is named "MDIO Initiator" > > + in the documentation. > > + > > +allOf: > > + - $ref: mdio.yaml# > > + > > +properties: > > + compatible: > > + oneOf: > > + - const: microchip,pic64hpsc-mdio > > + - items: > > + - const: microchip,pic64hx-mdio > > + - const: microchip,pic64hpsc-mdio > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 1 > > + > > + clock-frequency: true > > Does this genuinely have no constraints? It's going to divide the input frequency by 2 to 512 (the prescaler is 8 bit long), so assuming an input clock of 156.25 MHz, the bounds are 305KHz to 78MHz. The standard is 2.5MHz. I can add a maximum and minimum here since I do have some validation on this in the driver which will bail out if this is out of bound. Thanks, Charles