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[79.47.155.212]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45055960902sm4932144f8f.28.2026.05.05.06.14.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 May 2026 06:14:17 -0700 (PDT) From: Andrea della Porta X-Google-Original-From: Andrea della Porta Date: Tue, 5 May 2026 15:17:33 +0200 To: Lukasz Raczylo Cc: netdev@vger.kernel.org, Nicolas Ferre , Claudiu Beznea , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org Subject: Re: [RFC PATCH net-next 1/3] net: macb: flush PCIe posted write after TSTART doorbell Message-ID: References: <3106d546d494f2f52ec832e7f7d04f534286e254.1777064117.git.lukasz@raczylo.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <3106d546d494f2f52ec832e7f7d04f534286e254.1777064117.git.lukasz@raczylo.com> Hi Lukasz, On 23:38 Fri 24 Apr , Lukasz Raczylo wrote: > macb_start_xmit() and macb_tx_restart() kick transmission by > OR-ing MACB_BIT(TSTART) into NCR. On PCIe-attached macb instances > (BCM2712 + RP1 PCIe south bridge on Raspberry Pi 5 is the setup we > have in front of us), writes to NCR are posted PCIe writes: they > are not guaranteed to reach the device before the issuing CPU > returns. If the TSTART doorbell does not reach the MAC, no TX > begins, no TCOMP completion arrives, and the ring remains > quiescent without any kernel-visible indication. > > Note that the raspberrypi/linux vendor fork carries a local patch > around the TSTART site (a queue->tx_pending breadcrumb that is > promoted to queue->txubr_pending by the next TCOMP interrupt, > triggering macb_tx_restart()). That workaround makes the loss > recoverable under traffic, but it cannot help if TCOMP itself is > not raised because no TX started -- which is exactly the case we > are targeting here. The handshake is not present in mainline. > > Add a read-back of NCR after each TSTART write in macb_start_xmit() > and macb_tx_restart(). The read is an architected PCIe read > barrier for earlier posted writes on the same path; it ensures the > doorbell has reached the MAC before the functions return. > > We do not yet have direct hardware evidence that TSTART is being > lost on the RP1 path (that would require a PCIe protocol analyser, > or at minimum a before/after counter on queue->tx_stall_last_tail > with and without this patch applied in isolation). This patch is > one of a three-patch series ("candidate fixes for silent TX stall > on BCM2712/RP1"); see the cover letter for context. We have > verified the series compiles and applies cleanly against mainline > HEAD and against raspberrypi/linux rpi-6.18.y @ f2f68e79f16f; > runtime verification is pending. > > Link: https://github.com/cilium/cilium/issues/43198 > Link: https://bugs.launchpad.net/ubuntu/+source/linux-raspi/+bug/2133877 > Signed-off-by: Lukasz Raczylo > --- > drivers/net/ethernet/cadence/macb_main.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c > index a12aa2124..b6cca55ad 100644 > --- a/drivers/net/ethernet/cadence/macb_main.c > +++ b/drivers/net/ethernet/cadence/macb_main.c > @@ -1922,6 +1922,13 @@ static void macb_tx_restart(struct macb_queue *queue) > > spin_lock(&bp->lock); > macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); > + /* > + * Flush the PCIe posted-write queue so the TSTART doorbell > + * reliably reaches the MAC. Without this, the write can sit > + * in the fabric and the MAC never advances, causing a silent > + * TX stall. > + */ > + (void)macb_readl(bp, NCR); Do you expect it to be a temporal issue (in the comment you stated that the write should be delivered before the function returns) or is it just a dropped packet error? In the former case can you please explain why? If it's the latter, I'd expect the dropped packet to increment the counter in the AER, and I'm pretty sure it didn't when I performed my tests. Many thanks, Andrea > spin_unlock(&bp->lock); > > out_tx_ptr_unlock: > @@ -2560,6 +2567,11 @@ static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev) > spin_lock(&bp->lock); > macb_tx_lpi_wake(bp); > macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART)); > + /* > + * Flush the PCIe posted-write queue; see the comment in > + * macb_tx_restart() for the reasoning. > + */ > + (void)macb_readl(bp, NCR); > spin_unlock(&bp->lock); > > if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1) > -- > 2.53.0 >