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Wed, 13 May 2026 21:15:01 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Wed, 13 May 2026 21:15:00 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Wed, 13 May 2026 21:15:00 -0700 Received: from rkannoth-OptiPlex-7090 (unknown [10.28.36.165]) by maili.marvell.com (Postfix) with SMTP id 813815B6938; Wed, 13 May 2026 21:14:52 -0700 (PDT) Date: Thu, 14 May 2026 09:44:51 +0530 From: Ratheesh Kannoth To: , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v13 net-next 8/9] octeontx2: cn20k: Respect NPC MCAM X2/X4 profile in flows and DFT alloc Message-ID: References: <20260511033923.1301976-1-rkannoth@marvell.com> <20260511033923.1301976-9-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260511033923.1301976-9-rkannoth@marvell.com> X-Proofpoint-GUID: v01W4DoBFcy66W4jTOZ5VT9iFySjrkHk X-Proofpoint-ORIG-GUID: v01W4DoBFcy66W4jTOZ5VT9iFySjrkHk X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE0MDAzOCBTYWx0ZWRfX3sGxgTUqlu/4 PIFvR1NarJGGYPyASi175bliOOTJbXvYYeHpzddXpxrtfGcVlyJdmCcnZekmHI/KJm14mkGWLw4 SNzAitmyf+7ZiQRAJakdMVW5JyPV4d8qs1v88923mMIn0huovujWQJ3QpFbGEW5cQWM7OrbjmHB pJlw2uBblMej//NiUd78F2QOrcuKZoOqsAJYJuHMAO+bERCFlLPH+L76V4nFAbhnuHDTGE+oAEh WCgg/2FaflcpCtHBTIM3MDGeHt2/QwAVDGvgj39aSwMTnUnaoAFJ9boDbxPnjdT9CFUzC/SDPZB gpy8KEq4OVlYA96WhogGyqQNKXRyUTxXanDUgW0rqjH0FBkZZ8473MscQLgrTgmi03LzZmYi2Qp KbPEVRPcd/PTnChkMkmi5Mx0rngJwvGx/cu+dSdnp4x8Zcr2sQx/ke1oz+Bvz4oUifqxnX8n653 1Kc+cSZQCgGkwsySUHA== X-Authority-Analysis: v=2.4 cv=ZtTd7d7G c=1 sm=1 tr=0 ts=6a054c45 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=kj9zAlcOel0A:10 a=NGcC8JguVDcA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=TtqV-g6YmW1Jfm2GSLaY:22 a=M5GUcnROAAAA:8 a=fCIphdZVNb5Y-s_u9r8A:9 a=CjuIK1q_8ugA:10 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-14_01,2026-05-13_01,2025-10-01_01 On 2026-05-11 at 09:09:22, Ratheesh Kannoth (rkannoth@marvell.com) wrote: > Default CN20K NPC rule allocation now keys off the active MCAM keyword > width: use X4 with a bank-masked reference index when the silicon uses > X4 keys, and X2 with the raw index otherwise (replacing the previous > always-X2 / eidx + 1 behaviour). >> -static int otx2_mcam_pfl_info_get(struct otx2_nic *pfvf, bool *is_x2, >> - u16 *x4_slots) >> +static int otx2_mcam_pfl_info_get(struct otx2_nic *pfvf, u16 *x4_slots, u8 *kw_type) >> { >> struct npc_get_pfl_info_rsp *rsp; >> struct msg_req *req; >> static struct { >> bool is_set; >> - bool is_x2; >> + u8 kw_type; >> u16 x4_slots; >> } pfl_info; >> >> @@ -53,8 +52,8 @@ static int otx2_mcam_pfl_info_get(struct otx2_nic *pfvf, bool *is_x2, >> */ >> mutex_lock(&pfvf->mbox.lock); >> if (pfl_info.is_set) { >This isn't a bug introduced by this patch, but caching device properties in Since this is not a bug in this patch, not planning to address as part of this series. >> @@ -164,6 +163,7 @@ int otx2_alloc_mcam_entries(struct otx2_nic *pfvf, u16 count) >> u16 dft_idx = 0, x4_slots = 0; >> int ent, allocated = 0, ref; >> bool is_x2 = false; >> + u8 kw_type = 0; >> int rc; >> >> /* Free current ones and allocate new ones with requested count */ >> @@ -182,12 +182,14 @@ int otx2_alloc_mcam_entries(struct otx2_nic *pfvf, u16 count) >> } >> >> if (is_cn20k(pfvf->pdev)) { >> - rc = otx2_mcam_pfl_info_get(pfvf, &is_x2, &x4_slots); >> + rc = otx2_mcam_pfl_info_get(pfvf, &x4_slots, &kw_type); >> if (rc) { >> netdev_err(pfvf->netdev, "Error to retrieve profile info\n"); >> return rc; >> } >This is an existing issue on this code path, but if otx2_mcam_pfl_info_get() >fails here, or if otx2_get_dft_rl_idx() fails below, the function returns >early without updating flow_cfg->max_flows. Since this is not a bug in this patch, not planning to address as part of this series. >> @@ -1174,15 +1192,14 @@ static int otx2_add_flow_msg(struct otx2_nic *pfvf, struct otx2_flow *flow) >> #ifdef CONFIG_DCB >> int vlan_prio, qidx, pfc_rule = 0; >> #endif >> + bool modify = false, is_x2; >> int err, vf = 0, off, sz; >> - bool modify = false; >> u8 kw_type = 0; >> u8 *src, *dst; >> u16 x4_slots; >> - bool is_x2; >> >> if (is_cn20k(pfvf->pdev)) { >> - err = otx2_mcam_pfl_info_get(pfvf, &is_x2, &x4_slots); >> + err = otx2_mcam_pfl_info_get(pfvf, &x4_slots, &kw_type); >> if (err) { >This is another existing issue in this function. If we trace further down >in otx2_add_flow_msg() after the mailbox message is allocated: > req = otx2_mbox_alloc_msg_npc_install_flow(&pfvf->mbox); > ... > vf = ethtool_get_flow_spec_ring_vf(ring_cookie); > if (vf > pci_num_vf(pfvf->pdev)) { > mutex_unlock(&pfvf->mbox.lock); > return -EINVAL; > } >Does this error path abandon the partially constructed message in the mailbox >queue? Would adding a call to otx2_mbox_reset(&pfvf->mbox.mbox, 0) before >returning prevent this incomplete message from being transmitted during the >next mailbox sync? Since this is not a bug in this patch, not planning to address as part of this series. > > In the AF flow-install path, flows that need more than 256 key bits > query the NPC profile; if the platform is fixed to X2 entries, fail > with -EOPNOTSUPP instead of requesting X4. Otherwise select X4 for the > MCAM alloc. > > On the PF, cache and pass the profile kw_type from npc_get_pfl_info > through otx2_mcam_pfl_info_get(), and use it when allocating MCAM > entries for RSS/defaults and when installing ethtool flows on CN20K, > including masking the reference index for X4 slot layout. > > Signed-off-by: Ratheesh Kannoth > --- > .../ethernet/marvell/octeontx2/af/cn20k/npc.c | 21 ++++++-- > .../marvell/octeontx2/af/rvu_npc_fs.c | 12 ++++- > .../marvell/octeontx2/nic/otx2_flows.c | 48 +++++++++++++------ > 3 files changed, 61 insertions(+), 20 deletions(-) > > diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c > index 88cfa6c67266..ff5baedbc122 100644 > --- a/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c > +++ b/drivers/net/ethernet/marvell/octeontx2/af/cn20k/npc.c > @@ -4438,10 +4438,16 @@ int npc_cn20k_dft_rules_alloc(struct rvu *rvu, u16 pcifunc) > pfvf = rvu_get_pfvf(rvu, pcifunc); > pfvf->hw_prio = NPC_DFT_RULE_PRIO; > > + if (npc_priv.kw == NPC_MCAM_KEY_X4) { > + req.kw_type = NPC_MCAM_KEY_X4; > + req.ref_entry = eidx & (npc_priv.bank_depth - 1); > + } else { > + req.kw_type = NPC_MCAM_KEY_X2; > + req.ref_entry = eidx; > + } > + > req.contig = false; > req.ref_prio = NPC_MCAM_HIGHER_PRIO; > - req.ref_entry = eidx; > - req.kw_type = NPC_MCAM_KEY_X2; > req.count = cnt; > req.hdr.pcifunc = pcifunc; > > @@ -4471,11 +4477,18 @@ int npc_cn20k_dft_rules_alloc(struct rvu *rvu, u16 pcifunc) > * as NPC_DFT_RULE_PRIO - 1 (higher hw priority) > */ > req.contig = false; > - req.kw_type = NPC_MCAM_KEY_X2; > req.count = cnt; > req.hdr.pcifunc = pcifunc; > req.ref_prio = NPC_MCAM_LOWER_PRIO; > - req.ref_entry = eidx + 1; > + > + if (npc_priv.kw == NPC_MCAM_KEY_X4) { > + req.kw_type = NPC_MCAM_KEY_X4; > + req.ref_entry = eidx & (npc_priv.bank_depth - 1); > + } else { > + req.kw_type = NPC_MCAM_KEY_X2; > + req.ref_entry = eidx; > + } > + > ret = rvu_mbox_handler_npc_mcam_alloc_entry(rvu, &req, &rsp); > if (ret) { > dev_err(rvu->dev, > diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c > index 6ae9cdcb608b..d20eb0e47d7d 100644 > --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c > +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c > @@ -1671,9 +1671,11 @@ rvu_npc_alloc_entry_for_flow_install(struct rvu *rvu, > { > struct npc_mcam_alloc_entry_req entry_req; > struct npc_mcam_alloc_entry_rsp entry_rsp; > + struct npc_get_pfl_info_rsp rsp = { 0 }; > struct npc_get_num_kws_req kws_req; > struct npc_get_num_kws_rsp kws_rsp; > int off, kw_bits, rc; > + struct msg_req req; > u8 *src, *dst; > > if (!is_cn20k(rvu->pdev)) { > @@ -1697,8 +1699,16 @@ rvu_npc_alloc_entry_for_flow_install(struct rvu *rvu, > kw_bits = kws_rsp.kws * 64; > > *kw_type = NPC_MCAM_KEY_X2; > - if (kw_bits > 256) > + if (kw_bits > 256) { > + rvu_mbox_handler_npc_get_pfl_info(rvu, &req, &rsp); > + if (rsp.kw_type == NPC_MCAM_KEY_X2) { > + dev_err(rvu->dev, > + "Only X2 entries are supported in X2 profile\n"); > + return -EOPNOTSUPP; > + } > + > *kw_type = NPC_MCAM_KEY_X4; > + } > > memset(&entry_req, 0, sizeof(entry_req)); > memset(&entry_rsp, 0, sizeof(entry_rsp)); > diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c > index 38cc539d724d..5dd0591fed99 100644 > --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c > +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c > @@ -37,14 +37,13 @@ static void otx2_clear_ntuple_flow_info(struct otx2_nic *pfvf, struct otx2_flow_ > flow_cfg->max_flows = 0; > } > > -static int otx2_mcam_pfl_info_get(struct otx2_nic *pfvf, bool *is_x2, > - u16 *x4_slots) > +static int otx2_mcam_pfl_info_get(struct otx2_nic *pfvf, u16 *x4_slots, u8 *kw_type) > { > struct npc_get_pfl_info_rsp *rsp; > struct msg_req *req; > static struct { > bool is_set; > - bool is_x2; > + u8 kw_type; > u16 x4_slots; > } pfl_info; > > @@ -53,8 +52,8 @@ static int otx2_mcam_pfl_info_get(struct otx2_nic *pfvf, bool *is_x2, > */ > mutex_lock(&pfvf->mbox.lock); > if (pfl_info.is_set) { > - *is_x2 = pfl_info.is_x2; > *x4_slots = pfl_info.x4_slots; > + *kw_type = pfl_info.kw_type; > mutex_unlock(&pfvf->mbox.lock); > return 0; > } > @@ -79,16 +78,16 @@ static int otx2_mcam_pfl_info_get(struct otx2_nic *pfvf, bool *is_x2, > return -EFAULT; > } > > - *is_x2 = (rsp->kw_type == NPC_MCAM_KEY_X2); > - if (*is_x2) > - *x4_slots = 0; > + pfl_info.kw_type = rsp->kw_type; > + if (rsp->kw_type == NPC_MCAM_KEY_X2) > + pfl_info.x4_slots = 0; > else > - *x4_slots = rsp->x4_slots; > - > - pfl_info.is_x2 = *is_x2; > - pfl_info.x4_slots = *x4_slots; > + pfl_info.x4_slots = rsp->x4_slots; > pfl_info.is_set = true; > > + *x4_slots = pfl_info.x4_slots; > + *kw_type = pfl_info.kw_type; > + > mutex_unlock(&pfvf->mbox.lock); > return 0; > } > @@ -164,6 +163,7 @@ int otx2_alloc_mcam_entries(struct otx2_nic *pfvf, u16 count) > u16 dft_idx = 0, x4_slots = 0; > int ent, allocated = 0, ref; > bool is_x2 = false; > + u8 kw_type = 0; > int rc; > > /* Free current ones and allocate new ones with requested count */ > @@ -182,12 +182,14 @@ int otx2_alloc_mcam_entries(struct otx2_nic *pfvf, u16 count) > } > > if (is_cn20k(pfvf->pdev)) { > - rc = otx2_mcam_pfl_info_get(pfvf, &is_x2, &x4_slots); > + rc = otx2_mcam_pfl_info_get(pfvf, &x4_slots, &kw_type); > if (rc) { > netdev_err(pfvf->netdev, "Error to retrieve profile info\n"); > return rc; > } > > + is_x2 = kw_type == NPC_MCAM_KEY_X2; > + > rc = otx2_get_dft_rl_idx(pfvf, &dft_idx); > if (rc) { > netdev_err(pfvf->netdev, > @@ -289,6 +291,8 @@ int otx2_mcam_entry_init(struct otx2_nic *pfvf) > struct npc_mcam_alloc_entry_rsp *rsp; > int vf_vlan_max_flows, count; > int rc, ref, prio, ent; > + u8 kw_type = 0; > + u16 x4_slots; > u16 dft_idx; > > ref = 0; > @@ -315,6 +319,16 @@ int otx2_mcam_entry_init(struct otx2_nic *pfvf) > if (!flow_cfg->def_ent) > return -ENOMEM; > > + kw_type = NPC_MCAM_KEY_X2; > + if (is_cn20k(pfvf->pdev)) { > + rc = otx2_mcam_pfl_info_get(pfvf, &x4_slots, &kw_type); > + if (rc) { > + netdev_err(pfvf->netdev, > + "Error to get pfl info\n"); > + return rc; > + } > + } > + > mutex_lock(&pfvf->mbox.lock); > > req = otx2_mbox_alloc_msg_npc_mcam_alloc_entry(&pfvf->mbox); > @@ -324,6 +338,10 @@ int otx2_mcam_entry_init(struct otx2_nic *pfvf) > } > > req->kw_type = NPC_MCAM_KEY_X2; > + if (is_cn20k(pfvf->pdev) && kw_type == NPC_MCAM_KEY_X4) { > + req->kw_type = NPC_MCAM_KEY_X4; > + ref &= (x4_slots - 1); > + } > req->contig = false; > req->count = count; > req->ref_prio = prio; > @@ -1174,15 +1192,14 @@ static int otx2_add_flow_msg(struct otx2_nic *pfvf, struct otx2_flow *flow) > #ifdef CONFIG_DCB > int vlan_prio, qidx, pfc_rule = 0; > #endif > + bool modify = false, is_x2; > int err, vf = 0, off, sz; > - bool modify = false; > u8 kw_type = 0; > u8 *src, *dst; > u16 x4_slots; > - bool is_x2; > > if (is_cn20k(pfvf->pdev)) { > - err = otx2_mcam_pfl_info_get(pfvf, &is_x2, &x4_slots); > + err = otx2_mcam_pfl_info_get(pfvf, &x4_slots, &kw_type); > if (err) { > netdev_err(pfvf->netdev, > "Error to retrieve NPC profile info, pcifunc=%#x\n", > @@ -1190,6 +1207,7 @@ static int otx2_add_flow_msg(struct otx2_nic *pfvf, struct otx2_flow *flow) > return -EFAULT; > } > > + is_x2 = kw_type == NPC_MCAM_KEY_X2; > if (!is_x2) { > err = otx2_prepare_flow_request(&flow->flow_spec, > &treq); > -- > 2.43.0 >