Re: [PATCH 3/9] net: mdio: realtek-rtl9300: Add ports to info structure

[Daniel Golle <daniel@makrotopia.org>]

On Tue, May 19, 2026 at 10:14:24PM +0200, Andrew Lunn wrote:
> > > Hi Markus
> > >
> > > It would be good to take a step back and explain the concepts here in
> > > the commit message. An MDIO bus as 32 addresses, as defined by
> > > 802.3. Why do we need the concept of a port when we have addresses?
> > >
> > > Once you explain the concept, we can maybe suggest a better name. Or
> > > throw the whole concept out because it is not needed.
> > 
> > I'm just trying to give the properties in the info structure the right 
> > name that resembles its function. The driver already builds upon
> > the "port" naming.
> > 
> > Where does this come from?
> > 
> > - The hardware has 1-4 SMI busses
> > - Each bus serves up to 32 addresses
> > - A switch has X physical ports
> > - The mdio controller can only be fed with "physical port"
> 
> So in general, the MDIO API uses an address in the range 0-31, as
> defined in C22/C45. I would try to do any sort of mapping of ports to
> MDIO addresses in a layer above MDIO. Maybe that is not possible, i
> only partially remember the discussion about this hardware. But if it
> is going to get more complex, i really would suggest pulling it out
> into a layer above, and let the MDIO driver simply do MDIO.

The problem is that the hardware doesn't let you access the MDIO
busses directly -- you *have to* setup a mapping and then access each
PHY using the mapped port index. Also hardware PHY polling *has* to be
used to configure the MAC as there is no (known) way to directly
configure most of the MACs (but only a small number which is typically
used for SFPs), so setting up the mapping also for that is mandatory
and cannot be avoided.

The driver does it's best to present MDIO busses with the PHYs available
with their actual (ie. as on the hardware) addresses 0-31 towards Linux,
so PHY drivers, packages or even userland tools all work as expected.
But internally it will have to setup this mapping port->(bus, phy), and
then reverse-resolve each (bus, phy)->port.