From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDE5F175A66 for ; Wed, 17 Jun 2026 07:10:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781680219; cv=none; b=uRw7bzaKEGD+nLaTEyNNE8mGfKMMSbJLfo3vu/t6kCk6dBQ9HMDSM3YUFJWZEJYUk8ahe/wxSmqqxj5QGyy1Uf4BUGIMsRn3jViw5OJaHSzwLSh7wNmEiQvn+WXnS0LYjhzPopx5pEwZYeqRk1MaFQcEt+LgU4R+pCQq6dSWCGM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781680219; c=relaxed/simple; bh=IlU/cHfPmwQZZCSeUdQOO1g85Qu5GDL8I+1SJUQCjSI=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=k6gJzosd93Un9WaIEDOR8Rcw1D5uN5MkuJLPFPajmBKl9mxqJFIBo38vBpi547ZhlafOqGrUc8J1aTK2ZA42NhgRNnFxXzya+d5uv2dwFzAUxfVkFyL3ni2AtWZ3NDfguwrscwt44/KzzjdUECsusrdrxAhCceTuRBMdB323Yv8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EwqGOfRW; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EwqGOfRW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 45B251F000E9; Wed, 17 Jun 2026 07:10:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1781680218; bh=pmQvydvRCSP9YajH5ld+F3Yc26Xe0HLF5RsZ7TVJd7E=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=EwqGOfRWtC6kstEhI2fb+S8YM5jN7vXrtjG5NwDLQijHjwA1pi+y9cSljQFwmOWfC VZS86mHf2++UW9WJAgcOEN+KFaodqzputN9g8XhR1jOCQDN3xpPEvtLLGCvfVtiFPl 0a4TPuBO4WH6WRBg1UvYpYXzTQ/yVTDd3/Houc4qH+m/hIYAb8ayrd+f2pTzRXQxLd Egm9zqq100jqaxeUOIxmzScvYHMPWi+KE38MI3ZajURWnZ/SLAffMF/hzijf2HCEgR JEP2Icqa3HqAOXwWk/G+deywp3Vyed6p4PNaWSCSQaY2VUe0ooIB+JuaueJJOzEF0J XrLTlnfOGZrKQ== Date: Wed, 17 Jun 2026 09:10:16 +0200 From: Lorenzo Bianconi To: Wayen Yan Cc: netdev@vger.kernel.org, horms@kernel.org, pabeni@redhat.com, kuba@kernel.org, edumazet@google.com, andrew+netdev@lunn.ch, angelogioacchino.delregno@collabora.com, matthias.bgg@gmail.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: Re: [PATCH net] net: airoha: Fix TX scheduler queue mask loop upper bound Message-ID: References: <178166704952.2212140.11002626760717132754@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="3atRIyxmMYcc7hV5" Content-Disposition: inline In-Reply-To: <178166704952.2212140.11002626760717132754@gmail.com> --3atRIyxmMYcc7hV5 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable > In airoha_qdma_set_chan_tx_sched(), the loop clearing queue mask was > using AIROHA_NUM_TX_RING (32) instead of AIROHA_NUM_QOS_QUEUES (8). >=20 > Each channel has 8 queues, and TXQ_DISABLE_CHAN_QUEUE_MASK(channel, i) > computes BIT(i + (channel * 8)). With i ranging 0..31, this causes: > - channel 0: clears bit 0..31 (all 4 channels) instead of 0..7 > - channel 1: clears bit 8..31 (channels 1-3) instead of 8..15 > - channel 2: clears bit 16..31 (channels 2-3) instead of 16..23 > - channel 3: clears bit 24..31 (channel 3 only) - correct by accident >=20 > While BIT(32+) on arm64 produces 64-bit values truncated to 0 in u32 > mask parameter, the loop still incorrectly clears queues within the > same channel beyond queue 7. >=20 > Fix by using AIROHA_NUM_QOS_QUEUES (8) as the loop upper bound. >=20 > Fixes: ef1ca9271313 ("net: airoha: Add sched HTB offload support") > Signed-off-by: Wayen Yan > --- > drivers/net/ethernet/airoha/airoha_eth.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ether= net/airoha/airoha_eth.c > index 31cdb11cd7..a1eda13400 100644 > --- a/drivers/net/ethernet/airoha/airoha_eth.c > +++ b/drivers/net/ethernet/airoha/airoha_eth.c > @@ -2217,7 +2217,7 @@ static int airoha_qdma_set_chan_tx_sched(struct net= _device *dev, > struct airoha_gdm_port *port =3D netdev_priv(dev); > int i; > =20 > - for (i =3D 0; i < AIROHA_NUM_TX_RING; i++) > + for (i =3D 0; i < AIROHA_NUM_QOS_QUEUES; i++) > airoha_qdma_clear(port->qdma, REG_QUEUE_CLOSE_CFG(channel), > TXQ_DISABLE_CHAN_QUEUE_MASK(channel, i)); Even if the current codebase supports just AIROHA_NUM_QOS_CHANNEL (4), the = hw exposes 32 hw QoS channels (AIROHA_NUM_TX_RING). Here we are just clearing = the configuration, so I guess the current implementation is correct. Regards, Lorenzo > =20 > --=20 > 2.51.0 >=20 >=20 --3atRIyxmMYcc7hV5 Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTquNwa3Txd3rGGn7Y6cBh0uS2trAUCajJIWAAKCRA6cBh0uS2t rCpKAP4rBsCxkrXvSIxF8WbcxiMTBXD2SHgLLgWwzs8jVDSfDwEAqMrHpdsQRrOv LR2RcnPVRhLpqq9eX47Slb8U4831bgE= =uJkH -----END PGP SIGNATURE----- --3atRIyxmMYcc7hV5--