From: "Maciej W. Rozycki" <macro@linux-mips.org>
To: netdev@vger.kernel.org
Subject: [PATCH 2/3] defxx: DEFEA's Burst Holdoff register initialization fix
Date: Thu, 25 Sep 2014 11:06:45 +0100 (BST) [thread overview]
Message-ID: <alpine.LFD.2.11.1409251031170.6148@eddie.linux-mips.org> (raw)
In-Reply-To: <alpine.LFD.2.11.1409242337420.6148@eddie.linux-mips.org>
Use the mask rather than bit number macro to initialize the chip select
control bit for PDQ register space decoding in the Burst Holdoff register.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
---
Another brown paperbag. Dave, please apply.
Maciej
linux-defea-burst-holdoff.patch
Index: linux-20140924-dolch/drivers/net/fddi/defxx.c
===================================================================
--- linux-20140924-dolch.orig/drivers/net/fddi/defxx.c
+++ linux-20140924-dolch/drivers/net/fddi/defxx.c
@@ -748,9 +748,9 @@ static void dfx_bus_init(struct net_devi
*/
val = inb(base_addr + PI_DEFEA_K_BURST_HOLDOFF);
if (dfx_use_mmio)
- val |= PI_BURST_HOLDOFF_V_MEM_MAP;
+ val |= PI_BURST_HOLDOFF_M_MEM_MAP;
else
- val &= ~PI_BURST_HOLDOFF_V_MEM_MAP;
+ val &= ~PI_BURST_HOLDOFF_M_MEM_MAP;
outb(val, base_addr + PI_DEFEA_K_BURST_HOLDOFF);
/* Enable interrupts at EISA bus interface chip (ESIC) */
next prev parent reply other threads:[~2014-09-25 10:29 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-25 10:06 [PATCH 0/3] defxx: DEFEA fixes and updates Maciej W. Rozycki
2014-09-25 10:06 ` [PATCH 1/3] defxx: Correct DEFEA's ESIC port I/O accesses Maciej W. Rozycki
2014-09-25 10:38 ` David Laight
2014-09-25 11:14 ` Maciej W. Rozycki
2014-09-25 10:06 ` Maciej W. Rozycki [this message]
2014-09-25 10:06 ` [PATCH 3/3] defxx: DEFEA's ESIC port I/O decoding cleanup Maciej W. Rozycki
2014-09-28 21:22 ` [PATCH 0/3] defxx: DEFEA fixes and updates David Miller
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