[PATCH] atm: idt77252: Replace mdelay with usleep_range in idt77252_preset

[PATCH] atm: idt77252: Replace mdelay with usleep_range in idt77252_preset

[Jia-Ju Bai]

After checking all possible call chains to idt77252_preset() here,
my tool finds that idt77252_preset() is never called in atomic context,
namely never in an interrupt handler or holding a spinlock.
And idt77252_preset() calls deinit_card, which calls free_irq (can sleep),
so it indicates that idt77252_preset() can call functions which can sleep.
Thus mdelay can be replaced with usleep_range to avoid busy wait.

This is found by a static analysis tool named DCNS written by myself.

Signed-off-by: Jia-Ju Bai <baijiaju1990@gmail.com>
---
 drivers/atm/idt77252.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/atm/idt77252.c b/drivers/atm/idt77252.c
index 0277f36..cea4bf2 100644
--- a/drivers/atm/idt77252.c
+++ b/drivers/atm/idt77252.c
@@ -3563,7 +3563,7 @@ static int idt77252_preset(struct idt77252_dev *card)
 
 	/* Software reset */
 	writel(SAR_CFG_SWRST, SAR_REG_CFG);
-	mdelay(1);
+	usleep_range(500, 1000);
 	writel(0, SAR_REG_CFG);
 
 	IPRINTK("%s: Software resetted.\n", card->name);
-- 
1.7.9.5

Re: [PATCH] atm: idt77252: Replace mdelay with usleep_range in idt77252_preset

[Maciej W. Rozycki]

On Fri, 26 Jan 2018, Jia-Ju Bai wrote:

> diff --git a/drivers/atm/idt77252.c b/drivers/atm/idt77252.c
> index 0277f36..cea4bf2 100644
> --- a/drivers/atm/idt77252.c
> +++ b/drivers/atm/idt77252.c
> @@ -3563,7 +3563,7 @@ static int idt77252_preset(struct idt77252_dev *card)
>  
>  	/* Software reset */
>  	writel(SAR_CFG_SWRST, SAR_REG_CFG);
> -	mdelay(1);
> +	usleep_range(500, 1000);
>  	writel(0, SAR_REG_CFG);
>  
>  	IPRINTK("%s: Software resetted.\n", card->name);

 This is only called from the driver's ->probe method, so it looks to me 
indeed safe to sleep here.  A similar, more extensive clean-up seems due 
for 77252 older brother's driver nicstar.c.

 Out of curiosity I have looked up the SAR manual and it requires the 
SWRST bit to be asserted for at least 2 PCI clock cycles for the reset to 
be valid, so having the lower bound of .5ms still looks completely safe if 
not an overkill to me for real world applications where PCI is driven in 
the MHz clock range.

Reviewed-by: Maciej W. Rozycki <macro@linux-mips.org>

  Maciej