Re: [PATCH v8 net-next 0/9] Switch support

[Ratheesh Kannoth <rkannoth@marvell.com>]

On 2026-08-11 at 14:23:57, Ratheesh Kannoth (rkannoth@marvell.com) wrote:
> Marvell OcteonTX2 switch hardware is capable of accelerating L2, L3, and
> flow. When representors are enabled through devlink, a logical port is
> created in switch hardware for each representor device.
>
> This patch series implements communication from the host OS to the switch
> hardware and vice versa.
>
>                  control plane (FDB / FIB / flow over mailbox)
>     +---------------------------------------------------------------------+
>     |                               HOST OS                               |
>     |                                                                     |
>     | +------------+  +---------------------+  +---------------+          |
>     | | bridge /   |  | PF + notifiers      |  | TC / flower   |          |
>     | | routing    |  | (FDB, FIB, flow)    |  | offload       |          |
>     | +------+-----+  +-----------+---------+  +-------+-------+          |
>     |        ^                     |                      |               |
>     |        | slow path           |                      |               |
>     |        | (unmatched pkts)    v                      v               |
>     | +------+------+       +------+------+        +------+------+        |
>     | | rep-eth0    |       | PF / VF     | <----> | RVU AF      |        |
>     | +------+------+       +-------------+        +------+------+        |
>     |        |                                                |           |
>     | +------+------+                                         |           |
>     | | rep-eth1    |                                         |           |
>     | +-------------+                                         |           |
>     |        | slow path (miss / control to host stack)       |           |
>     +---------------------------------------------------------------------+
>     |      |                                         |                    |
>     |      |              mailbox / PCIe             |                    |
>     |      v                                         v                    |
>     +---------------------------------------------------------------------+
>     |                           SWITCH HARDWARE                           |
>     |                                                                     |
>     |      +---------------------------------------------------+          |
>     |      | L2 tables   | L3 tables   | flow TCAM (HW)        |          |
>     |      +-------+-------------+---------------+-------------+          |
>     |              |       fast path (HW)           |                     |
>     |              v                                v                     |
>     |           lport0  <========================>  lport1                |
>     |             HW forwarding between ports                             |
>     |                                                                     |
>     | slow path (miss): packets raised to host via representors           |
>     +---------------------------------------------------------------------+
>
> When representors are created, corresponding logical ports are created in
> switchdev. Matching traffic is accelerated in switch hardware using
> installed L2, L3, and flow rules. Packets that do not match offloaded
> state, or that require software handling, take the slow path through
> representors and the host networking stack. Control updates from the host
> (FDB, FIB, TC flower) are sent to the AF over mailbox and programmed into
> switch hardware tables.

Will address sashiko issues in v9

pw-bot: changes-requested

>