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Sat, 08 Aug 2026 02:58:58 -0700 (PDT) Received: from localhost ([140.209.217.211]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4995ea2dc4esm123249915e9.13.2026.08.08.02.58.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Aug 2026 02:58:58 -0700 (PDT) Date: Sat, 8 Aug 2026 11:58:54 +0200 From: Jiri Pirko To: Ivan Vecera Cc: netdev@vger.kernel.org, Arkadiusz Kubalewski , Jakub Kicinski , Min Li , Paolo Abeni , Petr Oros , Richard Cochran , Vadim Fedorenko , linux-kernel@vger.kernel.org, Jonathan Corbet , Shuah Khan , linux-doc@vger.kernel.org Subject: Re: [PATCH net-next v3 2/2] dpll: use pin owner's dpll ref for pin-level attribute setting Message-ID: References: <20260807095926.386923-1-ivecera@redhat.com> <20260807095926.386923-3-ivecera@redhat.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260807095926.386923-3-ivecera@redhat.com> Fri, Aug 07, 2026 at 11:59:26AM +0200, ivecera@redhat.com wrote: >Pin-level attributes (frequency, phase adjust, embedded sync, reference >sync) are properties of the pin itself, not of a particular DPLL device. >The get callbacks already use only the pin owner's DPLL reference >(via dpll_pin_own_dpll_ref_first()), but the set callbacks iterate over >all registered DPLL references and invoke the set operation on each one. > >This is redundant because a pin is a single physical entity - setting >its frequency or phase adjust once through the owner's ops is sufficient. >Calling set on every registered DPLL just results in duplicate HW writes >for drivers that share a pin across multiple DPLL devices (e.g. ice >registers each input pin with both the EEC and PPS DPLL, zl3073x >registers input pins with every DPLL channel). > >Simplify dpll_pin_freq_set(), dpll_pin_esync_set(), >dpll_pin_ref_sync_state_set() and dpll_pin_phase_adj_set() to call the >set callback only through the owner's DPLL reference, matching the >existing get-side behavior. This removes the xa_for_each iteration >loops, the now-unnecessary rollback logic, and several local variables. > >The -EOPNOTSUPP validation loop, which checked ops support across all >owner-matching references, is replaced with a direct check on the >single owner reference returned by dpll_pin_own_dpll_ref_first(). > >The documentation in dpll.rst is updated to reflect that pin-level >attributes are set through the pin owner's dpll reference only. > >No existing driver is affected: > - ptp_ocp and mlx5 register each pin with a single DPLL. > - ice registers input pins with two DPLLs (EEC and PPS) using > identical ops and pin_priv; the set callbacks address the HW by > pin index, not by DPLL, so the second call was a no-op. > - zl3073x registers input pins with every DPLL channel; the set > callbacks address HW by pin/ref ID regardless of DPLL. The > ref_sync_set callback was the only one with per-channel behavior, > addressed by the preceding patch. > >Signed-off-by: Ivan Vecera Reviewed-by: Jiri Pirko