From: Frank Li <Frank.li@oss.nxp.com>
To: Srinivas Neeli <srinivas.neeli@amd.com>
Cc: Vinod Koul <vkoul@kernel.org>,
Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>,
Frank Li <Frank.Li@kernel.org>,
Michal Simek <michal.simek@amd.com>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S . Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Suraj Gupta <suraj.gupta2@amd.com>,
Marek Vasut <marex@nabladev.com>,
Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>,
Alex Bereza <alex@bereza.email>,
Folker Schwesinger <dev@folker-schwesinger.de>,
dmaengine@vger.kernel.org, netdev@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, git@amd.com
Subject: Re: [PATCH V6 2/4] dmaengine: xilinx_dma: Move descriptors to done list based on completion bit
Date: Tue, 18 Aug 2026 14:05:46 -0500 [thread overview]
Message-ID: <aoStCsYpjNrmwuAd@SMW015318> (raw)
In-Reply-To: <20260818174151.1608971-3-srinivas.neeli@amd.com>
On Tue, Aug 18, 2026 at 11:11:49PM +0530, Srinivas Neeli wrote:
> In AXI MCDMA, xilinx_dma_complete_descriptor() walks the channel's
> active_list and unconditionally moves every entry to the done_list. The
> MCDMA IOC interrupt handler invokes this function on every
> interrupt-on-completion, but with interrupt coalescing (IRQThreshold > 1)
> an IOC interrupt may fire after only a subset of the queued descriptors
> have actually been processed by the hardware. As a result, descriptors
> whose completion bit is not yet set in the BD status were being reported
> as completed to client drivers.
>
> Add a check for the descriptor completion bit before moving entries from
> the active list to the done list, using the appropriate direction-
> specific status field (s2mm_status for DMA_DEV_TO_MEM, mm2s_status for
> DMA_MEM_TO_DEV).
>
> This mirrors the AXIDMA fix in commit 7bcdaa658102 ("dmaengine:
> xilinx_dma: Freeup active list based on descriptor completion bit").
>
> Fixes: 6ccd692bfb7f ("dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine driver support")
> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
> Signed-off-by: Srinivas Neeli <srinivas.neeli@amd.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> Changes in V6:
> - No change.
>
> Changes in V5:
> - No change.
>
> Changes in V4:
> - Reworded commit message to reference the AXIDMA fix it mirrors
> (commit 7bcdaa658102).
> - Added Reviewed-by: Radhey Shyam Pandey.
>
> Changes in V3:
> - Added Fixes tag.
> - Expanded commit message to explain the interrupt coalescing scenario
> and why the has_sg guard is omitted for MCDMA.
> - Changed local variable from 'bool completed' to 'u32 status' for
> cleaner status field access.
> - Simplified completion check logic.
>
> Changes in V2:
> - No change.
> ---
> drivers/dma/xilinx/xilinx_dma.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
> index 2319101be778..506ce1ec29bc 100644
> --- a/drivers/dma/xilinx/xilinx_dma.c
> +++ b/drivers/dma/xilinx/xilinx_dma.c
> @@ -1784,6 +1784,17 @@ static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan)
> struct xilinx_axidma_tx_segment, node);
> if (!(seg->hw.status & XILINX_DMA_BD_COMP_MASK) && chan->has_sg)
> break;
> + } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) {
> + struct xilinx_aximcdma_tx_segment *seg;
> + u32 status;
> +
> + seg = list_last_entry(&desc->segments,
> + struct xilinx_aximcdma_tx_segment,
> + node);
> + status = (chan->direction == DMA_DEV_TO_MEM) ?
> + seg->hw.s2mm_status : seg->hw.mm2s_status;
> + if (!(status & XILINX_DMA_BD_COMP_MASK))
> + break;
> }
> if (chan->has_sg && chan->xdev->dma_config->dmatype !=
> XDMA_TYPE_VDMA)
> --
> 2.43.0
>
next prev parent reply other threads:[~2026-08-18 19:06 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-18 17:41 [PATCH V6 0/4] dmaengine: xilinx_dma: MCDMA descriptor and metadata handling improvements Srinivas Neeli
2026-08-18 17:41 ` [PATCH V6 1/4] dmaengine: xilinx_dma: Fix MCDMA descriptor fields based on DMA direction Srinivas Neeli
2026-08-18 18:57 ` Frank Li
2026-08-18 17:41 ` [PATCH V6 2/4] dmaengine: xilinx_dma: Move descriptors to done list based on completion bit Srinivas Neeli
2026-08-18 19:05 ` Frank Li [this message]
2026-08-18 17:41 ` [PATCH V6 3/4] net: xilinx: axienet: Derive RX frame length from residue in dmaengine path Srinivas Neeli
2026-08-18 17:41 ` [PATCH V6 4/4] dmaengine: xilinx_dma: Extend metadata handling for AXI DMA and MCDMA Srinivas Neeli
2026-08-18 19:15 ` Frank Li
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