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Wed, 09 Sep 2026 11:47:49 -0700 (PDT) Date: Wed, 9 Sep 2026 20:47:48 +0200 From: Lorenzo Bianconi To: Mohd Ayaan Anwar Cc: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Davis , Andrew Lunn , Heiner Kallweit , Russell King , Richard Cochran , Bjorn Andersson , Konrad Dybcio , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Maxime Chevallier , Maxime Coquelin , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH net-next v2 8/9] net: stmmac: qcom-ethqos: add per-platform NOC clock voting Message-ID: References: <20260908-shikra_ethernet-v2-0-bbe3389d0652@oss.qualcomm.com> <20260908-shikra_ethernet-v2-8-bbe3389d0652@oss.qualcomm.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="slUpn+zr8Skpi/6V" Content-Disposition: inline In-Reply-To: <20260908-shikra_ethernet-v2-8-bbe3389d0652@oss.qualcomm.com> X-Authority-Analysis: v=2.4 cv=YZYodARf c=1 sm=1 tr=0 ts=6aa1a9d7 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=WpTaRW6qxYHRGzLzQsVYzg==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=Jx9YaH9-bZbgU6IgifAA:9 a=CjuIK1q_8ugA:10 a=8sS7P86Wg6PPOb-1CJIA:9 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA5MDIxMCBTYWx0ZWRfX10geybvGoA0R Eov0nMrF2nfJrFrT7EDumGx2r1tzCsqy7AEmoYO7BwK3Hd3WA9ajnpRbul/U0GGnMaJ2rGgt605 XAObLqMJip0UIaNcgfD04paR7N1cIDY= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA5MDIxMCBTYWx0ZWRfX7i+DDI6z4tfo 7hzqMGZGNd3Pb1RyESgFfbMgZupYtgPKauhcV19VT45EF6mylAG4n0CNoeZ/UpOKnajZibuUsuN HP4w0XRAxraWo7LaeJ5zm4dmLeRhLX7uE1wyqYAfy4V/+BI3gTAVuGhLABBxfsbz4KTvXNfJU03 e1eF6wUs3ntzXh1nB4vQQ5oFWGqubaF6oG+5a3VqoYjw1AW1A0QTuAEd6AvbtoKdZs3U5lUxHXg 7XKuE+QhLRIwXsMaZRq+40x8NEv7LcVI2FP3CA1MiYCbcoaiCDfKDC+JxfXF/6QiIM/v2z/qg2f zppJYIPX6FzZv/SOA8RcuwJ3262vxnvHeJYLCIBBiSOLmrCUDjhWda/FVkw2lS7p3tmtMNbrgdV +sVH0zpnuhIcZixUlZujQ23rcsqKyA2yFUTguiB3XzHdunXxcij696BE2L6oYIWUVWkaF5hURxi nb779eW1hO1u9CDVF9g== X-Proofpoint-GUID: ycv7mdX9sj1yGFVGH1te5kygSXy_B8nQ X-Proofpoint-ORIG-GUID: ycv7mdX9sj1yGFVGH1te5kygSXy_B8nQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-08_03,2026-09-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 bulkscore=0 phishscore=0 spamscore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609090210 --slUpn+zr8Skpi/6V Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable > Some SoCs gate the EMAC's path to the System NOC behind dedicated clocks > that must be enabled before the DMA can reach memory. Add > ethqos_noc_clk_cfg and the corresponding fields in the driver-data and > runtime structs so each compatible can declare its own set with per-clock > rates. The clocks are acquired during probe and enabled/disabled > alongside the existing link clock in ethqos_clks_config(). >=20 > No functional change for existing compatibles. This will help us when > we add support for Shikra. >=20 > Signed-off-by: Mohd Ayaan Anwar > --- > .../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 106 +++++++++++++++= ++++++ > 1 file changed, 106 insertions(+) >=20 [...] > static u32 rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset) > @@ -689,15 +703,51 @@ static int ethqos_mac_finish_serdes(struct net_devi= ce *ndev, void *priv, > static int ethqos_clks_config(void *priv, bool enabled) > { > struct qcom_ethqos *ethqos =3D priv; > + unsigned int i; > int ret =3D 0; > =20 > if (enabled) { > + if (ethqos->num_noc_clks) { > + ret =3D dev_pm_opp_set_rate(ðqos->pdev->dev, > + ethqos->noc_clk_rates[0]); assuming the first clock is always an OPP device seems a bit fragile to me. Can we find a way to enforce it? (e.g. have a dedicated clk_bulk_data struct for it). > + if (ret) { > + dev_err(ðqos->pdev->dev, > + "NOC OPP rate set failed: %d\n", ret); > + return ret; > + } > + > + for (i =3D 1; i < ethqos->num_noc_clks; i++) { > + ret =3D clk_set_rate(ethqos->noc_clks[i].clk, > + ethqos->noc_clk_rates[i]); > + if (ret) { > + dev_err(ðqos->pdev->dev, > + "NOC clock rate set failed: %d\n", ret); > + dev_pm_opp_set_rate(ðqos->pdev->dev, 0); > + return ret; > + } > + } > + } > + > ret =3D clk_prepare_enable(ethqos->link_clk); > if (ret) { > dev_err(ðqos->pdev->dev, "link_clk enable failed\n"); > + if (ethqos->num_noc_clks) > + dev_pm_opp_set_rate(ðqos->pdev->dev, 0); > return ret; > } > =20 > + if (ethqos->num_noc_clks) { > + ret =3D clk_bulk_prepare_enable(ethqos->num_noc_clks, > + ethqos->noc_clks); > + if (ret) { > + dev_err(ðqos->pdev->dev, > + "NOC clocks enable failed: %d\n", ret); > + clk_disable_unprepare(ethqos->link_clk); > + dev_pm_opp_set_rate(ðqos->pdev->dev, 0); > + return ret; > + } > + } > + > /* Enable functional clock to prevent DMA reset to timeout due > * to lacking PHY clock after the hardware block has been power > * cycled. The actual configuration will be adjusted once > @@ -706,7 +756,12 @@ static int ethqos_clks_config(void *priv, bool enabl= ed) > qcom_ethqos_set_sgmii_loopback(ethqos, true); > ethqos_set_func_clk_en(ethqos); > } else { > + if (ethqos->num_noc_clks) > + clk_bulk_disable_unprepare(ethqos->num_noc_clks, > + ethqos->noc_clks); > clk_disable_unprepare(ethqos->link_clk); > + if (ethqos->num_noc_clks) > + dev_pm_opp_set_rate(ðqos->pdev->dev, 0); > } > =20 > return ret; > @@ -734,6 +789,51 @@ static void ethqos_ptp_clk_freq_config(struct stmmac= _priv *priv) > netdev_dbg(priv->dev, "PTP rate %lu\n", plat_dat->clk_ptp_rate); > } > =20 > +static void qcom_ethqos_noc_opp_cleanup(void *dev) > +{ > + dev_pm_opp_set_rate(dev, 0); > +} > + > +/* Some SoCs gate NOC access behind dedicated clocks. Acquire them here > + * so ethqos_clks_config() can enable/disable them at runtime. The OPP > + * table is used to propagate the required VDD_CX performance state via > + * dev_pm_opp_set_rate(). > + */ > +static int qcom_ethqos_init_noc_clks(struct qcom_ethqos *ethqos, > + const struct ethqos_emac_driver_data *data) > +{ > + struct device *dev =3D ðqos->pdev->dev; > + unsigned int i; > + int ret; > + > + if (!data->num_noc_clks) > + return 0; > + > + for (i =3D 0; i < data->num_noc_clks; i++) { > + ethqos->noc_clks[i].id =3D data->noc_clk_cfg[i].id; > + ethqos->noc_clk_rates[i] =3D data->noc_clk_cfg[i].rate; > + } > + ethqos->num_noc_clks =3D data->num_noc_clks; > + > + ret =3D devm_clk_bulk_get(dev, ethqos->num_noc_clks, ethqos->noc_clks); > + if (ret) > + return dev_err_probe(dev, ret, "Failed to get NOC clocks\n"); > + > + ret =3D devm_pm_opp_set_clkname(dev, data->noc_clk_cfg[0].id); > + if (ret) > + return dev_err_probe(dev, ret, "Failed to set OPP clock name\n"); > + > + ret =3D devm_pm_opp_of_add_table(dev); > + if (ret) > + return dev_err_probe(dev, ret, "Failed to add OPP table\n"); > + > + ret =3D dev_pm_opp_set_rate(dev, data->noc_clk_cfg[0].rate); > + if (ret) > + return dev_err_probe(dev, ret, "Failed to set initial NOC OPP rate\n"); > + > + return devm_add_action_or_reset(dev, qcom_ethqos_noc_opp_cleanup, dev); > +} > + > static int qcom_ethqos_probe(struct platform_device *pdev) > { > struct device_node *np =3D pdev->dev.of_node; > @@ -795,6 +895,12 @@ static int qcom_ethqos_probe(struct platform_device = *pdev) > ethqos->has_emac_ge_3 =3D data->has_emac_ge_3; > ethqos->needs_sgmii_loopback =3D data->needs_sgmii_loopback; > =20 > + if (data->num_noc_clks) { I guess you can drop this check since it is already done in qcom_ethqos_init_noc_clks(), right? Regards, Lorenzo > + ret =3D qcom_ethqos_init_noc_clks(ethqos, data); > + if (ret) > + return ret; > + } > + > ethqos->link_clk =3D devm_clk_get(dev, data->link_clk_name ?: "rgmii"); > if (IS_ERR(ethqos->link_clk)) > return dev_err_probe(dev, PTR_ERR(ethqos->link_clk), >=20 > --=20 > 2.34.1 >=20 >=20 --slUpn+zr8Skpi/6V Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTquNwa3Txd3rGGn7Y6cBh0uS2trAUCaqGp1AAKCRA6cBh0uS2t rJe5AP412HbG+cRGfi9lkrr+Gg/WmE/XOiGzUoflMRha2mmokAD/RbM96cAfeMgt zWdQxOE79McBOAswltXFCrrAJhxVMgg= =+2DD -----END PGP SIGNATURE----- --slUpn+zr8Skpi/6V--