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[73.183.53.213]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-530ca309989sm100594471cf.4.2026.09.14.06.44.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2026 06:44:22 -0700 (PDT) Date: Mon, 14 Sep 2026 09:44:20 -0400 From: Brian Masney To: AngeloGioacchino Del Regno Cc: Louis-Alexis Eyraud , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Chun-Jie Chen , Philipp Zabel , Edward-JW Yang , Richard Cochran , Chen-Yu Tsai , kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, Conor Dooley , Irving-CH Lin Subject: Re: [PATCH v4 00/24] MT8189: Add support for system and base clock controllers Message-ID: References: <20260729-mt8189-clocks-system-base-v4-0-e356b813a64c@collabora.com> <1f6bdf69-c3fe-4e1d-8ff8-0e36d9f4e063@collabora.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1f6bdf69-c3fe-4e1d-8ff8-0e36d9f4e063@collabora.com> User-Agent: Mutt/2.4.0 (2026-06-19) Hi Angelo, On Fri, Jul 31, 2026 at 12:04:49PM +0200, AngeloGioacchino Del Regno wrote: > On 7/30/26 20:22, Brian Masney wrote: > > Should there be a new MAINTAINERS entry added? There's currently 221 > > files under drivers/clk/mediatek/ and there's currently only one > > mediatek maintainer entry: > > > > MEDIATEK MT6735 CLOCK & RESET DRIVERS. > > > > Is there anyone from mediatek (or elsewhere) that could act as a clk > > subsystem maintainer similar to what the other SoC vendors do? Help with > > reviews, send in pulls, etc? > > > > I may be able to step in, but I have to check if it's feasible, time-wise, on > my side. > > Though, that won't happen until mid-September... because, well, I'm about to go > on holiday (in a few days from now). I'm checking in to see if you would be willing to be clk submaintainer for the MediaTek clk drivers? Brian