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Fri, 12 Sep 2025 10:11:31 +0200 (CEST) Message-ID: Date: Fri, 12 Sep 2025 10:11:31 +0200 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 01/12] dt-bindings: media: Convert MediaTek mt8173-mdp bindings to DT schema To: Ariel D'Alessandro , airlied@gmail.com, amergnat@baylibre.com, andrew+netdev@lunn.ch, andrew-ct.chen@mediatek.com, broonie@kernel.org, chunkuang.hu@kernel.org, conor+dt@kernel.org, davem@davemloft.net, dmitry.torokhov@gmail.com, edumazet@google.com, flora.fu@mediatek.com, heiko@sntech.de, houlong.wei@mediatek.com, jeesw@melfas.com, kernel@collabora.com, krzk+dt@kernel.org, kuba@kernel.org, lgirdwood@gmail.com, linus.walleij@linaro.org, louisalexis.eyraud@collabora.com, luiz.dentz@gmail.com, maarten.lankhorst@linux.intel.com, marcel@holtmann.org, matthias.bgg@gmail.com, mchehab@kernel.org, minghsiu.tsai@mediatek.com, mripard@kernel.org, p.zabel@pengutronix.de, pabeni@redhat.com, robh@kernel.org, sean.wang@kernel.org, simona@ffwll.ch, support.opensource@diasemi.com, tiffany.lin@mediatek.com, tzimmermann@suse.de, yunfei.dong@mediatek.com Cc: devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-bluetooth@vger.kernel.org, linux-gpio@vger.kernel.org, linux-input@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-sound@vger.kernel.org, netdev@vger.kernel.org References: <20250911151001.108744-1-ariel.dalessandro@collabora.com> <20250911151001.108744-2-ariel.dalessandro@collabora.com> From: AngeloGioacchino Del Regno Content-Language: en-US In-Reply-To: <20250911151001.108744-2-ariel.dalessandro@collabora.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Il 11/09/25 17:09, Ariel D'Alessandro ha scritto: > Convert the existing text-based DT bindings for MediaTek MT8173 Media Data > Path to a DT schema. > > Signed-off-by: Ariel D'Alessandro Reviewed-by: AngeloGioacchino Del Regno > --- > .../bindings/media/mediatek,mt8173-mdp.yaml | 169 ++++++++++++++++++ > .../bindings/media/mediatek-mdp.txt | 95 ---------- > 2 files changed, 169 insertions(+), 95 deletions(-) > create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml > delete mode 100644 Documentation/devicetree/bindings/media/mediatek-mdp.txt > > diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml > new file mode 100644 > index 0000000000000..8ca33a733c478 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml > @@ -0,0 +1,169 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/mediatek,mt8173-mdp.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek MT8173 Media Data Path > + > +maintainers: > + - Ariel D'Alessandro > + > +description: > + Media Data Path is used for scaling and color space conversion. > + > +properties: > + compatible: > + oneOf: > + - enum: > + - mediatek,mt8173-mdp-rdma > + - mediatek,mt8173-mdp-rsz > + - mediatek,mt8173-mdp-wdma > + - mediatek,mt8173-mdp-wrot > + - items: > + - const: mediatek,mt8173-mdp-rdma > + - const: mediatek,mt8173-mdp > + > + reg: > + maxItems: 1 > + > + clocks: > + minItems: 1 > + maxItems: 2 > + > + power-domains: > + maxItems: 1 > + > + iommus: > + maxItems: 1 > + > + mediatek,vpu: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + phandle to Mediatek Video Processor Unit for HW Codec encode/decode and > + image processing. > + > +required: > + - compatible > + - reg > + - clocks > + - power-domains > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: mediatek,mt8173-mdp-rdma > + then: > + properties: > + clocks: > + items: > + - description: Main clock > + - description: Mutex clock > + else: > + properties: > + clocks: > + items: > + - description: Main clock > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - mediatek,mt8173-mdp-rdma > + - mediatek,mt8173-mdp-wdma > + - mediatek,mt8173-mdp-wrot > + then: > + required: > + - iommus > + > + - if: > + properties: > + compatible: > + contains: > + const: mediatek,mt8173-mdp > + then: > + required: > + - mediatek,vpu > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + mdp_rdma0: rdma@14001000 { > + compatible = "mediatek,mt8173-mdp-rdma", > + "mediatek,mt8173-mdp"; > + reg = <0 0x14001000 0 0x1000>; > + clocks = <&mmsys CLK_MM_MDP_RDMA0>, > + <&mmsys CLK_MM_MUTEX_32K>; > + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; > + iommus = <&iommu M4U_PORT_MDP_RDMA0>; > + mediatek,vpu = <&vpu>; > + }; > + > + mdp_rdma1: rdma@14002000 { > + compatible = "mediatek,mt8173-mdp-rdma"; > + reg = <0 0x14002000 0 0x1000>; > + clocks = <&mmsys CLK_MM_MDP_RDMA1>, > + <&mmsys CLK_MM_MUTEX_32K>; > + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; > + iommus = <&iommu M4U_PORT_MDP_RDMA1>; > + }; > + > + mdp_rsz0: rsz@14003000 { > + compatible = "mediatek,mt8173-mdp-rsz"; > + reg = <0 0x14003000 0 0x1000>; > + clocks = <&mmsys CLK_MM_MDP_RSZ0>; > + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; > + }; > + > + mdp_rsz1: rsz@14004000 { > + compatible = "mediatek,mt8173-mdp-rsz"; > + reg = <0 0x14004000 0 0x1000>; > + clocks = <&mmsys CLK_MM_MDP_RSZ1>; > + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; > + }; > + > + mdp_rsz2: rsz@14005000 { > + compatible = "mediatek,mt8173-mdp-rsz"; > + reg = <0 0x14005000 0 0x1000>; > + clocks = <&mmsys CLK_MM_MDP_RSZ2>; > + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; > + }; > + > + mdp_wdma0: wdma@14006000 { > + compatible = "mediatek,mt8173-mdp-wdma"; > + reg = <0 0x14006000 0 0x1000>; > + clocks = <&mmsys CLK_MM_MDP_WDMA>; > + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; > + iommus = <&iommu M4U_PORT_MDP_WDMA>; > + }; > + > + mdp_wrot0: wrot@14007000 { > + compatible = "mediatek,mt8173-mdp-wrot"; > + reg = <0 0x14007000 0 0x1000>; > + clocks = <&mmsys CLK_MM_MDP_WROT0>; > + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; > + iommus = <&iommu M4U_PORT_MDP_WROT0>; > + }; > + > + mdp_wrot1: wrot@14008000 { > + compatible = "mediatek,mt8173-mdp-wrot"; > + reg = <0 0x14008000 0 0x1000>; > + clocks = <&mmsys CLK_MM_MDP_WROT1>; > + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; > + iommus = <&iommu M4U_PORT_MDP_WROT1>; > + }; > + }; > + > +...