From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C55AC43381 for ; Sun, 24 Feb 2019 11:42:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 15224206B6 for ; Sun, 24 Feb 2019 11:42:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=amazon.com header.i=@amazon.com header.b="ZssdJMFN" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728185AbfBXLmc (ORCPT ); Sun, 24 Feb 2019 06:42:32 -0500 Received: from smtp-fw-9102.amazon.com ([207.171.184.29]:47287 "EHLO smtp-fw-9102.amazon.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725920AbfBXLmc (ORCPT ); Sun, 24 Feb 2019 06:42:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1551008551; x=1582544551; h=subject:to:cc:references:from:message-id:date: mime-version:in-reply-to:content-transfer-encoding; bh=WlBt2qFKD/UROeojKGvsdssKA1aypBIpohSd+913PKk=; b=ZssdJMFNLZJw6gjAcPtJhPq1KGYjc5qbDabTuQ8gNC9gh2ZvK5B7Imls O1c/ZzW3MC/OV1Sz0yhgmcv1osqsZHtKvvMAQT4+XsRBzgrfLMfY13nAU dhBIBM+k+lgOxwHszxTzzDo+VTOCLBuG82ys5Axb5bZdDb+mkxiTOa3zX 0=; X-IronPort-AV: E=Sophos;i="5.58,407,1544486400"; d="scan'208";a="661390004" Received: from sea3-co-svc-lb6-vlan3.sea.amazon.com (HELO email-inbound-relay-1d-f273de60.us-east-1.amazon.com) ([10.47.22.38]) by smtp-border-fw-out-9102.sea19.amazon.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 24 Feb 2019 11:42:29 +0000 Received: from EX13MTAUEA001.ant.amazon.com (iad55-ws-svc-p15-lb9-vlan3.iad.amazon.com [10.40.159.166]) by email-inbound-relay-1d-f273de60.us-east-1.amazon.com (8.14.7/8.14.7) with ESMTP id x1OBgQqn033397 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=FAIL); Sun, 24 Feb 2019 11:42:27 GMT Received: from EX13D19EUB003.ant.amazon.com (10.43.166.69) by EX13MTAUEA001.ant.amazon.com (10.43.61.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sun, 24 Feb 2019 11:42:26 +0000 Received: from [10.218.62.29] (10.43.160.211) by EX13D19EUB003.ant.amazon.com (10.43.166.69) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sun, 24 Feb 2019 11:42:21 +0000 Subject: Re: [RFC v1 08/19] RDMA/irdma: Add privileged UDA queue implementation To: Shiraz Saleem , , , CC: , , , References: <20190215171107.6464-1-shiraz.saleem@intel.com> <20190215171107.6464-9-shiraz.saleem@intel.com> From: Gal Pressman Message-ID: Date: Sun, 24 Feb 2019 13:42:17 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.5.1 MIME-Version: 1.0 In-Reply-To: <20190215171107.6464-9-shiraz.saleem@intel.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.43.160.211] X-ClientProxiedBy: EX13D01UWA004.ant.amazon.com (10.43.160.99) To EX13D19EUB003.ant.amazon.com (10.43.166.69) Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On 15-Feb-19 19:10, Shiraz Saleem wrote: > +/** > + * irdma_puda_poll_info - poll cq for completion > + * @cq: cq for poll > + * @info: info return for successful completion > + */ > +static enum irdma_status_code > +irdma_puda_poll_info(struct irdma_sc_cq *cq, struct irdma_puda_cmpl_info *info) > +{ > + struct irdma_cq_uk *cq_uk = &cq->cq_uk; > + u64 qword0, qword2, qword3, qword6; > + __le64 *cqe; > + __le64 *ext_cqe = NULL; > + u64 qword7 = 0; > + u64 comp_ctx; > + bool valid_bit; > + bool ext_valid = 0; > + u32 major_err, minor_err; > + u32 peek_head; > + bool error; > + u8 polarity; > + > + cqe = IRDMA_GET_CURRENT_CQ_ELEM(&cq->cq_uk); > + get_64bit_val(cqe, 24, &qword3); > + valid_bit = (bool)RS_64(qword3, IRDMA_CQ_VALID); > + if (valid_bit != cq_uk->polarity) > + return IRDMA_ERR_Q_EMPTY; > + > + if (cq->dev->hw_attrs.hw_rev > IRDMA_GEN_1) > + ext_valid = (bool)RS_64(qword3, IRDMA_CQ_EXTCQE); > + > + if (ext_valid) { > + enum irdma_status_code ret = 0; > + > + peek_head = (cq_uk->cq_ring.head + 1) % cq_uk->cq_ring.size; > + ext_cqe = cq_uk->cq_base[peek_head].buf; > + get_64bit_val(ext_cqe, 24, &qword7); > + polarity = (u8)RS_64(qword7, IRDMA_CQ_VALID); > + if (!peek_head) > + polarity ^= 1; > + if (polarity != cq_uk->polarity) > + return IRDMA_ERR_Q_EMPTY; > + > + IRDMA_RING_MOVE_HEAD(cq_uk->cq_ring, ret); Should you check for 'ret' value here? It was initialized to 0 and overriden here but I can't see any actual use for it. > + if (IRDMA_RING_CURRENT_HEAD(cq_uk->cq_ring) == 0) > + cq_uk->polarity = !cq_uk->polarity; > + /* update cq tail in cq shadow memory also */ > + IRDMA_RING_MOVE_TAIL(cq_uk->cq_ring); > + } > + > + irdma_debug_buf(cq->dev, IRDMA_DEBUG_PUDA, "PUDA CQE", cqe, 32); > + if (ext_valid) > + irdma_debug_buf(cq->dev, IRDMA_DEBUG_PUDA, "PUDA EXT-CQE", > + ext_cqe, 32); > + > + error = (bool)RS_64(qword3, IRDMA_CQ_ERROR); > + if (error) { > + irdma_debug(cq->dev, IRDMA_DEBUG_PUDA, "receive error\n"); > + major_err = (u32)(RS_64(qword3, IRDMA_CQ_MAJERR)); > + minor_err = (u32)(RS_64(qword3, IRDMA_CQ_MINERR)); > + info->compl_error = major_err << 16 | minor_err; > + return IRDMA_ERR_CQ_COMPL_ERROR; > + } > + > + get_64bit_val(cqe, 0, &qword0); > + get_64bit_val(cqe, 16, &qword2); > + > + info->q_type = (u8)RS_64(qword3, IRDMA_CQ_SQ); > + info->qp_id = (u32)RS_64(qword2, IRDMACQ_QPID); > + if (cq->dev->hw_attrs.hw_rev > IRDMA_GEN_1) > + info->ipv4 = (bool)RS_64(qword3, IRDMACQ_IPV4); > + > + get_64bit_val(cqe, 8, &comp_ctx); > + info->qp = (struct irdma_qp_uk *)(unsigned long)comp_ctx; > + info->wqe_idx = (u32)RS_64(qword3, IRDMA_CQ_WQEIDX); > + > + if (info->q_type == IRDMA_CQE_QTYPE_RQ) { > + if (ext_valid) { > + info->vlan_valid = (bool)RS_64(qword7, IRDMA_CQ_UDVLANVALID); > + if (info->vlan_valid) { > + get_64bit_val(ext_cqe, 16, &qword6); > + info->vlan = (u16)RS_64(qword6, IRDMA_CQ_UDVLAN); > + } > + info->smac_valid = (bool)RS_64(qword7, IRDMA_CQ_UDSMACVALID); > + if (info->smac_valid) { > + get_64bit_val(ext_cqe, 16, &qword6); > + info->smac[0] = (u8)((qword6 >> 40) & 0xFF); > + info->smac[1] = (u8)((qword6 >> 32) & 0xFF); > + info->smac[2] = (u8)((qword6 >> 24) & 0xFF); > + info->smac[3] = (u8)((qword6 >> 16) & 0xFF); > + info->smac[4] = (u8)((qword6 >> 8) & 0xFF); > + info->smac[5] = (u8)(qword6 & 0xFF); > + } > + } > + > + if (cq->dev->hw_attrs.hw_rev == IRDMA_GEN_1) { > + info->vlan_valid = (bool)RS_64(qword3, IRDMA_VLAN_TAG_VALID); > + info->l4proto = (u8)RS_64(qword2, IRDMA_UDA_L4PROTO); > + info->l3proto = (u8)RS_64(qword2, IRDMA_UDA_L3PROTO); > + } > + > + info->payload_len = (u32)RS_64(qword0, IRDMACQ_PAYLDLEN); > + } > + > + return 0; > +}