[RFC Patch net-next 00/10] net: dsa: microchip: add support for phylink mac config and link up

[RFC Patch net-next 00/10] net: dsa: microchip: add support for phylink mac config and link up

[Arun Ramadoss]

This patch series add common phylink mac config and link up support for the ksz
series switches. At present, ksz8795 and ksz9477 doesn't implement the phylink
mac config and link up. It configures the mac interface in the port setup hook.
ksz8830 series switch does not mac link configuration. For lan937x switches, in
the part support patch series has support only for MII and RMII configuration.
Some group of switches have some register address and bit fields common and
others are different. So, this patch aims to have common phylink implementation
which configures the register based on the chip id.

Arun Ramadoss (10):
  net: dsa: microchip: lan937x: read rgmii delay from device tree
  net: dsa: microchip: add common gigabit set and get function
  net: dsa: microchip: add common 100/10Mbps selection function
  net: dsa: microchip: add common duplex and flow control function
  net: dsa: microchip: add support for common phylink mac link up
  net: dsa: microchip: lan937x: add support for configuing xMII register
  net: dsa: microchip: apply rgmii tx and rx delay in phylink mac config
  net: dsa: microchip: ksz9477: use common xmii function
  net: dsa: microchip: ksz8795: use common xmii function
  net: dsa: microchip: add support for phylink mac config

 drivers/net/dsa/microchip/ksz8795.c      |  40 ---
 drivers/net/dsa/microchip/ksz8795_reg.h  |   8 -
 drivers/net/dsa/microchip/ksz9477.c      | 183 +-------------
 drivers/net/dsa/microchip/ksz9477_reg.h  |  24 --
 drivers/net/dsa/microchip/ksz_common.c   | 305 ++++++++++++++++++++++-
 drivers/net/dsa/microchip/ksz_common.h   |  41 +++
 drivers/net/dsa/microchip/lan937x.h      |   4 -
 drivers/net/dsa/microchip/lan937x_main.c | 131 ++++------
 drivers/net/dsa/microchip/lan937x_reg.h  |  32 +--
 9 files changed, 419 insertions(+), 349 deletions(-)


base-commit: 5022e221c98a609e0e5b0a73852c7e3d32f1c545
-- 
2.36.1

[RFC Patch net-next 01/10] net: dsa: microchip: lan937x: read rgmii delay from device tree

[Arun Ramadoss]

This patch read the rgmii tx and rx delay from device tree and stored it
in the ksz_port.

Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
---
 drivers/net/dsa/microchip/ksz_common.c | 16 ++++++++++++++++
 drivers/net/dsa/microchip/ksz_common.h |  2 ++
 2 files changed, 18 insertions(+)

diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index 28d7cb2ce98f..4bc6277b4361 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -1499,6 +1499,7 @@ int ksz_switch_register(struct ksz_device *dev)
 	struct device_node *port, *ports;
 	phy_interface_t interface;
 	unsigned int port_num;
+	u32 *value;
 	int ret;
 	int i;
 
@@ -1589,6 +1590,21 @@ int ksz_switch_register(struct ksz_device *dev)
 				}
 				of_get_phy_mode(port,
 						&dev->ports[port_num].interface);
+
+				if (!dev->info->supports_rgmii[port_num])
+					continue;
+
+				value = &dev->ports[port_num].rgmii_rx_val;
+				if (of_property_read_u32(port,
+							 "rx-internal-delay-ps",
+							 value))
+					*value = 0;
+
+				value = &dev->ports[port_num].rgmii_tx_val;
+				if (of_property_read_u32(port,
+							 "tx-internal-delay-ps",
+							 value))
+					*value = 0;
 			}
 		dev->synclko_125 = of_property_read_bool(dev->dev->of_node,
 							 "microchip,synclko-125");
diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
index d5dddb7ec045..41fe6388af9e 100644
--- a/drivers/net/dsa/microchip/ksz_common.h
+++ b/drivers/net/dsa/microchip/ksz_common.h
@@ -77,6 +77,8 @@ struct ksz_port {
 	struct ksz_port_mib mib;
 	phy_interface_t interface;
 	u16 max_frame;
+	u32 rgmii_tx_val;
+	u32 rgmii_rx_val;
 };
 
 struct ksz_device {
-- 
2.36.1

Re: [RFC Patch net-next 01/10] net: dsa: microchip: lan937x: read rgmii delay from device tree

[Vladimir Oltean]

On Tue, Jul 12, 2022 at 09:32:59PM +0530, Arun Ramadoss wrote:
> This patch read the rgmii tx and rx delay from device tree and stored it
> in the ksz_port.
> 
> Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
> ---

I think this patch should be squashed into the change that actually uses
the parsed values.

>  drivers/net/dsa/microchip/ksz_common.c | 16 ++++++++++++++++
>  drivers/net/dsa/microchip/ksz_common.h |  2 ++
>  2 files changed, 18 insertions(+)
> 
> diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
> index 28d7cb2ce98f..4bc6277b4361 100644
> --- a/drivers/net/dsa/microchip/ksz_common.c
> +++ b/drivers/net/dsa/microchip/ksz_common.c
> @@ -1499,6 +1499,7 @@ int ksz_switch_register(struct ksz_device *dev)
>  	struct device_node *port, *ports;
>  	phy_interface_t interface;
>  	unsigned int port_num;
> +	u32 *value;
>  	int ret;
>  	int i;
>  
> @@ -1589,6 +1590,21 @@ int ksz_switch_register(struct ksz_device *dev)
>  				}
>  				of_get_phy_mode(port,
>  						&dev->ports[port_num].interface);
> +
> +				if (!dev->info->supports_rgmii[port_num])
> +					continue;
> +
> +				value = &dev->ports[port_num].rgmii_rx_val;
> +				if (of_property_read_u32(port,
> +							 "rx-internal-delay-ps",
> +							 value))
> +					*value = 0;
> +
> +				value = &dev->ports[port_num].rgmii_tx_val;
> +				if (of_property_read_u32(port,
> +							 "tx-internal-delay-ps",
> +							 value))
> +					*value = 0;
>  			}
>  		dev->synclko_125 = of_property_read_bool(dev->dev->of_node,
>  							 "microchip,synclko-125");
> diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
> index d5dddb7ec045..41fe6388af9e 100644
> --- a/drivers/net/dsa/microchip/ksz_common.h
> +++ b/drivers/net/dsa/microchip/ksz_common.h
> @@ -77,6 +77,8 @@ struct ksz_port {
>  	struct ksz_port_mib mib;
>  	phy_interface_t interface;
>  	u16 max_frame;
> +	u32 rgmii_tx_val;
> +	u32 rgmii_rx_val;
>  };
>  
>  struct ksz_device {
> -- 
> 2.36.1
> 

Re: [RFC Patch net-next 01/10] net: dsa: microchip: lan937x: read rgmii delay from device tree

[Arun.Ramadoss]

On Tue, 2022-07-19 at 13:28 +0300, Vladimir Oltean wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> 
> On Tue, Jul 12, 2022 at 09:32:59PM +0530, Arun Ramadoss wrote:
> > This patch read the rgmii tx and rx delay from device tree and
> > stored it
> > in the ksz_port.
> > 
> > Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
> > ---
> 
> I think this patch should be squashed into the change that actually
> uses
> the parsed values.

Ok, I will Squash this patch.

> 
> >  drivers/net/dsa/microchip/ksz_common.c | 16 ++++++++++++++++
> >  drivers/net/dsa/microchip/ksz_common.h |  2 ++
> >  2 files changed, 18 insertions(+)
> > 
> > diff --git a/drivers/net/dsa/microchip/ksz_common.c
> > b/drivers/net/dsa/microchip/ksz_common.c
> > index 28d7cb2ce98f..4bc6277b4361 100644
> > --- a/drivers/net/dsa/microchip/ksz_common.c
> > +++ b/drivers/net/dsa/microchip/ksz_common.c
> > @@ -1499,6 +1499,7 @@ int ksz_switch_register(struct ksz_device
> > *dev)
> >       struct device_node *port, *ports;
> >       phy_interface_t interface;
> >       unsigned int port_num;
> > +     u32 *value;
> >       int ret;
> >       int i;
> > 
> > @@ -1589,6 +1590,21 @@ int ksz_switch_register(struct ksz_device
> > *dev)
> >                               }
> >                               of_get_phy_mode(port,
> >                                               &dev-
> > >ports[port_num].interface);
> > +
> > +                             if (!dev->info-
> > >supports_rgmii[port_num])
> > +                                     continue;
> > +
> > +                             value = &dev-
> > >ports[port_num].rgmii_rx_val;
> > +                             if (of_property_read_u32(port,
> > +                                                      "rx-
> > internal-delay-ps",
> > +                                                      value))
> > +                                     *value = 0;
> > +
> > +                             value = &dev-
> > >ports[port_num].rgmii_tx_val;
> > +                             if (of_property_read_u32(port,
> > +                                                      "tx-
> > internal-delay-ps",
> > +                                                      value))
> > +                                     *value = 0;
> >                       }
> >               dev->synclko_125 = of_property_read_bool(dev->dev-
> > >of_node,
> >                                                        "microchip,s
> > ynclko-125");
> > diff --git a/drivers/net/dsa/microchip/ksz_common.h
> > b/drivers/net/dsa/microchip/ksz_common.h
> > index d5dddb7ec045..41fe6388af9e 100644
> > --- a/drivers/net/dsa/microchip/ksz_common.h
> > +++ b/drivers/net/dsa/microchip/ksz_common.h
> > @@ -77,6 +77,8 @@ struct ksz_port {
> >       struct ksz_port_mib mib;
> >       phy_interface_t interface;
> >       u16 max_frame;
> > +     u32 rgmii_tx_val;
> > +     u32 rgmii_rx_val;
> >  };
> > 
> >  struct ksz_device {
> > --
> > 2.36.1
> > 

[RFC Patch net-next 02/10] net: dsa: microchip: add common gigabit set and get function

[Arun Ramadoss]

This patch add helper function for setting and getting the gigabit
enable for the ksz series switch. KSZ8795 switch has different register
address compared to all other ksz switches. KSZ8795 series uses the Port
5 Interface control 6 Bit 6 for configuring the 1Gbps or 100/10Mbps
speed selection. All other switches uses the xMII control 1 0xN301
register Bit6 for gigabit.
Further, for KSZ8795 & KSZ9893 switches if bit 1 then 1Gbps is chosen
and if bit 0 then 100/10Mbps is chosen. It is other way around for
other switches bit 0 is for 1Gbps. So, this patch implements the common
function for configuring the gigabit set and get capability.

Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
---
 drivers/net/dsa/microchip/ksz9477.c      | 36 ++-----------
 drivers/net/dsa/microchip/ksz9477_reg.h  |  4 --
 drivers/net/dsa/microchip/ksz_common.c   | 66 ++++++++++++++++++++++++
 drivers/net/dsa/microchip/ksz_common.h   | 12 +++++
 drivers/net/dsa/microchip/lan937x_main.c | 16 ++----
 drivers/net/dsa/microchip/lan937x_reg.h  |  1 -
 6 files changed, 87 insertions(+), 48 deletions(-)

diff --git a/drivers/net/dsa/microchip/ksz9477.c b/drivers/net/dsa/microchip/ksz9477.c
index 6453642fa14c..cfa7ddf60718 100644
--- a/drivers/net/dsa/microchip/ksz9477.c
+++ b/drivers/net/dsa/microchip/ksz9477.c
@@ -866,32 +866,6 @@ void ksz9477_port_mirror_del(struct ksz_device *dev, int port,
 			     PORT_MIRROR_SNIFFER, false);
 }
 
-static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data)
-{
-	bool gbit;
-
-	if (dev->features & NEW_XMII)
-		gbit = !(data & PORT_MII_NOT_1GBIT);
-	else
-		gbit = !!(data & PORT_MII_1000MBIT_S1);
-	return gbit;
-}
-
-static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data)
-{
-	if (dev->features & NEW_XMII) {
-		if (gbit)
-			*data &= ~PORT_MII_NOT_1GBIT;
-		else
-			*data |= PORT_MII_NOT_1GBIT;
-	} else {
-		if (gbit)
-			*data |= PORT_MII_1000MBIT_S1;
-		else
-			*data &= ~PORT_MII_1000MBIT_S1;
-	}
-}
-
 static int ksz9477_get_xmii(struct ksz_device *dev, u8 data)
 {
 	int mode;
@@ -977,7 +951,7 @@ static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port)
 	if (port < dev->phy_port_cnt)
 		return PHY_INTERFACE_MODE_NA;
 	ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
-	gbit = ksz9477_get_gbit(dev, data8);
+	gbit = ksz_get_gbit(dev, port);
 	mode = ksz9477_get_xmii(dev, data8);
 	switch (mode) {
 	case 2:
@@ -1122,22 +1096,22 @@ void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
 		switch (p->interface) {
 		case PHY_INTERFACE_MODE_MII:
 			ksz9477_set_xmii(dev, 0, &data8);
-			ksz9477_set_gbit(dev, false, &data8);
+			ksz_set_gbit(dev, port, false);
 			p->phydev.speed = SPEED_100;
 			break;
 		case PHY_INTERFACE_MODE_RMII:
 			ksz9477_set_xmii(dev, 1, &data8);
-			ksz9477_set_gbit(dev, false, &data8);
+			ksz_set_gbit(dev, port, false);
 			p->phydev.speed = SPEED_100;
 			break;
 		case PHY_INTERFACE_MODE_GMII:
 			ksz9477_set_xmii(dev, 2, &data8);
-			ksz9477_set_gbit(dev, true, &data8);
+			ksz_set_gbit(dev, port, true);
 			p->phydev.speed = SPEED_1000;
 			break;
 		default:
 			ksz9477_set_xmii(dev, 3, &data8);
-			ksz9477_set_gbit(dev, true, &data8);
+			ksz_set_gbit(dev, port, true);
 			data8 &= ~PORT_RGMII_ID_IG_ENABLE;
 			data8 &= ~PORT_RGMII_ID_EG_ENABLE;
 			if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
diff --git a/drivers/net/dsa/microchip/ksz9477_reg.h b/drivers/net/dsa/microchip/ksz9477_reg.h
index d0cce4ca3cf9..f23ed4809e47 100644
--- a/drivers/net/dsa/microchip/ksz9477_reg.h
+++ b/drivers/net/dsa/microchip/ksz9477_reg.h
@@ -1185,10 +1185,6 @@
 #define REG_PORT_XMII_CTRL_1		0x0301
 
 #define PORT_RMII_CLK_SEL		BIT(7)
-/* S1 */
-#define PORT_MII_1000MBIT_S1		BIT(6)
-/* S2 */
-#define PORT_MII_NOT_1GBIT		BIT(6)
 #define PORT_MII_SEL_EDGE		BIT(5)
 #define PORT_RGMII_ID_IG_ENABLE		BIT(4)
 #define PORT_RGMII_ID_EG_ENABLE		BIT(3)
diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index 4bc6277b4361..5ebcd87fc531 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -256,6 +256,7 @@ static const u16 ksz8795_regs[] = {
 	[S_START_CTRL]			= 0x01,
 	[S_BROADCAST_CTRL]		= 0x06,
 	[S_MULTICAST_CTRL]		= 0x04,
+	[P_XMII_CTRL_1]			= 0x56,
 };
 
 static const u32 ksz8795_masks[] = {
@@ -280,6 +281,11 @@ static const u32 ksz8795_masks[] = {
 	[DYNAMIC_MAC_TABLE_TIMESTAMP]	= GENMASK(28, 27),
 };
 
+static const u8 ksz8795_values[] = {
+	[P_MII_1GBIT]			= 1,
+	[P_MII_NOT_1GBIT]		= 0,
+};
+
 static const u8 ksz8795_shifts[] = {
 	[VLAN_TABLE_MEMBERSHIP_S]	= 7,
 	[VLAN_TABLE]			= 16,
@@ -350,6 +356,7 @@ static const u16 ksz9477_regs[] = {
 	[S_START_CTRL]			= 0x0300,
 	[S_BROADCAST_CTRL]		= 0x0332,
 	[S_MULTICAST_CTRL]		= 0x0331,
+	[P_XMII_CTRL_1]			= 0x0301,
 };
 
 static const u32 ksz9477_masks[] = {
@@ -361,6 +368,16 @@ static const u8 ksz9477_shifts[] = {
 	[ALU_STAT_INDEX]		= 16,
 };
 
+static const u8 ksz9477_values[] = {
+	[P_MII_1GBIT]			= 0,
+	[P_MII_NOT_1GBIT]		= 1,
+};
+
+static const u8 ksz9893_values[] = {
+	[P_MII_1GBIT]			= 1,
+	[P_MII_NOT_1GBIT]		= 0,
+};
+
 static const u32 lan937x_masks[] = {
 	[ALU_STAT_WRITE]		= 1,
 	[ALU_STAT_READ]			= 2,
@@ -387,6 +404,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
 		.regs = ksz8795_regs,
 		.masks = ksz8795_masks,
 		.shifts = ksz8795_shifts,
+		.bitval = ksz8795_values,
 		.supports_mii = {false, false, false, false, true},
 		.supports_rmii = {false, false, false, false, true},
 		.supports_rgmii = {false, false, false, false, true},
@@ -423,6 +441,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
 		.regs = ksz8795_regs,
 		.masks = ksz8795_masks,
 		.shifts = ksz8795_shifts,
+		.bitval = ksz8795_values,
 		.supports_mii = {false, false, false, false, true},
 		.supports_rmii = {false, false, false, false, true},
 		.supports_rgmii = {false, false, false, false, true},
@@ -445,6 +464,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
 		.regs = ksz8795_regs,
 		.masks = ksz8795_masks,
 		.shifts = ksz8795_shifts,
+		.bitval = ksz8795_values,
 		.supports_mii = {false, false, false, false, true},
 		.supports_rmii = {false, false, false, false, true},
 		.supports_rgmii = {false, false, false, false, true},
@@ -487,6 +507,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
 		.regs = ksz9477_regs,
 		.masks = ksz9477_masks,
 		.shifts = ksz9477_shifts,
+		.bitval = ksz9477_values,
 		.supports_mii	= {false, false, false, false,
 				   false, true, false},
 		.supports_rmii	= {false, false, false, false,
@@ -513,6 +534,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
 		.regs = ksz9477_regs,
 		.masks = ksz9477_masks,
 		.shifts = ksz9477_shifts,
+		.bitval = ksz9477_values,
 		.supports_mii	= {false, false, false, false,
 				   false, true, true},
 		.supports_rmii	= {false, false, false, false,
@@ -538,6 +560,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
 		.regs = ksz9477_regs,
 		.masks = ksz9477_masks,
 		.shifts = ksz9477_shifts,
+		.bitval = ksz9893_values,
 		.supports_mii = {false, false, true},
 		.supports_rmii = {false, false, true},
 		.supports_rgmii = {false, false, true},
@@ -560,6 +583,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
 		.regs = ksz9477_regs,
 		.masks = ksz9477_masks,
 		.shifts = ksz9477_shifts,
+		.bitval = ksz9477_values,
 		.supports_mii	= {false, false, false, false,
 				   false, true, true},
 		.supports_rmii	= {false, false, false, false,
@@ -585,6 +609,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
 		.regs = ksz9477_regs,
 		.masks = lan937x_masks,
 		.shifts = lan937x_shifts,
+		.bitval = ksz9477_values,
 		.supports_mii = {false, false, false, false, true},
 		.supports_rmii = {false, false, false, false, true},
 		.supports_rgmii = {false, false, false, false, true},
@@ -606,6 +631,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
 		.regs = ksz9477_regs,
 		.masks = lan937x_masks,
 		.shifts = lan937x_shifts,
+		.bitval = ksz9477_values,
 		.supports_mii = {false, false, false, false, true, true},
 		.supports_rmii = {false, false, false, false, true, true},
 		.supports_rgmii = {false, false, false, false, true, true},
@@ -627,6 +653,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
 		.regs = ksz9477_regs,
 		.masks = lan937x_masks,
 		.shifts = lan937x_shifts,
+		.bitval = ksz9477_values,
 		.supports_mii	= {false, false, false, false,
 				   true, true, false, false},
 		.supports_rmii	= {false, false, false, false,
@@ -652,6 +679,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
 		.regs = ksz9477_regs,
 		.masks = lan937x_masks,
 		.shifts = lan937x_shifts,
+		.bitval = ksz9477_values,
 		.supports_mii	= {false, false, false, false,
 				   true, true, false, false},
 		.supports_rmii	= {false, false, false, false,
@@ -677,6 +705,7 @@ const struct ksz_chip_data ksz_switch_chips[] = {
 		.regs = ksz9477_regs,
 		.masks = lan937x_masks,
 		.shifts = lan937x_shifts,
+		.bitval = ksz9477_values,
 		.supports_mii	= {false, false, false, false,
 				   true, true, false, false},
 		.supports_rmii	= {false, false, false, false,
@@ -1352,6 +1381,43 @@ static void ksz_phylink_mac_config(struct dsa_switch *ds, int port,
 		dev->dev_ops->phylink_mac_config(dev, port, mode, state);
 }
 
+bool ksz_get_gbit(struct ksz_device *dev, int port)
+{
+	const u8 *bitval = dev->info->bitval;
+	const u16 *regs = dev->info->regs;
+	bool gbit = false;
+	u8 data8;
+	bool val;
+
+	ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
+
+	val = FIELD_GET(P_MII_1GBIT_M, data8);
+
+	if (val == bitval[P_MII_1GBIT])
+		gbit = true;
+
+	return gbit;
+}
+
+void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
+{
+	const u8 *bitval = dev->info->bitval;
+	const u16 *regs = dev->info->regs;
+	u8 data8;
+
+	ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
+
+	data8 &= ~P_MII_1GBIT_M;
+
+	if (gbit)
+		data8 |= FIELD_PREP(P_MII_1GBIT_M, bitval[P_MII_1GBIT]);
+	else
+		data8 |= FIELD_PREP(P_MII_1GBIT_M, bitval[P_MII_NOT_1GBIT]);
+
+	/* Write the updated value */
+	ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
+}
+
 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,
 				    unsigned int mode,
 				    phy_interface_t interface,
diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
index 41fe6388af9e..a76dfef6309c 100644
--- a/drivers/net/dsa/microchip/ksz_common.h
+++ b/drivers/net/dsa/microchip/ksz_common.h
@@ -51,6 +51,7 @@ struct ksz_chip_data {
 	const u16 *regs;
 	const u32 *masks;
 	const u8 *shifts;
+	const u8 *bitval;
 	int stp_ctrl_reg;
 	int broadcast_ctrl_reg;
 	int multicast_ctrl_reg;
@@ -171,6 +172,7 @@ enum ksz_regs {
 	S_START_CTRL,
 	S_BROADCAST_CTRL,
 	S_MULTICAST_CTRL,
+	P_XMII_CTRL_1,
 };
 
 enum ksz_masks {
@@ -210,6 +212,11 @@ enum ksz_shifts {
 	ALU_STAT_INDEX,
 };
 
+enum ksz_values {
+	P_MII_1GBIT,
+	P_MII_NOT_1GBIT,
+};
+
 struct alu_struct {
 	/* entry 1 */
 	u8	is_static:1;
@@ -295,6 +302,8 @@ void ksz_switch_remove(struct ksz_device *dev);
 void ksz_init_mib_timer(struct ksz_device *dev);
 void ksz_r_mib_stats64(struct ksz_device *dev, int port);
 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
+bool ksz_get_gbit(struct ksz_device *dev, int port);
+void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit);
 extern const struct ksz_chip_data ksz_switch_chips[];
 
 /* Common register access functions */
@@ -458,6 +467,9 @@ static inline int is_lan937x(struct ksz_device *dev)
 
 #define SW_START			0x01
 
+/* xMII configuration */
+#define P_MII_1GBIT_M			BIT(6)
+
 /* Regmap tables generation */
 #define KSZ_SPI_OP_RD		3
 #define KSZ_SPI_OP_WR		2
diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
index c29d175ca6f7..efca96b02e15 100644
--- a/drivers/net/dsa/microchip/lan937x_main.c
+++ b/drivers/net/dsa/microchip/lan937x_main.c
@@ -312,14 +312,6 @@ int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu)
 	return 0;
 }
 
-static void lan937x_config_gbit(struct ksz_device *dev, bool gbit, u8 *data)
-{
-	if (gbit)
-		*data &= ~PORT_MII_NOT_1GBIT;
-	else
-		*data |= PORT_MII_NOT_1GBIT;
-}
-
 static void lan937x_mac_config(struct ksz_device *dev, int port,
 			       phy_interface_t interface)
 {
@@ -333,11 +325,11 @@ static void lan937x_mac_config(struct ksz_device *dev, int port,
 	/* configure MAC based on interface */
 	switch (interface) {
 	case PHY_INTERFACE_MODE_MII:
-		lan937x_config_gbit(dev, false, &data8);
+		ksz_set_gbit(dev, port, false);
 		data8 |= PORT_MII_SEL;
 		break;
 	case PHY_INTERFACE_MODE_RMII:
-		lan937x_config_gbit(dev, false, &data8);
+		ksz_set_gbit(dev, port, false);
 		data8 |= PORT_RMII_SEL;
 		break;
 	default:
@@ -363,9 +355,9 @@ static void lan937x_config_interface(struct ksz_device *dev, int port,
 			PORT_MII_TX_FLOW_CTRL | PORT_MII_RX_FLOW_CTRL);
 
 	if (speed == SPEED_1000)
-		lan937x_config_gbit(dev, true, &xmii_ctrl1);
+		ksz_set_gbit(dev, port, true);
 	else
-		lan937x_config_gbit(dev, false, &xmii_ctrl1);
+		ksz_set_gbit(dev, port, false);
 
 	if (speed == SPEED_100)
 		xmii_ctrl0 |= PORT_MII_100MBIT;
diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h
index c187d0a3e7fa..747295d34411 100644
--- a/drivers/net/dsa/microchip/lan937x_reg.h
+++ b/drivers/net/dsa/microchip/lan937x_reg.h
@@ -140,7 +140,6 @@
 #define PORT_GRXC_ENABLE		BIT(0)
 
 #define REG_PORT_XMII_CTRL_1		0x0301
-#define PORT_MII_NOT_1GBIT		BIT(6)
 #define PORT_MII_SEL_EDGE		BIT(5)
 #define PORT_RGMII_ID_IG_ENABLE		BIT(4)
 #define PORT_RGMII_ID_EG_ENABLE		BIT(3)
-- 
2.36.1

Re: [RFC Patch net-next 02/10] net: dsa: microchip: add common gigabit set and get function

[Vladimir Oltean]

On Tue, Jul 12, 2022 at 09:33:00PM +0530, Arun Ramadoss wrote:
> This patch add helper function for setting and getting the gigabit
> enable for the ksz series switch. KSZ8795 switch has different register
> address compared to all other ksz switches. KSZ8795 series uses the Port
> 5 Interface control 6 Bit 6 for configuring the 1Gbps or 100/10Mbps
> speed selection. All other switches uses the xMII control 1 0xN301
> register Bit6 for gigabit.
> Further, for KSZ8795 & KSZ9893 switches if bit 1 then 1Gbps is chosen
> and if bit 0 then 100/10Mbps is chosen. It is other way around for
> other switches bit 0 is for 1Gbps. So, this patch implements the common
> function for configuring the gigabit set and get capability.
> 
> Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
> ---

Reviewed-by: Vladimir Oltean <olteanv@gmail.com>

[RFC Patch net-next 03/10] net: dsa: microchip: add common 100/10Mbps selection function

[Arun Ramadoss]

This patch adds the function for configuring the 100/10Mbps speed
selection for the ksz switches. KSZ8795 switch uses Global control 4
register 0x06 bit 4 for choosing 100/10Mpbs. Other switches uses xMII
control 1 0xN300 for it.
For KSZ8795, if the bit is set then 10Mbps is chosen and if bit is
clear then 100Mbps chosen. For all other switches it is other way
around, if the bit is set then 100Mbps is chosen.
So, this patch add the generic function for ksz switch to select the
100/10Mbps speed selection. While configuring, first it disables the
gigabit functionality and then configure the respective speed.

Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
---
 drivers/net/dsa/microchip/ksz9477_reg.h  |  1 -
 drivers/net/dsa/microchip/ksz_common.c   | 29 ++++++++++++++++++++++++
 drivers/net/dsa/microchip/ksz_common.h   |  6 +++++
 drivers/net/dsa/microchip/lan937x_main.c | 14 ++++--------
 drivers/net/dsa/microchip/lan937x_reg.h  |  1 -
 5 files changed, 40 insertions(+), 11 deletions(-)

diff --git a/drivers/net/dsa/microchip/ksz9477_reg.h b/drivers/net/dsa/microchip/ksz9477_reg.h
index f23ed4809e47..2649fdf0bae1 100644
--- a/drivers/net/dsa/microchip/ksz9477_reg.h
+++ b/drivers/net/dsa/microchip/ksz9477_reg.h
@@ -1179,7 +1179,6 @@
 
 #define PORT_SGMII_SEL			BIT(7)
 #define PORT_MII_FULL_DUPLEX		BIT(6)
-#define PORT_MII_100MBIT		BIT(4)
 #define PORT_GRXC_ENABLE		BIT(0)
 
 #define REG_PORT_XMII_CTRL_1		0x0301
diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index 5ebcd87fc531..f41cd2801210 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -256,6 +256,7 @@ static const u16 ksz8795_regs[] = {
 	[S_START_CTRL]			= 0x01,
 	[S_BROADCAST_CTRL]		= 0x06,
 	[S_MULTICAST_CTRL]		= 0x04,
+	[P_XMII_CTRL_0]			= 0x06,
 	[P_XMII_CTRL_1]			= 0x56,
 };
 
@@ -284,6 +285,8 @@ static const u32 ksz8795_masks[] = {
 static const u8 ksz8795_values[] = {
 	[P_MII_1GBIT]			= 1,
 	[P_MII_NOT_1GBIT]		= 0,
+	[P_MII_100MBIT]			= 0,
+	[P_MII_10MBIT]			= 1,
 };
 
 static const u8 ksz8795_shifts[] = {
@@ -356,6 +359,7 @@ static const u16 ksz9477_regs[] = {
 	[S_START_CTRL]			= 0x0300,
 	[S_BROADCAST_CTRL]		= 0x0332,
 	[S_MULTICAST_CTRL]		= 0x0331,
+	[P_XMII_CTRL_0]			= 0x0300,
 	[P_XMII_CTRL_1]			= 0x0301,
 };
 
@@ -371,11 +375,15 @@ static const u8 ksz9477_shifts[] = {
 static const u8 ksz9477_values[] = {
 	[P_MII_1GBIT]			= 0,
 	[P_MII_NOT_1GBIT]		= 1,
+	[P_MII_100MBIT]			= 1,
+	[P_MII_10MBIT]			= 0,
 };
 
 static const u8 ksz9893_values[] = {
 	[P_MII_1GBIT]			= 1,
 	[P_MII_NOT_1GBIT]		= 0,
+	[P_MII_100MBIT]			= 1,
+	[P_MII_10MBIT]			= 0,
 };
 
 static const u32 lan937x_masks[] = {
@@ -1418,6 +1426,27 @@ void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
 	ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
 }
 
+void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
+{
+	const u8 *bitval = dev->info->bitval;
+	const u16 *regs = dev->info->regs;
+	u8 data8;
+
+	ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
+
+	data8 &= ~P_MII_100MBIT_M;
+
+	ksz_set_gbit(dev, port, false);
+
+	if (speed == SPEED_100)
+		data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]);
+	else
+		data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]);
+
+	/* Write the updated value */
+	ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
+}
+
 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,
 				    unsigned int mode,
 				    phy_interface_t interface,
diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
index a76dfef6309c..f1fa6feca559 100644
--- a/drivers/net/dsa/microchip/ksz_common.h
+++ b/drivers/net/dsa/microchip/ksz_common.h
@@ -172,6 +172,7 @@ enum ksz_regs {
 	S_START_CTRL,
 	S_BROADCAST_CTRL,
 	S_MULTICAST_CTRL,
+	P_XMII_CTRL_0,
 	P_XMII_CTRL_1,
 };
 
@@ -215,6 +216,8 @@ enum ksz_shifts {
 enum ksz_values {
 	P_MII_1GBIT,
 	P_MII_NOT_1GBIT,
+	P_MII_100MBIT,
+	P_MII_10MBIT,
 };
 
 struct alu_struct {
@@ -304,6 +307,7 @@ void ksz_r_mib_stats64(struct ksz_device *dev, int port);
 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
 bool ksz_get_gbit(struct ksz_device *dev, int port);
 void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit);
+void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed);
 extern const struct ksz_chip_data ksz_switch_chips[];
 
 /* Common register access functions */
@@ -468,6 +472,8 @@ static inline int is_lan937x(struct ksz_device *dev)
 #define SW_START			0x01
 
 /* xMII configuration */
+#define P_MII_100MBIT_M			BIT(4)
+
 #define P_MII_1GBIT_M			BIT(6)
 
 /* Regmap tables generation */
diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
index efca96b02e15..37f63110e5bb 100644
--- a/drivers/net/dsa/microchip/lan937x_main.c
+++ b/drivers/net/dsa/microchip/lan937x_main.c
@@ -346,21 +346,18 @@ static void lan937x_config_interface(struct ksz_device *dev, int port,
 				     int speed, int duplex,
 				     bool tx_pause, bool rx_pause)
 {
-	u8 xmii_ctrl0, xmii_ctrl1;
+	u8 xmii_ctrl0;
 
 	ksz_pread8(dev, port, REG_PORT_XMII_CTRL_0, &xmii_ctrl0);
-	ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &xmii_ctrl1);
 
-	xmii_ctrl0 &= ~(PORT_MII_100MBIT | PORT_MII_FULL_DUPLEX |
-			PORT_MII_TX_FLOW_CTRL | PORT_MII_RX_FLOW_CTRL);
+	xmii_ctrl0 &= ~(PORT_MII_FULL_DUPLEX | PORT_MII_TX_FLOW_CTRL |
+			PORT_MII_RX_FLOW_CTRL);
 
 	if (speed == SPEED_1000)
 		ksz_set_gbit(dev, port, true);
-	else
-		ksz_set_gbit(dev, port, false);
 
-	if (speed == SPEED_100)
-		xmii_ctrl0 |= PORT_MII_100MBIT;
+	if (speed == SPEED_100 || speed == SPEED_10)
+		ksz_set_100_10mbit(dev, port, speed);
 
 	if (duplex)
 		xmii_ctrl0 |= PORT_MII_FULL_DUPLEX;
@@ -372,7 +369,6 @@ static void lan937x_config_interface(struct ksz_device *dev, int port,
 		xmii_ctrl0 |= PORT_MII_RX_FLOW_CTRL;
 
 	ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_0, xmii_ctrl0);
-	ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, xmii_ctrl1);
 }
 
 void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h
index 747295d34411..b9364f6a4f8f 100644
--- a/drivers/net/dsa/microchip/lan937x_reg.h
+++ b/drivers/net/dsa/microchip/lan937x_reg.h
@@ -135,7 +135,6 @@
 #define PORT_SGMII_SEL			BIT(7)
 #define PORT_MII_FULL_DUPLEX		BIT(6)
 #define PORT_MII_TX_FLOW_CTRL		BIT(5)
-#define PORT_MII_100MBIT		BIT(4)
 #define PORT_MII_RX_FLOW_CTRL		BIT(3)
 #define PORT_GRXC_ENABLE		BIT(0)
 
-- 
2.36.1

Re: [RFC Patch net-next 03/10] net: dsa: microchip: add common 100/10Mbps selection function

[Vladimir Oltean]

On Tue, Jul 12, 2022 at 09:33:01PM +0530, Arun Ramadoss wrote:
> This patch adds the function for configuring the 100/10Mbps speed
> selection for the ksz switches. KSZ8795 switch uses Global control 4
> register 0x06 bit 4 for choosing 100/10Mpbs. Other switches uses xMII
> control 1 0xN300 for it.
> For KSZ8795, if the bit is set then 10Mbps is chosen and if bit is
> clear then 100Mbps chosen. For all other switches it is other way
> around, if the bit is set then 100Mbps is chosen.
> So, this patch add the generic function for ksz switch to select the
> 100/10Mbps speed selection. While configuring, first it disables the
> gigabit functionality and then configure the respective speed.
> 
> Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
> ---
>  drivers/net/dsa/microchip/ksz9477_reg.h  |  1 -
>  drivers/net/dsa/microchip/ksz_common.c   | 29 ++++++++++++++++++++++++
>  drivers/net/dsa/microchip/ksz_common.h   |  6 +++++
>  drivers/net/dsa/microchip/lan937x_main.c | 14 ++++--------
>  drivers/net/dsa/microchip/lan937x_reg.h  |  1 -
>  5 files changed, 40 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/net/dsa/microchip/ksz9477_reg.h b/drivers/net/dsa/microchip/ksz9477_reg.h
> index f23ed4809e47..2649fdf0bae1 100644
> --- a/drivers/net/dsa/microchip/ksz9477_reg.h
> +++ b/drivers/net/dsa/microchip/ksz9477_reg.h
> @@ -1179,7 +1179,6 @@
>  
>  #define PORT_SGMII_SEL			BIT(7)
>  #define PORT_MII_FULL_DUPLEX		BIT(6)
> -#define PORT_MII_100MBIT		BIT(4)
>  #define PORT_GRXC_ENABLE		BIT(0)
>  
>  #define REG_PORT_XMII_CTRL_1		0x0301
> diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
> index 5ebcd87fc531..f41cd2801210 100644
> --- a/drivers/net/dsa/microchip/ksz_common.c
> +++ b/drivers/net/dsa/microchip/ksz_common.c
> @@ -256,6 +256,7 @@ static const u16 ksz8795_regs[] = {
>  	[S_START_CTRL]			= 0x01,
>  	[S_BROADCAST_CTRL]		= 0x06,
>  	[S_MULTICAST_CTRL]		= 0x04,
> +	[P_XMII_CTRL_0]			= 0x06,
>  	[P_XMII_CTRL_1]			= 0x56,
>  };
>  
> @@ -284,6 +285,8 @@ static const u32 ksz8795_masks[] = {
>  static const u8 ksz8795_values[] = {
>  	[P_MII_1GBIT]			= 1,
>  	[P_MII_NOT_1GBIT]		= 0,
> +	[P_MII_100MBIT]			= 0,
> +	[P_MII_10MBIT]			= 1,

Can you namespace P_GMII_1GBIT/P_GMII_NOT_1GBIT separately from
P_MII_100MBIT/P_MII_10MBIT? Otherwise it's not obvious that the first
set writes to regs[P_XMII_CTRL_1] and the other to regs[P_XMII_CTRL_0].

>  };
>  
>  static const u8 ksz8795_shifts[] = {
> @@ -356,6 +359,7 @@ static const u16 ksz9477_regs[] = {
>  	[S_START_CTRL]			= 0x0300,
>  	[S_BROADCAST_CTRL]		= 0x0332,
>  	[S_MULTICAST_CTRL]		= 0x0331,
> +	[P_XMII_CTRL_0]			= 0x0300,
>  	[P_XMII_CTRL_1]			= 0x0301,
>  };
>  
> @@ -371,11 +375,15 @@ static const u8 ksz9477_shifts[] = {
>  static const u8 ksz9477_values[] = {
>  	[P_MII_1GBIT]			= 0,
>  	[P_MII_NOT_1GBIT]		= 1,
> +	[P_MII_100MBIT]			= 1,
> +	[P_MII_10MBIT]			= 0,
>  };
>  
>  static const u8 ksz9893_values[] = {
>  	[P_MII_1GBIT]			= 1,
>  	[P_MII_NOT_1GBIT]		= 0,
> +	[P_MII_100MBIT]			= 1,
> +	[P_MII_10MBIT]			= 0,
>  };
>  
>  static const u32 lan937x_masks[] = {
> @@ -1418,6 +1426,27 @@ void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
>  	ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
>  }
>  
> +void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
> +{
> +	const u8 *bitval = dev->info->bitval;
> +	const u16 *regs = dev->info->regs;
> +	u8 data8;
> +
> +	ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
> +
> +	data8 &= ~P_MII_100MBIT_M;
> +
> +	ksz_set_gbit(dev, port, false);
> +
> +	if (speed == SPEED_100)
> +		data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]);
> +	else
> +		data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]);
> +
> +	/* Write the updated value */
> +	ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
> +}
> +
>  static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,
>  				    unsigned int mode,
>  				    phy_interface_t interface,
> diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
> index a76dfef6309c..f1fa6feca559 100644
> --- a/drivers/net/dsa/microchip/ksz_common.h
> +++ b/drivers/net/dsa/microchip/ksz_common.h
> @@ -172,6 +172,7 @@ enum ksz_regs {
>  	S_START_CTRL,
>  	S_BROADCAST_CTRL,
>  	S_MULTICAST_CTRL,
> +	P_XMII_CTRL_0,
>  	P_XMII_CTRL_1,
>  };
>  
> @@ -215,6 +216,8 @@ enum ksz_shifts {
>  enum ksz_values {
>  	P_MII_1GBIT,
>  	P_MII_NOT_1GBIT,
> +	P_MII_100MBIT,
> +	P_MII_10MBIT,
>  };
>  
>  struct alu_struct {
> @@ -304,6 +307,7 @@ void ksz_r_mib_stats64(struct ksz_device *dev, int port);
>  void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
>  bool ksz_get_gbit(struct ksz_device *dev, int port);
>  void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit);
> +void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed);
>  extern const struct ksz_chip_data ksz_switch_chips[];
>  
>  /* Common register access functions */
> @@ -468,6 +472,8 @@ static inline int is_lan937x(struct ksz_device *dev)
>  #define SW_START			0x01
>  
>  /* xMII configuration */
> +#define P_MII_100MBIT_M			BIT(4)
> +
>  #define P_MII_1GBIT_M			BIT(6)
>  
>  /* Regmap tables generation */
> diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
> index efca96b02e15..37f63110e5bb 100644
> --- a/drivers/net/dsa/microchip/lan937x_main.c
> +++ b/drivers/net/dsa/microchip/lan937x_main.c
> @@ -346,21 +346,18 @@ static void lan937x_config_interface(struct ksz_device *dev, int port,
>  				     int speed, int duplex,
>  				     bool tx_pause, bool rx_pause)
>  {
> -	u8 xmii_ctrl0, xmii_ctrl1;
> +	u8 xmii_ctrl0;
>  
>  	ksz_pread8(dev, port, REG_PORT_XMII_CTRL_0, &xmii_ctrl0);
> -	ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &xmii_ctrl1);
>  
> -	xmii_ctrl0 &= ~(PORT_MII_100MBIT | PORT_MII_FULL_DUPLEX |
> -			PORT_MII_TX_FLOW_CTRL | PORT_MII_RX_FLOW_CTRL);
> +	xmii_ctrl0 &= ~(PORT_MII_FULL_DUPLEX | PORT_MII_TX_FLOW_CTRL |
> +			PORT_MII_RX_FLOW_CTRL);
>  
>  	if (speed == SPEED_1000)
>  		ksz_set_gbit(dev, port, true);
> -	else
> -		ksz_set_gbit(dev, port, false);
>  
> -	if (speed == SPEED_100)
> -		xmii_ctrl0 |= PORT_MII_100MBIT;
> +	if (speed == SPEED_100 || speed == SPEED_10)
> +		ksz_set_100_10mbit(dev, port, speed);

Why don't you create a single ksz_port_set_xmii_speed() entry point, and
this decides whether to call ksz_set_gbit() with true or false depending
on whether the speed was 1000, and ksz_set_100_10mbit() as appropriate?

>  
>  	if (duplex)
>  		xmii_ctrl0 |= PORT_MII_FULL_DUPLEX;
> @@ -372,7 +369,6 @@ static void lan937x_config_interface(struct ksz_device *dev, int port,
>  		xmii_ctrl0 |= PORT_MII_RX_FLOW_CTRL;
>  
>  	ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_0, xmii_ctrl0);
> -	ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, xmii_ctrl1);

Will these remaining ksz_pwrite8 calls to REG_PORT_XMII_CTRL_0 not
overwrite what ksz_set_gbit() is doing?

>  }
>  
>  void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
> diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h
> index 747295d34411..b9364f6a4f8f 100644
> --- a/drivers/net/dsa/microchip/lan937x_reg.h
> +++ b/drivers/net/dsa/microchip/lan937x_reg.h
> @@ -135,7 +135,6 @@
>  #define PORT_SGMII_SEL			BIT(7)
>  #define PORT_MII_FULL_DUPLEX		BIT(6)
>  #define PORT_MII_TX_FLOW_CTRL		BIT(5)
> -#define PORT_MII_100MBIT		BIT(4)
>  #define PORT_MII_RX_FLOW_CTRL		BIT(3)
>  #define PORT_GRXC_ENABLE		BIT(0)
>  
> -- 
> 2.36.1
> 

Re: [RFC Patch net-next 03/10] net: dsa: microchip: add common 100/10Mbps selection function

[Arun.Ramadoss]

Hi Vladimir,
On Tue, 2022-07-19 at 13:48 +0300, Vladimir Oltean wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> 
> On Tue, Jul 12, 2022 at 09:33:01PM +0530, Arun Ramadoss wrote:
> > This patch adds the function for configuring the 100/10Mbps speed
> > selection for the ksz switches. KSZ8795 switch uses Global control
> > 4
> > register 0x06 bit 4 for choosing 100/10Mpbs. Other switches uses
> > xMII
> > control 1 0xN300 for it.
> > For KSZ8795, if the bit is set then 10Mbps is chosen and if bit is
> > clear then 100Mbps chosen. For all other switches it is other way
> > around, if the bit is set then 100Mbps is chosen.
> > So, this patch add the generic function for ksz switch to select
> > the
> > 100/10Mbps speed selection. While configuring, first it disables
> > the
> > gigabit functionality and then configure the respective speed.
> > 
> > Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
> > ---
> >  drivers/net/dsa/microchip/ksz9477_reg.h  |  1 -
> >  drivers/net/dsa/microchip/ksz_common.c   | 29
> > ++++++++++++++++++++++++
> >  drivers/net/dsa/microchip/ksz_common.h   |  6 +++++
> >  drivers/net/dsa/microchip/lan937x_main.c | 14 ++++--------
> >  drivers/net/dsa/microchip/lan937x_reg.h  |  1 -
> >  5 files changed, 40 insertions(+), 11 deletions(-)
> > 
> > diff --git a/drivers/net/dsa/microchip/ksz9477_reg.h
> > b/drivers/net/dsa/microchip/ksz9477_reg.h
> > index f23ed4809e47..2649fdf0bae1 100644
> > --- a/drivers/net/dsa/microchip/ksz9477_reg.h
> > +++ b/drivers/net/dsa/microchip/ksz9477_reg.h
> > @@ -1179,7 +1179,6 @@
> > 
> >  #define PORT_SGMII_SEL                       BIT(7)
> >  #define PORT_MII_FULL_DUPLEX         BIT(6)
> > -#define PORT_MII_100MBIT             BIT(4)
> >  #define PORT_GRXC_ENABLE             BIT(0)
> > 
> >  #define REG_PORT_XMII_CTRL_1         0x0301
> > diff --git a/drivers/net/dsa/microchip/ksz_common.c
> > b/drivers/net/dsa/microchip/ksz_common.c
> > index 5ebcd87fc531..f41cd2801210 100644
> > --- a/drivers/net/dsa/microchip/ksz_common.c
> > +++ b/drivers/net/dsa/microchip/ksz_common.c
> > @@ -256,6 +256,7 @@ static const u16 ksz8795_regs[] = {
> >       [S_START_CTRL]                  = 0x01,
> >       [S_BROADCAST_CTRL]              = 0x06,
> >       [S_MULTICAST_CTRL]              = 0x04,
> > +     [P_XMII_CTRL_0]                 = 0x06,
> >       [P_XMII_CTRL_1]                 = 0x56,
> >  };
> > 
> > @@ -284,6 +285,8 @@ static const u32 ksz8795_masks[] = {
> >  static const u8 ksz8795_values[] = {
> >       [P_MII_1GBIT]                   = 1,
> >       [P_MII_NOT_1GBIT]               = 0,
> > +     [P_MII_100MBIT]                 = 0,
> > +     [P_MII_10MBIT]                  = 1,
> 
> Can you namespace P_GMII_1GBIT/P_GMII_NOT_1GBIT separately from
> P_MII_100MBIT/P_MII_10MBIT? Otherwise it's not obvious that the first
> set writes to regs[P_XMII_CTRL_1] and the other to
> regs[P_XMII_CTRL_0].

Yes, I can do it.

> 
> >  };
> > 
> >  static const u8 ksz8795_shifts[] = {
> > @@ -356,6 +359,7 @@ static const u16 ksz9477_regs[] = {
> >       [S_START_CTRL]                  = 0x0300,
> >       [S_BROADCAST_CTRL]              = 0x0332,
> >       [S_MULTICAST_CTRL]              = 0x0331,
> > +     [P_XMII_CTRL_0]                 = 0x0300,
> >       [P_XMII_CTRL_1]                 = 0x0301,
> >  };
> > 
> > 
> > diff --git a/drivers/net/dsa/microchip/ksz_common.h
> > b/drivers/net/dsa/microchip/ksz_common.h
> > index a76dfef6309c..f1fa6feca559 100644
> > --- a/drivers/net/dsa/microchip/ksz_common.h
> > +++ b/drivers/net/dsa/microchip/ksz_common.h
> > @@ -172,6 +172,7 @@ enum ksz_regs {
> >       S_START_CTRL,
> >       S_BROADCAST_CTRL,
> >       S_MULTICAST_CTRL,
> > +     P_XMII_CTRL_0,
> >       P_XMII_CTRL_1,
> >  };
> > 
> > 
> >  /* Regmap tables generation */
> > diff --git a/drivers/net/dsa/microchip/lan937x_main.c
> > b/drivers/net/dsa/microchip/lan937x_main.c
> > index efca96b02e15..37f63110e5bb 100644
> > --- a/drivers/net/dsa/microchip/lan937x_main.c
> > +++ b/drivers/net/dsa/microchip/lan937x_main.c
> > @@ -346,21 +346,18 @@ static void lan937x_config_interface(struct
> > ksz_device *dev, int port,
> >                                    int speed, int duplex,
> >                                    bool tx_pause, bool rx_pause)
> >  {
> > -     u8 xmii_ctrl0, xmii_ctrl1;
> > +     u8 xmii_ctrl0;
> > 
> >       ksz_pread8(dev, port, REG_PORT_XMII_CTRL_0, &xmii_ctrl0);
> > -     ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &xmii_ctrl1);
> > 
> > -     xmii_ctrl0 &= ~(PORT_MII_100MBIT | PORT_MII_FULL_DUPLEX |
> > -                     PORT_MII_TX_FLOW_CTRL |
> > PORT_MII_RX_FLOW_CTRL);
> > +     xmii_ctrl0 &= ~(PORT_MII_FULL_DUPLEX | PORT_MII_TX_FLOW_CTRL
> > |
> > +                     PORT_MII_RX_FLOW_CTRL);
> > 
> >       if (speed == SPEED_1000)
> >               ksz_set_gbit(dev, port, true);
> > -     else
> > -             ksz_set_gbit(dev, port, false);
> > 
> > -     if (speed == SPEED_100)
> > -             xmii_ctrl0 |= PORT_MII_100MBIT;
> > +     if (speed == SPEED_100 || speed == SPEED_10)
> > +             ksz_set_100_10mbit(dev, port, speed);
> 
> Why don't you create a single ksz_port_set_xmii_speed() entry point,
> and
> this decides whether to call ksz_set_gbit() with true or false
> depending
> on whether the speed was 1000, and ksz_set_100_10mbit() as
> appropriate?

Ok, I will create new function.

> > 
> >       if (duplex)
> >               xmii_ctrl0 |= PORT_MII_FULL_DUPLEX;
> > @@ -372,7 +369,6 @@ static void lan937x_config_interface(struct
> > ksz_device *dev, int port,
> >               xmii_ctrl0 |= PORT_MII_RX_FLOW_CTRL;
> > 
> >       ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_0, xmii_ctrl0);
> > -     ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, xmii_ctrl1);
> 
> Will these remaining ksz_pwrite8 calls to REG_PORT_XMII_CTRL_0 not
> overwrite what ksz_set_gbit() is doing?

Yes, this ksz_pwrite8 overwrites the ksz_set_gbit. But the next patch
updates the duplex and flow control separately, I tested the phylink
register configuration only after applying entire series. So I missed
this. Thanks for pointing it.
I will move the reading the xmii_ctrl0 after configuring the
ksz_set_gbit().

> 
> >  }
> > 
> >  void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
> > diff --git a/drivers/net/dsa/microchip/lan937x_reg.h
> > b/drivers/net/dsa/microchip/lan937x_reg.h
> > index 747295d34411..b9364f6a4f8f 100644
> > --- a/drivers/net/dsa/microchip/lan937x_reg.h
> > +++ b/drivers/net/dsa/microchip/lan937x_reg.h
> > @@ -135,7 +135,6 @@
> >  #define PORT_SGMII_SEL                       BIT(7)
> >  #define PORT_MII_FULL_DUPLEX         BIT(6)
> >  #define PORT_MII_TX_FLOW_CTRL                BIT(5)
> > -#define PORT_MII_100MBIT             BIT(4)
> >  #define PORT_MII_RX_FLOW_CTRL                BIT(3)
> >  #define PORT_GRXC_ENABLE             BIT(0)
> > 
> > --
> > 2.36.1
> > 

[RFC Patch net-next 04/10] net: dsa: microchip: add common duplex and flow control function

[Arun Ramadoss]

This patch add common function for configuring the Full/Half duplex and
transmit/receive flow control. KSZ8795 uses the Global control register
4 for configuring the duplex and flow control, whereas all other KSZ9477
based switch uses the xMII Control 0 register.

Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
---
 drivers/net/dsa/microchip/ksz9477_reg.h  |  1 -
 drivers/net/dsa/microchip/ksz_common.c   | 64 ++++++++++++++++++++++++
 drivers/net/dsa/microchip/ksz_common.h   |  8 +++
 drivers/net/dsa/microchip/lan937x_main.c | 24 +++------
 drivers/net/dsa/microchip/lan937x_reg.h  |  3 --
 5 files changed, 80 insertions(+), 20 deletions(-)

diff --git a/drivers/net/dsa/microchip/ksz9477_reg.h b/drivers/net/dsa/microchip/ksz9477_reg.h
index 2649fdf0bae1..6ca859345932 100644
--- a/drivers/net/dsa/microchip/ksz9477_reg.h
+++ b/drivers/net/dsa/microchip/ksz9477_reg.h
@@ -1178,7 +1178,6 @@
 #define REG_PORT_XMII_CTRL_0		0x0300
 
 #define PORT_SGMII_SEL			BIT(7)
-#define PORT_MII_FULL_DUPLEX		BIT(6)
 #define PORT_GRXC_ENABLE		BIT(0)
 
 #define REG_PORT_XMII_CTRL_1		0x0301
diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index f41cd2801210..4ef0ee9a245d 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -280,6 +280,8 @@ static const u32 ksz8795_masks[] = {
 	[DYNAMIC_MAC_TABLE_FID]		= GENMASK(26, 20),
 	[DYNAMIC_MAC_TABLE_SRC_PORT]	= GENMASK(26, 24),
 	[DYNAMIC_MAC_TABLE_TIMESTAMP]	= GENMASK(28, 27),
+	[P_MII_TX_FLOW_CTRL]		= BIT(5),
+	[P_MII_RX_FLOW_CTRL]		= BIT(5),
 };
 
 static const u8 ksz8795_values[] = {
@@ -287,6 +289,8 @@ static const u8 ksz8795_values[] = {
 	[P_MII_NOT_1GBIT]		= 0,
 	[P_MII_100MBIT]			= 0,
 	[P_MII_10MBIT]			= 1,
+	[P_MII_FULL_DUPLEX]		= 0,
+	[P_MII_HALF_DUPLEX]		= 1,
 };
 
 static const u8 ksz8795_shifts[] = {
@@ -366,6 +370,8 @@ static const u16 ksz9477_regs[] = {
 static const u32 ksz9477_masks[] = {
 	[ALU_STAT_WRITE]		= 0,
 	[ALU_STAT_READ]			= 1,
+	[P_MII_TX_FLOW_CTRL]		= BIT(5),
+	[P_MII_RX_FLOW_CTRL]		= BIT(3),
 };
 
 static const u8 ksz9477_shifts[] = {
@@ -377,6 +383,8 @@ static const u8 ksz9477_values[] = {
 	[P_MII_NOT_1GBIT]		= 1,
 	[P_MII_100MBIT]			= 1,
 	[P_MII_10MBIT]			= 0,
+	[P_MII_FULL_DUPLEX]		= 1,
+	[P_MII_HALF_DUPLEX]		= 0,
 };
 
 static const u8 ksz9893_values[] = {
@@ -384,11 +392,15 @@ static const u8 ksz9893_values[] = {
 	[P_MII_NOT_1GBIT]		= 0,
 	[P_MII_100MBIT]			= 1,
 	[P_MII_10MBIT]			= 0,
+	[P_MII_FULL_DUPLEX]		= 1,
+	[P_MII_HALF_DUPLEX]		= 0,
 };
 
 static const u32 lan937x_masks[] = {
 	[ALU_STAT_WRITE]		= 1,
 	[ALU_STAT_READ]			= 2,
+	[P_MII_TX_FLOW_CTRL]		= BIT(5),
+	[P_MII_RX_FLOW_CTRL]		= BIT(3),
 };
 
 static const u8 lan937x_shifts[] = {
@@ -1447,6 +1459,58 @@ void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
 	ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
 }
 
+void ksz_set_fullduplex(struct ksz_device *dev, int port, bool val)
+{
+	const u8 *bitval = dev->info->bitval;
+	const u16 *regs = dev->info->regs;
+	u8 data8;
+
+	ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
+
+	data8 &= ~P_MII_DUPLEX_M;
+
+	if (val)
+		data8 |= FIELD_PREP(P_MII_DUPLEX_M,
+				    bitval[P_MII_FULL_DUPLEX]);
+	else
+		data8 |= FIELD_PREP(P_MII_DUPLEX_M,
+				    bitval[P_MII_HALF_DUPLEX]);
+
+	ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
+}
+
+void ksz_set_tx_pause(struct ksz_device *dev, int port, bool val)
+{
+	const u32 *masks = dev->info->masks;
+	const u16 *regs = dev->info->regs;
+	u8 data8;
+
+	ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
+
+	if (val)
+		data8 |= masks[P_MII_TX_FLOW_CTRL];
+	else
+		data8 &= ~masks[P_MII_TX_FLOW_CTRL];
+
+	ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
+}
+
+void ksz_set_rx_pause(struct ksz_device *dev, int port, bool val)
+{
+	const u32 *masks = dev->info->masks;
+	const u16 *regs = dev->info->regs;
+	u8 data8;
+
+	ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
+
+	if (val)
+		data8 |= masks[P_MII_RX_FLOW_CTRL];
+	else
+		data8 &= ~masks[P_MII_RX_FLOW_CTRL];
+
+	ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
+}
+
 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,
 				    unsigned int mode,
 				    phy_interface_t interface,
diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
index f1fa6feca559..851ee50895a4 100644
--- a/drivers/net/dsa/microchip/ksz_common.h
+++ b/drivers/net/dsa/microchip/ksz_common.h
@@ -198,6 +198,8 @@ enum ksz_masks {
 	DYNAMIC_MAC_TABLE_TIMESTAMP,
 	ALU_STAT_WRITE,
 	ALU_STAT_READ,
+	P_MII_TX_FLOW_CTRL,
+	P_MII_RX_FLOW_CTRL,
 };
 
 enum ksz_shifts {
@@ -218,6 +220,8 @@ enum ksz_values {
 	P_MII_NOT_1GBIT,
 	P_MII_100MBIT,
 	P_MII_10MBIT,
+	P_MII_FULL_DUPLEX,
+	P_MII_HALF_DUPLEX,
 };
 
 struct alu_struct {
@@ -308,6 +312,9 @@ void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
 bool ksz_get_gbit(struct ksz_device *dev, int port);
 void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit);
 void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed);
+void ksz_set_fullduplex(struct ksz_device *dev, int port, bool val);
+void ksz_set_tx_pause(struct ksz_device *dev, int port, bool val);
+void ksz_set_rx_pause(struct ksz_device *dev, int port, bool val);
 extern const struct ksz_chip_data ksz_switch_chips[];
 
 /* Common register access functions */
@@ -472,6 +479,7 @@ static inline int is_lan937x(struct ksz_device *dev)
 #define SW_START			0x01
 
 /* xMII configuration */
+#define P_MII_DUPLEX_M			BIT(6)
 #define P_MII_100MBIT_M			BIT(4)
 
 #define P_MII_1GBIT_M			BIT(6)
diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
index 37f63110e5bb..67b03ab0ede3 100644
--- a/drivers/net/dsa/microchip/lan937x_main.c
+++ b/drivers/net/dsa/microchip/lan937x_main.c
@@ -234,6 +234,8 @@ int lan937x_reset_switch(struct ksz_device *dev)
 
 void lan937x_port_setup(struct ksz_device *dev, int port, bool cpu_port)
 {
+	const u32 *masks = dev->info->masks;
+	const u16 *regs = dev->info->regs;
 	struct dsa_switch *ds = dev->ds;
 	u8 member;
 
@@ -254,8 +256,9 @@ void lan937x_port_setup(struct ksz_device *dev, int port, bool cpu_port)
 	lan937x_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
 
 	if (!dev->info->internal_phy[port])
-		lan937x_port_cfg(dev, port, REG_PORT_XMII_CTRL_0,
-				 PORT_MII_TX_FLOW_CTRL | PORT_MII_RX_FLOW_CTRL,
+		lan937x_port_cfg(dev, port, regs[P_XMII_CTRL_0],
+				 masks[P_MII_TX_FLOW_CTRL] |
+				 masks[P_MII_RX_FLOW_CTRL],
 				 true);
 
 	if (cpu_port)
@@ -346,29 +349,18 @@ static void lan937x_config_interface(struct ksz_device *dev, int port,
 				     int speed, int duplex,
 				     bool tx_pause, bool rx_pause)
 {
-	u8 xmii_ctrl0;
-
-	ksz_pread8(dev, port, REG_PORT_XMII_CTRL_0, &xmii_ctrl0);
-
-	xmii_ctrl0 &= ~(PORT_MII_FULL_DUPLEX | PORT_MII_TX_FLOW_CTRL |
-			PORT_MII_RX_FLOW_CTRL);
-
 	if (speed == SPEED_1000)
 		ksz_set_gbit(dev, port, true);
 
 	if (speed == SPEED_100 || speed == SPEED_10)
 		ksz_set_100_10mbit(dev, port, speed);
 
-	if (duplex)
-		xmii_ctrl0 |= PORT_MII_FULL_DUPLEX;
+	ksz_set_fullduplex(dev, port, duplex);
 
-	if (tx_pause)
-		xmii_ctrl0 |= PORT_MII_TX_FLOW_CTRL;
+	ksz_set_tx_pause(dev, port, tx_pause);
 
-	if (rx_pause)
-		xmii_ctrl0 |= PORT_MII_RX_FLOW_CTRL;
+	ksz_set_rx_pause(dev, port, rx_pause);
 
-	ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_0, xmii_ctrl0);
 }
 
 void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h
index b9364f6a4f8f..d5eb6dc3a739 100644
--- a/drivers/net/dsa/microchip/lan937x_reg.h
+++ b/drivers/net/dsa/microchip/lan937x_reg.h
@@ -133,9 +133,6 @@
 /* 3 - xMII */
 #define REG_PORT_XMII_CTRL_0		0x0300
 #define PORT_SGMII_SEL			BIT(7)
-#define PORT_MII_FULL_DUPLEX		BIT(6)
-#define PORT_MII_TX_FLOW_CTRL		BIT(5)
-#define PORT_MII_RX_FLOW_CTRL		BIT(3)
 #define PORT_GRXC_ENABLE		BIT(0)
 
 #define REG_PORT_XMII_CTRL_1		0x0301
-- 
2.36.1

Re: [RFC Patch net-next 04/10] net: dsa: microchip: add common duplex and flow control function

[Vladimir Oltean]

On Tue, Jul 12, 2022 at 09:33:02PM +0530, Arun Ramadoss wrote:
> This patch add common function for configuring the Full/Half duplex and
> transmit/receive flow control. KSZ8795 uses the Global control register
> 4 for configuring the duplex and flow control, whereas all other KSZ9477
> based switch uses the xMII Control 0 register.
> 
> Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
> ---
>  drivers/net/dsa/microchip/ksz9477_reg.h  |  1 -
>  drivers/net/dsa/microchip/ksz_common.c   | 64 ++++++++++++++++++++++++
>  drivers/net/dsa/microchip/ksz_common.h   |  8 +++
>  drivers/net/dsa/microchip/lan937x_main.c | 24 +++------
>  drivers/net/dsa/microchip/lan937x_reg.h  |  3 --
>  5 files changed, 80 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/net/dsa/microchip/ksz9477_reg.h b/drivers/net/dsa/microchip/ksz9477_reg.h
> index 2649fdf0bae1..6ca859345932 100644
> --- a/drivers/net/dsa/microchip/ksz9477_reg.h
> +++ b/drivers/net/dsa/microchip/ksz9477_reg.h
> @@ -1178,7 +1178,6 @@
>  #define REG_PORT_XMII_CTRL_0		0x0300
>  
>  #define PORT_SGMII_SEL			BIT(7)
> -#define PORT_MII_FULL_DUPLEX		BIT(6)
>  #define PORT_GRXC_ENABLE		BIT(0)
>  
>  #define REG_PORT_XMII_CTRL_1		0x0301
> diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
> index f41cd2801210..4ef0ee9a245d 100644
> --- a/drivers/net/dsa/microchip/ksz_common.c
> +++ b/drivers/net/dsa/microchip/ksz_common.c
> @@ -280,6 +280,8 @@ static const u32 ksz8795_masks[] = {
>  	[DYNAMIC_MAC_TABLE_FID]		= GENMASK(26, 20),
>  	[DYNAMIC_MAC_TABLE_SRC_PORT]	= GENMASK(26, 24),
>  	[DYNAMIC_MAC_TABLE_TIMESTAMP]	= GENMASK(28, 27),
> +	[P_MII_TX_FLOW_CTRL]		= BIT(5),
> +	[P_MII_RX_FLOW_CTRL]		= BIT(5),

The masks are the same for TX and RX flow control and the writes are to
the same register (regs[P_XMII_CTRL_0]), is this an error?

>  };
>  
>  static const u8 ksz8795_values[] = {
> @@ -287,6 +289,8 @@ static const u8 ksz8795_values[] = {
>  	[P_MII_NOT_1GBIT]		= 0,
>  	[P_MII_100MBIT]			= 0,
>  	[P_MII_10MBIT]			= 1,
> +	[P_MII_FULL_DUPLEX]		= 0,
> +	[P_MII_HALF_DUPLEX]		= 1,
>  };
>  
>  static const u8 ksz8795_shifts[] = {
> @@ -366,6 +370,8 @@ static const u16 ksz9477_regs[] = {
>  static const u32 ksz9477_masks[] = {
>  	[ALU_STAT_WRITE]		= 0,
>  	[ALU_STAT_READ]			= 1,
> +	[P_MII_TX_FLOW_CTRL]		= BIT(5),
> +	[P_MII_RX_FLOW_CTRL]		= BIT(3),
>  };
>  
>  static const u8 ksz9477_shifts[] = {
> @@ -377,6 +383,8 @@ static const u8 ksz9477_values[] = {
>  	[P_MII_NOT_1GBIT]		= 1,
>  	[P_MII_100MBIT]			= 1,
>  	[P_MII_10MBIT]			= 0,
> +	[P_MII_FULL_DUPLEX]		= 1,
> +	[P_MII_HALF_DUPLEX]		= 0,
>  };
>  
>  static const u8 ksz9893_values[] = {
> @@ -384,11 +392,15 @@ static const u8 ksz9893_values[] = {
>  	[P_MII_NOT_1GBIT]		= 0,
>  	[P_MII_100MBIT]			= 1,
>  	[P_MII_10MBIT]			= 0,
> +	[P_MII_FULL_DUPLEX]		= 1,
> +	[P_MII_HALF_DUPLEX]		= 0,
>  };
>  
>  static const u32 lan937x_masks[] = {
>  	[ALU_STAT_WRITE]		= 1,
>  	[ALU_STAT_READ]			= 2,
> +	[P_MII_TX_FLOW_CTRL]		= BIT(5),
> +	[P_MII_RX_FLOW_CTRL]		= BIT(3),
>  };
>  
>  static const u8 lan937x_shifts[] = {
> @@ -1447,6 +1459,58 @@ void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
>  	ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
>  }
>  
> +void ksz_set_fullduplex(struct ksz_device *dev, int port, bool val)
> +{
> +	const u8 *bitval = dev->info->bitval;
> +	const u16 *regs = dev->info->regs;
> +	u8 data8;
> +
> +	ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
> +
> +	data8 &= ~P_MII_DUPLEX_M;
> +
> +	if (val)
> +		data8 |= FIELD_PREP(P_MII_DUPLEX_M,
> +				    bitval[P_MII_FULL_DUPLEX]);
> +	else
> +		data8 |= FIELD_PREP(P_MII_DUPLEX_M,
> +				    bitval[P_MII_HALF_DUPLEX]);
> +
> +	ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
> +}
> +
> +void ksz_set_tx_pause(struct ksz_device *dev, int port, bool val)
> +{
> +	const u32 *masks = dev->info->masks;
> +	const u16 *regs = dev->info->regs;
> +	u8 data8;
> +
> +	ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
> +
> +	if (val)
> +		data8 |= masks[P_MII_TX_FLOW_CTRL];
> +	else
> +		data8 &= ~masks[P_MII_TX_FLOW_CTRL];
> +
> +	ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
> +}
> +
> +void ksz_set_rx_pause(struct ksz_device *dev, int port, bool val)
> +{
> +	const u32 *masks = dev->info->masks;
> +	const u16 *regs = dev->info->regs;
> +	u8 data8;
> +
> +	ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
> +
> +	if (val)
> +		data8 |= masks[P_MII_RX_FLOW_CTRL];
> +	else
> +		data8 &= ~masks[P_MII_RX_FLOW_CTRL];
> +
> +	ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
> +}
> +
>  static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,
>  				    unsigned int mode,
>  				    phy_interface_t interface,
> diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
> index f1fa6feca559..851ee50895a4 100644
> --- a/drivers/net/dsa/microchip/ksz_common.h
> +++ b/drivers/net/dsa/microchip/ksz_common.h
> @@ -198,6 +198,8 @@ enum ksz_masks {
>  	DYNAMIC_MAC_TABLE_TIMESTAMP,
>  	ALU_STAT_WRITE,
>  	ALU_STAT_READ,
> +	P_MII_TX_FLOW_CTRL,
> +	P_MII_RX_FLOW_CTRL,
>  };
>  
>  enum ksz_shifts {
> @@ -218,6 +220,8 @@ enum ksz_values {
>  	P_MII_NOT_1GBIT,
>  	P_MII_100MBIT,
>  	P_MII_10MBIT,
> +	P_MII_FULL_DUPLEX,
> +	P_MII_HALF_DUPLEX,
>  };
>  
>  struct alu_struct {
> @@ -308,6 +312,9 @@ void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
>  bool ksz_get_gbit(struct ksz_device *dev, int port);
>  void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit);
>  void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed);
> +void ksz_set_fullduplex(struct ksz_device *dev, int port, bool val);
> +void ksz_set_tx_pause(struct ksz_device *dev, int port, bool val);
> +void ksz_set_rx_pause(struct ksz_device *dev, int port, bool val);
>  extern const struct ksz_chip_data ksz_switch_chips[];
>  
>  /* Common register access functions */
> @@ -472,6 +479,7 @@ static inline int is_lan937x(struct ksz_device *dev)
>  #define SW_START			0x01
>  
>  /* xMII configuration */
> +#define P_MII_DUPLEX_M			BIT(6)
>  #define P_MII_100MBIT_M			BIT(4)
>  
>  #define P_MII_1GBIT_M			BIT(6)
> diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
> index 37f63110e5bb..67b03ab0ede3 100644
> --- a/drivers/net/dsa/microchip/lan937x_main.c
> +++ b/drivers/net/dsa/microchip/lan937x_main.c
> @@ -234,6 +234,8 @@ int lan937x_reset_switch(struct ksz_device *dev)
>  
>  void lan937x_port_setup(struct ksz_device *dev, int port, bool cpu_port)
>  {
> +	const u32 *masks = dev->info->masks;
> +	const u16 *regs = dev->info->regs;
>  	struct dsa_switch *ds = dev->ds;
>  	u8 member;
>  
> @@ -254,8 +256,9 @@ void lan937x_port_setup(struct ksz_device *dev, int port, bool cpu_port)
>  	lan937x_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
>  
>  	if (!dev->info->internal_phy[port])
> -		lan937x_port_cfg(dev, port, REG_PORT_XMII_CTRL_0,
> -				 PORT_MII_TX_FLOW_CTRL | PORT_MII_RX_FLOW_CTRL,
> +		lan937x_port_cfg(dev, port, regs[P_XMII_CTRL_0],
> +				 masks[P_MII_TX_FLOW_CTRL] |
> +				 masks[P_MII_RX_FLOW_CTRL],
>  				 true);
>  
>  	if (cpu_port)
> @@ -346,29 +349,18 @@ static void lan937x_config_interface(struct ksz_device *dev, int port,
>  				     int speed, int duplex,
>  				     bool tx_pause, bool rx_pause)
>  {
> -	u8 xmii_ctrl0;
> -
> -	ksz_pread8(dev, port, REG_PORT_XMII_CTRL_0, &xmii_ctrl0);
> -
> -	xmii_ctrl0 &= ~(PORT_MII_FULL_DUPLEX | PORT_MII_TX_FLOW_CTRL |
> -			PORT_MII_RX_FLOW_CTRL);
> -
>  	if (speed == SPEED_1000)
>  		ksz_set_gbit(dev, port, true);
>  
>  	if (speed == SPEED_100 || speed == SPEED_10)
>  		ksz_set_100_10mbit(dev, port, speed);
>  
> -	if (duplex)
> -		xmii_ctrl0 |= PORT_MII_FULL_DUPLEX;
> +	ksz_set_fullduplex(dev, port, duplex);
>  
> -	if (tx_pause)
> -		xmii_ctrl0 |= PORT_MII_TX_FLOW_CTRL;
> +	ksz_set_tx_pause(dev, port, tx_pause);
>  
> -	if (rx_pause)
> -		xmii_ctrl0 |= PORT_MII_RX_FLOW_CTRL;
> +	ksz_set_rx_pause(dev, port, rx_pause);
>  
> -	ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_0, xmii_ctrl0);
>  }
>  
>  void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
> diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h
> index b9364f6a4f8f..d5eb6dc3a739 100644
> --- a/drivers/net/dsa/microchip/lan937x_reg.h
> +++ b/drivers/net/dsa/microchip/lan937x_reg.h
> @@ -133,9 +133,6 @@
>  /* 3 - xMII */
>  #define REG_PORT_XMII_CTRL_0		0x0300
>  #define PORT_SGMII_SEL			BIT(7)
> -#define PORT_MII_FULL_DUPLEX		BIT(6)
> -#define PORT_MII_TX_FLOW_CTRL		BIT(5)
> -#define PORT_MII_RX_FLOW_CTRL		BIT(3)
>  #define PORT_GRXC_ENABLE		BIT(0)
>  
>  #define REG_PORT_XMII_CTRL_1		0x0301
> -- 
> 2.36.1
> 

Re: [RFC Patch net-next 04/10] net: dsa: microchip: add common duplex and flow control function

[Arun.Ramadoss]

On Tue, 2022-07-19 at 13:52 +0300, Vladimir Oltean wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> 
> On Tue, Jul 12, 2022 at 09:33:02PM +0530, Arun Ramadoss wrote:
> > This patch add common function for configuring the Full/Half duplex
> > and
> > transmit/receive flow control. KSZ8795 uses the Global control
> > register
> > 4 for configuring the duplex and flow control, whereas all other
> > KSZ9477
> > based switch uses the xMII Control 0 register.
> > 
> > Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
> > ---
> >  drivers/net/dsa/microchip/ksz9477_reg.h  |  1 -
> >  drivers/net/dsa/microchip/ksz_common.c   | 64
> > ++++++++++++++++++++++++
> >  drivers/net/dsa/microchip/ksz_common.h   |  8 +++
> >  drivers/net/dsa/microchip/lan937x_main.c | 24 +++------
> >  drivers/net/dsa/microchip/lan937x_reg.h  |  3 --
> >  5 files changed, 80 insertions(+), 20 deletions(-)
> > 
> > diff --git a/drivers/net/dsa/microchip/ksz9477_reg.h
> > b/drivers/net/dsa/microchip/ksz9477_reg.h
> > index 2649fdf0bae1..6ca859345932 100644
> > --- a/drivers/net/dsa/microchip/ksz9477_reg.h
> > +++ b/drivers/net/dsa/microchip/ksz9477_reg.h
> > @@ -1178,7 +1178,6 @@
> >  #define REG_PORT_XMII_CTRL_0         0x0300
> > 
> >  #define PORT_SGMII_SEL                       BIT(7)
> > -#define PORT_MII_FULL_DUPLEX         BIT(6)
> >  #define PORT_GRXC_ENABLE             BIT(0)
> > 
> >  #define REG_PORT_XMII_CTRL_1         0x0301
> > diff --git a/drivers/net/dsa/microchip/ksz_common.c
> > b/drivers/net/dsa/microchip/ksz_common.c
> > index f41cd2801210..4ef0ee9a245d 100644
> > --- a/drivers/net/dsa/microchip/ksz_common.c
> > +++ b/drivers/net/dsa/microchip/ksz_common.c
> > @@ -280,6 +280,8 @@ static const u32 ksz8795_masks[] = {
> >       [DYNAMIC_MAC_TABLE_FID]         = GENMASK(26, 20),
> >       [DYNAMIC_MAC_TABLE_SRC_PORT]    = GENMASK(26, 24),
> >       [DYNAMIC_MAC_TABLE_TIMESTAMP]   = GENMASK(28, 27),
> > +     [P_MII_TX_FLOW_CTRL]            = BIT(5),
> > +     [P_MII_RX_FLOW_CTRL]            = BIT(5),
> 
> The masks are the same for TX and RX flow control and the writes are
> to
> the same register (regs[P_XMII_CTRL_0]), is this an error?

I have gone through ksz8795 datasheet, I could not find separate bit
for Tx and Rx flow control bit. Bit 5 mentioned as Flow control on the
switch MII/RMII interface. So I had configured same bit for Tx and Rx.

> 
> >  };
> > 
> >  static const u8 ksz8795_values[] = {
> > @@ -287,6 +289,8 @@ static const u8 ksz8795_values[] = {
> >       [P_MII_NOT_1GBIT]               = 0,
> >       [P_MII_100MBIT]                 = 0,
> >       [P_MII_10MBIT]                  = 1,
> > +     [P_MII_FULL_DUPLEX]             = 0,
> > +     [P_MII_HALF_DUPLEX]             = 1,
> >  };
> > 
> >  static const u8 ksz8795_shifts[] = {
> > @@ -366,6 +370,8 @@ static const u16 ksz9477_regs[] = {
> >  static const u32 ksz9477_masks[] = {
> >       [ALU_STAT_WRITE]                = 0,
> >       [ALU_STAT_READ]                 = 1,
> > +     [P_MII_TX_FLOW_CTRL]            = BIT(5),
> > +     [P_MII_RX_FLOW_CTRL]            = BIT(3),
> >  };
> > 
> > --
> > 2.36.1
> > 
> 
> 

[RFC Patch net-next 05/10] net: dsa: microchip: add support for common phylink mac link up

[Arun Ramadoss]

This patch add the support for common phylink mac link up for the ksz
series switch. The register address, bit position and values are
configured based on the chip id to the dev->info structure.

Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
---
 drivers/net/dsa/microchip/ksz_common.c   | 30 +++++++++++++++++++----
 drivers/net/dsa/microchip/ksz_common.h   |  4 ---
 drivers/net/dsa/microchip/lan937x.h      |  4 ---
 drivers/net/dsa/microchip/lan937x_main.c | 31 ------------------------
 4 files changed, 25 insertions(+), 44 deletions(-)

diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index 4ef0ee9a245d..0cb711fcf046 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -222,7 +222,6 @@ static const struct ksz_dev_ops lan937x_dev_ops = {
 	.mirror_del = ksz9477_port_mirror_del,
 	.get_caps = lan937x_phylink_get_caps,
 	.phylink_mac_config = lan937x_phylink_mac_config,
-	.phylink_mac_link_up = lan937x_phylink_mac_link_up,
 	.fdb_dump = ksz9477_fdb_dump,
 	.fdb_add = ksz9477_fdb_add,
 	.fdb_del = ksz9477_fdb_del,
@@ -1438,7 +1437,7 @@ void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
 	ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
 }
 
-void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
+static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
 {
 	const u8 *bitval = dev->info->bitval;
 	const u16 *regs = dev->info->regs;
@@ -1459,7 +1458,7 @@ void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
 	ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
 }
 
-void ksz_set_fullduplex(struct ksz_device *dev, int port, bool val)
+static void ksz_set_fullduplex(struct ksz_device *dev, int port, bool val)
 {
 	const u8 *bitval = dev->info->bitval;
 	const u16 *regs = dev->info->regs;
@@ -1479,7 +1478,7 @@ void ksz_set_fullduplex(struct ksz_device *dev, int port, bool val)
 	ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
 }
 
-void ksz_set_tx_pause(struct ksz_device *dev, int port, bool val)
+static void ksz_set_tx_pause(struct ksz_device *dev, int port, bool val)
 {
 	const u32 *masks = dev->info->masks;
 	const u16 *regs = dev->info->regs;
@@ -1495,7 +1494,7 @@ void ksz_set_tx_pause(struct ksz_device *dev, int port, bool val)
 	ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
 }
 
-void ksz_set_rx_pause(struct ksz_device *dev, int port, bool val)
+static void ksz_set_rx_pause(struct ksz_device *dev, int port, bool val)
 {
 	const u32 *masks = dev->info->masks;
 	const u16 *regs = dev->info->regs;
@@ -1518,6 +1517,27 @@ static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,
 				    int duplex, bool tx_pause, bool rx_pause)
 {
 	struct ksz_device *dev = ds->priv;
+	struct ksz_port *p;
+
+	p = &dev->ports[port];
+
+	/* Internal PHYs */
+	if (dev->info->internal_phy[port])
+		return;
+
+	p->phydev.speed = speed;
+
+	if (speed == SPEED_1000)
+		ksz_set_gbit(dev, port, true);
+
+	if (speed == SPEED_100 || speed == SPEED_10)
+		ksz_set_100_10mbit(dev, port, speed);
+
+	ksz_set_fullduplex(dev, port, duplex);
+
+	ksz_set_tx_pause(dev, port, tx_pause);
+
+	ksz_set_rx_pause(dev, port, rx_pause);
 
 	if (dev->dev_ops->phylink_mac_link_up)
 		dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface,
diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
index 851ee50895a4..db836b376341 100644
--- a/drivers/net/dsa/microchip/ksz_common.h
+++ b/drivers/net/dsa/microchip/ksz_common.h
@@ -311,10 +311,6 @@ void ksz_r_mib_stats64(struct ksz_device *dev, int port);
 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
 bool ksz_get_gbit(struct ksz_device *dev, int port);
 void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit);
-void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed);
-void ksz_set_fullduplex(struct ksz_device *dev, int port, bool val);
-void ksz_set_tx_pause(struct ksz_device *dev, int port, bool val);
-void ksz_set_rx_pause(struct ksz_device *dev, int port, bool val);
 extern const struct ksz_chip_data ksz_switch_chips[];
 
 /* Common register access functions */
diff --git a/drivers/net/dsa/microchip/lan937x.h b/drivers/net/dsa/microchip/lan937x.h
index 72ba9cb2fbc6..0ae553a9b9af 100644
--- a/drivers/net/dsa/microchip/lan937x.h
+++ b/drivers/net/dsa/microchip/lan937x.h
@@ -17,10 +17,6 @@ void lan937x_w_phy(struct ksz_device *dev, u16 addr, u16 reg, u16 val);
 int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu);
 void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
 			      struct phylink_config *config);
-void lan937x_phylink_mac_link_up(struct ksz_device *dev, int port,
-				 unsigned int mode, phy_interface_t interface,
-				 struct phy_device *phydev, int speed,
-				 int duplex, bool tx_pause, bool rx_pause);
 void lan937x_phylink_mac_config(struct ksz_device *dev, int port,
 				unsigned int mode,
 				const struct phylink_link_state *state);
diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
index 67b03ab0ede3..a2e648eacd19 100644
--- a/drivers/net/dsa/microchip/lan937x_main.c
+++ b/drivers/net/dsa/microchip/lan937x_main.c
@@ -345,24 +345,6 @@ static void lan937x_mac_config(struct ksz_device *dev, int port,
 	ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8);
 }
 
-static void lan937x_config_interface(struct ksz_device *dev, int port,
-				     int speed, int duplex,
-				     bool tx_pause, bool rx_pause)
-{
-	if (speed == SPEED_1000)
-		ksz_set_gbit(dev, port, true);
-
-	if (speed == SPEED_100 || speed == SPEED_10)
-		ksz_set_100_10mbit(dev, port, speed);
-
-	ksz_set_fullduplex(dev, port, duplex);
-
-	ksz_set_tx_pause(dev, port, tx_pause);
-
-	ksz_set_rx_pause(dev, port, rx_pause);
-
-}
-
 void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
 			      struct phylink_config *config)
 {
@@ -375,19 +357,6 @@ void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
 	}
 }
 
-void lan937x_phylink_mac_link_up(struct ksz_device *dev, int port,
-				 unsigned int mode, phy_interface_t interface,
-				 struct phy_device *phydev, int speed,
-				 int duplex, bool tx_pause, bool rx_pause)
-{
-	/* Internal PHYs */
-	if (dev->info->internal_phy[port])
-		return;
-
-	lan937x_config_interface(dev, port, speed, duplex,
-				 tx_pause, rx_pause);
-}
-
 void lan937x_phylink_mac_config(struct ksz_device *dev, int port,
 				unsigned int mode,
 				const struct phylink_link_state *state)
-- 
2.36.1

[RFC Patch net-next 06/10] net: dsa: microchip: lan937x: add support for configuing xMII register

[Arun Ramadoss]

This patch add the common ksz_set_xmii function for ksz series switch
and update the lan937x code phylink mac config. The register address for
the ksz8795 is Port 5 Interface control 6 and for all other switch is
xMII Control 1.
The bit value for selecting the interface is same for
KSZ8795 and KSZ9893 are same. The bit values for KSZ9477 and lan973x are
same. So, this patch add the bit value for each switches in
ksz_chip_data and configure the registers based on the chip id.

Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
---
 drivers/net/dsa/microchip/ksz_common.c   | 57 ++++++++++++++++++++++++
 drivers/net/dsa/microchip/ksz_common.h   |  8 ++++
 drivers/net/dsa/microchip/lan937x_main.c | 32 +------------
 drivers/net/dsa/microchip/lan937x_reg.h  |  9 ----
 4 files changed, 66 insertions(+), 40 deletions(-)

diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index 0cb711fcf046..649da4c361c1 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -284,6 +284,10 @@ static const u32 ksz8795_masks[] = {
 };
 
 static const u8 ksz8795_values[] = {
+	[P_RGMII_SEL]			= 3,
+	[P_GMII_SEL]			= 2,
+	[P_RMII_SEL]			= 1,
+	[P_MII_SEL]			= 0,
 	[P_MII_1GBIT]			= 1,
 	[P_MII_NOT_1GBIT]		= 0,
 	[P_MII_100MBIT]			= 0,
@@ -378,6 +382,10 @@ static const u8 ksz9477_shifts[] = {
 };
 
 static const u8 ksz9477_values[] = {
+	[P_RGMII_SEL]			= 0,
+	[P_RMII_SEL]			= 1,
+	[P_GMII_SEL]			= 2,
+	[P_MII_SEL]			= 3,
 	[P_MII_1GBIT]			= 0,
 	[P_MII_NOT_1GBIT]		= 1,
 	[P_MII_100MBIT]			= 1,
@@ -387,6 +395,10 @@ static const u8 ksz9477_values[] = {
 };
 
 static const u8 ksz9893_values[] = {
+	[P_RGMII_SEL]			= 3,
+	[P_GMII_SEL]			= 2,
+	[P_RMII_SEL]			= 1,
+	[P_MII_SEL]			= 0,
 	[P_MII_1GBIT]			= 1,
 	[P_MII_NOT_1GBIT]		= 0,
 	[P_MII_100MBIT]			= 1,
@@ -1390,6 +1402,51 @@ static int ksz_max_mtu(struct dsa_switch *ds, int port)
 	return dev->dev_ops->max_mtu(dev, port);
 }
 
+void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface)
+{
+	const u8 *bitval = dev->info->bitval;
+	const u16 *regs = dev->info->regs;
+	u8 data8;
+
+	ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
+
+	data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |
+		   P_RGMII_ID_EG_ENABLE);
+
+	switch (interface) {
+	case PHY_INTERFACE_MODE_MII:
+		data8 |= bitval[P_MII_SEL];
+		break;
+	case PHY_INTERFACE_MODE_RMII:
+		data8 |= bitval[P_RMII_SEL];
+		break;
+	case PHY_INTERFACE_MODE_GMII:
+		data8 |= bitval[P_GMII_SEL];
+		break;
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+		data8 |= bitval[P_RGMII_SEL];
+		break;
+	default:
+		dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
+			phy_modes(interface), port);
+		return;
+	}
+
+	if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
+	    interface == PHY_INTERFACE_MODE_RGMII_RXID)
+		data8 |= P_RGMII_ID_IG_ENABLE;
+
+	if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
+	    interface == PHY_INTERFACE_MODE_RGMII_TXID)
+		data8 |= P_RGMII_ID_EG_ENABLE;
+
+	/* Write the updated value */
+	ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
+}
+
 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port,
 				   unsigned int mode,
 				   const struct phylink_link_state *state)
diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
index db836b376341..90f3ec9ddaec 100644
--- a/drivers/net/dsa/microchip/ksz_common.h
+++ b/drivers/net/dsa/microchip/ksz_common.h
@@ -216,6 +216,10 @@ enum ksz_shifts {
 };
 
 enum ksz_values {
+	P_RGMII_SEL,
+	P_RMII_SEL,
+	P_GMII_SEL,
+	P_MII_SEL,
 	P_MII_1GBIT,
 	P_MII_NOT_1GBIT,
 	P_MII_100MBIT,
@@ -311,6 +315,7 @@ void ksz_r_mib_stats64(struct ksz_device *dev, int port);
 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
 bool ksz_get_gbit(struct ksz_device *dev, int port);
 void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit);
+void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface);
 extern const struct ksz_chip_data ksz_switch_chips[];
 
 /* Common register access functions */
@@ -479,6 +484,9 @@ static inline int is_lan937x(struct ksz_device *dev)
 #define P_MII_100MBIT_M			BIT(4)
 
 #define P_MII_1GBIT_M			BIT(6)
+#define P_RGMII_ID_IG_ENABLE		BIT(4)
+#define P_RGMII_ID_EG_ENABLE		BIT(3)
+#define P_MII_SEL_M			0x3
 
 /* Regmap tables generation */
 #define KSZ_SPI_OP_RD		3
diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
index a2e648eacd19..d86ffdf976b0 100644
--- a/drivers/net/dsa/microchip/lan937x_main.c
+++ b/drivers/net/dsa/microchip/lan937x_main.c
@@ -315,36 +315,6 @@ int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu)
 	return 0;
 }
 
-static void lan937x_mac_config(struct ksz_device *dev, int port,
-			       phy_interface_t interface)
-{
-	u8 data8;
-
-	ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
-
-	/* clear MII selection & set it based on interface later */
-	data8 &= ~PORT_MII_SEL_M;
-
-	/* configure MAC based on interface */
-	switch (interface) {
-	case PHY_INTERFACE_MODE_MII:
-		ksz_set_gbit(dev, port, false);
-		data8 |= PORT_MII_SEL;
-		break;
-	case PHY_INTERFACE_MODE_RMII:
-		ksz_set_gbit(dev, port, false);
-		data8 |= PORT_RMII_SEL;
-		break;
-	default:
-		dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
-			phy_modes(interface), port);
-		return;
-	}
-
-	/* Write the updated value */
-	ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8);
-}
-
 void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
 			      struct phylink_config *config)
 {
@@ -370,7 +340,7 @@ void lan937x_phylink_mac_config(struct ksz_device *dev, int port,
 		return;
 	}
 
-	lan937x_mac_config(dev, port, state->interface);
+	ksz_set_xmii(dev, port, state->interface);
 }
 
 int lan937x_setup(struct dsa_switch *ds)
diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h
index d5eb6dc3a739..a6cb3ca22dc3 100644
--- a/drivers/net/dsa/microchip/lan937x_reg.h
+++ b/drivers/net/dsa/microchip/lan937x_reg.h
@@ -131,19 +131,10 @@
 #define REG_PORT_T1_PHY_CTRL_BASE	0x0100
 
 /* 3 - xMII */
-#define REG_PORT_XMII_CTRL_0		0x0300
 #define PORT_SGMII_SEL			BIT(7)
 #define PORT_GRXC_ENABLE		BIT(0)
 
-#define REG_PORT_XMII_CTRL_1		0x0301
 #define PORT_MII_SEL_EDGE		BIT(5)
-#define PORT_RGMII_ID_IG_ENABLE		BIT(4)
-#define PORT_RGMII_ID_EG_ENABLE		BIT(3)
-#define PORT_MII_MAC_MODE		BIT(2)
-#define PORT_MII_SEL_M			0x3
-#define PORT_RGMII_SEL			0x0
-#define PORT_RMII_SEL			0x1
-#define PORT_MII_SEL			0x2
 
 /* 4 - MAC */
 #define REG_PORT_MAC_CTRL_0		0x0400
-- 
2.36.1

Re: [RFC Patch net-next 06/10] net: dsa: microchip: lan937x: add support for configuing xMII register

[Vladimir Oltean]

On Tue, Jul 12, 2022 at 09:33:04PM +0530, Arun Ramadoss wrote:
> This patch add the common ksz_set_xmii function for ksz series switch
> and update the lan937x code phylink mac config. The register address for
> the ksz8795 is Port 5 Interface control 6 and for all other switch is
> xMII Control 1.
> The bit value for selecting the interface is same for
> KSZ8795 and KSZ9893 are same. The bit values for KSZ9477 and lan973x are
> same. So, this patch add the bit value for each switches in
> ksz_chip_data and configure the registers based on the chip id.
> 
> Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
> ---
>  drivers/net/dsa/microchip/ksz_common.c   | 57 ++++++++++++++++++++++++
>  drivers/net/dsa/microchip/ksz_common.h   |  8 ++++
>  drivers/net/dsa/microchip/lan937x_main.c | 32 +------------
>  drivers/net/dsa/microchip/lan937x_reg.h  |  9 ----
>  4 files changed, 66 insertions(+), 40 deletions(-)
> 
> diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
> index 0cb711fcf046..649da4c361c1 100644
> --- a/drivers/net/dsa/microchip/ksz_common.c
> +++ b/drivers/net/dsa/microchip/ksz_common.c
> @@ -284,6 +284,10 @@ static const u32 ksz8795_masks[] = {
>  };
>  
>  static const u8 ksz8795_values[] = {
> +	[P_RGMII_SEL]			= 3,
> +	[P_GMII_SEL]			= 2,
> +	[P_RMII_SEL]			= 1,
> +	[P_MII_SEL]			= 0,
>  	[P_MII_1GBIT]			= 1,
>  	[P_MII_NOT_1GBIT]		= 0,
>  	[P_MII_100MBIT]			= 0,
> @@ -378,6 +382,10 @@ static const u8 ksz9477_shifts[] = {
>  };
>  
>  static const u8 ksz9477_values[] = {
> +	[P_RGMII_SEL]			= 0,
> +	[P_RMII_SEL]			= 1,
> +	[P_GMII_SEL]			= 2,
> +	[P_MII_SEL]			= 3,
>  	[P_MII_1GBIT]			= 0,
>  	[P_MII_NOT_1GBIT]		= 1,
>  	[P_MII_100MBIT]			= 1,
> @@ -387,6 +395,10 @@ static const u8 ksz9477_values[] = {
>  };
>  
>  static const u8 ksz9893_values[] = {
> +	[P_RGMII_SEL]			= 3,
> +	[P_GMII_SEL]			= 2,
> +	[P_RMII_SEL]			= 1,
> +	[P_MII_SEL]			= 0,
>  	[P_MII_1GBIT]			= 1,
>  	[P_MII_NOT_1GBIT]		= 0,
>  	[P_MII_100MBIT]			= 1,
> @@ -1390,6 +1402,51 @@ static int ksz_max_mtu(struct dsa_switch *ds, int port)
>  	return dev->dev_ops->max_mtu(dev, port);
>  }
>  
> +void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface)
> +{
> +	const u8 *bitval = dev->info->bitval;
> +	const u16 *regs = dev->info->regs;
> +	u8 data8;
> +
> +	ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
> +
> +	data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |
> +		   P_RGMII_ID_EG_ENABLE);
> +
> +	switch (interface) {
> +	case PHY_INTERFACE_MODE_MII:
> +		data8 |= bitval[P_MII_SEL];
> +		break;
> +	case PHY_INTERFACE_MODE_RMII:
> +		data8 |= bitval[P_RMII_SEL];
> +		break;
> +	case PHY_INTERFACE_MODE_GMII:
> +		data8 |= bitval[P_GMII_SEL];
> +		break;
> +	case PHY_INTERFACE_MODE_RGMII:
> +	case PHY_INTERFACE_MODE_RGMII_ID:
> +	case PHY_INTERFACE_MODE_RGMII_TXID:
> +	case PHY_INTERFACE_MODE_RGMII_RXID:
> +		data8 |= bitval[P_RGMII_SEL];
> +		break;
> +	default:
> +		dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
> +			phy_modes(interface), port);
> +		return;
> +	}
> +
> +	if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
> +	    interface == PHY_INTERFACE_MODE_RGMII_RXID)
> +		data8 |= P_RGMII_ID_IG_ENABLE;
> +
> +	if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
> +	    interface == PHY_INTERFACE_MODE_RGMII_TXID)
> +		data8 |= P_RGMII_ID_EG_ENABLE;

I'm confused to see RGMII delay handling both in ksz_set_xmii() and in
lan937x_phylink_mac_config(), called immediately afterwards via
dev->dev_ops->phylink_mac_config(). Can you explain the differences
between P_RGMII_ID_IG_ENABLE in regs[P_XMII_CTRL_1] and RGMII_1_RX_DELAY_2NS
in REG_PORT_XMII_CTRL_4?

> +
> +	/* Write the updated value */
> +	ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
> +}
> +
>  static void ksz_phylink_mac_config(struct dsa_switch *ds, int port,
>  				   unsigned int mode,
>  				   const struct phylink_link_state *state)
> diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
> index db836b376341..90f3ec9ddaec 100644
> --- a/drivers/net/dsa/microchip/ksz_common.h
> +++ b/drivers/net/dsa/microchip/ksz_common.h
> @@ -216,6 +216,10 @@ enum ksz_shifts {
>  };
>  
>  enum ksz_values {
> +	P_RGMII_SEL,
> +	P_RMII_SEL,
> +	P_GMII_SEL,
> +	P_MII_SEL,
>  	P_MII_1GBIT,
>  	P_MII_NOT_1GBIT,
>  	P_MII_100MBIT,
> @@ -311,6 +315,7 @@ void ksz_r_mib_stats64(struct ksz_device *dev, int port);
>  void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
>  bool ksz_get_gbit(struct ksz_device *dev, int port);
>  void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit);
> +void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface);
>  extern const struct ksz_chip_data ksz_switch_chips[];
>  
>  /* Common register access functions */
> @@ -479,6 +484,9 @@ static inline int is_lan937x(struct ksz_device *dev)
>  #define P_MII_100MBIT_M			BIT(4)
>  
>  #define P_MII_1GBIT_M			BIT(6)
> +#define P_RGMII_ID_IG_ENABLE		BIT(4)
> +#define P_RGMII_ID_EG_ENABLE		BIT(3)
> +#define P_MII_SEL_M			0x3
>  
>  /* Regmap tables generation */
>  #define KSZ_SPI_OP_RD		3
> diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
> index a2e648eacd19..d86ffdf976b0 100644
> --- a/drivers/net/dsa/microchip/lan937x_main.c
> +++ b/drivers/net/dsa/microchip/lan937x_main.c
> @@ -315,36 +315,6 @@ int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu)
>  	return 0;
>  }
>  
> -static void lan937x_mac_config(struct ksz_device *dev, int port,
> -			       phy_interface_t interface)
> -{
> -	u8 data8;
> -
> -	ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
> -
> -	/* clear MII selection & set it based on interface later */
> -	data8 &= ~PORT_MII_SEL_M;
> -
> -	/* configure MAC based on interface */
> -	switch (interface) {
> -	case PHY_INTERFACE_MODE_MII:
> -		ksz_set_gbit(dev, port, false);
> -		data8 |= PORT_MII_SEL;
> -		break;
> -	case PHY_INTERFACE_MODE_RMII:
> -		ksz_set_gbit(dev, port, false);
> -		data8 |= PORT_RMII_SEL;
> -		break;
> -	default:
> -		dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
> -			phy_modes(interface), port);
> -		return;
> -	}
> -
> -	/* Write the updated value */
> -	ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8);
> -}
> -
>  void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
>  			      struct phylink_config *config)
>  {
> @@ -370,7 +340,7 @@ void lan937x_phylink_mac_config(struct ksz_device *dev, int port,
>  		return;
>  	}
>  
> -	lan937x_mac_config(dev, port, state->interface);
> +	ksz_set_xmii(dev, port, state->interface);
>  }
>  
>  int lan937x_setup(struct dsa_switch *ds)
> diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h
> index d5eb6dc3a739..a6cb3ca22dc3 100644
> --- a/drivers/net/dsa/microchip/lan937x_reg.h
> +++ b/drivers/net/dsa/microchip/lan937x_reg.h
> @@ -131,19 +131,10 @@
>  #define REG_PORT_T1_PHY_CTRL_BASE	0x0100
>  
>  /* 3 - xMII */
> -#define REG_PORT_XMII_CTRL_0		0x0300
>  #define PORT_SGMII_SEL			BIT(7)
>  #define PORT_GRXC_ENABLE		BIT(0)
>  
> -#define REG_PORT_XMII_CTRL_1		0x0301
>  #define PORT_MII_SEL_EDGE		BIT(5)
> -#define PORT_RGMII_ID_IG_ENABLE		BIT(4)
> -#define PORT_RGMII_ID_EG_ENABLE		BIT(3)
> -#define PORT_MII_MAC_MODE		BIT(2)
> -#define PORT_MII_SEL_M			0x3
> -#define PORT_RGMII_SEL			0x0
> -#define PORT_RMII_SEL			0x1
> -#define PORT_MII_SEL			0x2
>  
>  /* 4 - MAC */
>  #define REG_PORT_MAC_CTRL_0		0x0400
> -- 
> 2.36.1
> 

Re: [RFC Patch net-next 06/10] net: dsa: microchip: lan937x: add support for configuing xMII register

[Arun.Ramadoss]

Hi Vladimir,

On Tue, 2022-07-19 at 14:04 +0300, Vladimir Oltean wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> 
> On Tue, Jul 12, 2022 at 09:33:04PM +0530, Arun Ramadoss wrote:
> > This patch add the common ksz_set_xmii function for ksz series
> > switch
> > and update the lan937x code phylink mac config. The register
> > address for
> > the ksz8795 is Port 5 Interface control 6 and for all other switch
> > is
> > xMII Control 1.
> > The bit value for selecting the interface is same for
> > KSZ8795 and KSZ9893 are same. The bit values for KSZ9477 and
> > lan973x are
> > same. So, this patch add the bit value for each switches in
> > ksz_chip_data and configure the registers based on the chip id.
> > 
> > Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
> > ---
> >  drivers/net/dsa/microchip/ksz_common.c   | 57
> > ++++++++++++++++++++++++
> >  drivers/net/dsa/microchip/ksz_common.h   |  8 ++++
> >  drivers/net/dsa/microchip/lan937x_main.c | 32 +------------
> >  drivers/net/dsa/microchip/lan937x_reg.h  |  9 ----
> >  4 files changed, 66 insertions(+), 40 deletions(-)
> > 
> > diff --git a/drivers/net/dsa/microchip/ksz_common.c
> > b/drivers/net/dsa/microchip/ksz_common.c
> > index 0cb711fcf046..649da4c361c1 100644
> > --- a/drivers/net/dsa/microchip/ksz_common.c
> > +++ b/drivers/net/dsa/microchip/ksz_common.c
> > @@ -284,6 +284,10 @@ static const u32 ksz8795_masks[] = {
> >  };
> > 
> > 
> >  +void ksz_set_xmii(struct ksz_device *dev, int port,
> > phy_interface_t interface)
> > +{
> > +     const u8 *bitval = dev->info->bitval;
> > +     const u16 *regs = dev->info->regs;
> > +     u8 data8;
> > +
> > +     ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
> > +
> > +     data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |
> > +                P_RGMII_ID_EG_ENABLE);
> > +
> > +     switch (interface) {
> > +     case PHY_INTERFACE_MODE_MII:
> > +             data8 |= bitval[P_MII_SEL];
> > +             break;
> > +     case PHY_INTERFACE_MODE_RMII:
> > +             data8 |= bitval[P_RMII_SEL];
> > +             break;
> > +     case PHY_INTERFACE_MODE_GMII:
> > +             data8 |= bitval[P_GMII_SEL];
> > +             break;
> > +     case PHY_INTERFACE_MODE_RGMII:
> > +     case PHY_INTERFACE_MODE_RGMII_ID:
> > +     case PHY_INTERFACE_MODE_RGMII_TXID:
> > +     case PHY_INTERFACE_MODE_RGMII_RXID:
> > +             data8 |= bitval[P_RGMII_SEL];
> > +             break;
> > +     default:
> > +             dev_err(dev->dev, "Unsupported interface '%s' for
> > port %d\n",
> > +                     phy_modes(interface), port);
> > +             return;
> > +     }
> > +
> > +     if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
> > +         interface == PHY_INTERFACE_MODE_RGMII_RXID)
> > +             data8 |= P_RGMII_ID_IG_ENABLE;
> > +
> > +     if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
> > +         interface == PHY_INTERFACE_MODE_RGMII_TXID)
> > +             data8 |= P_RGMII_ID_EG_ENABLE;
> 
> I'm confused to see RGMII delay handling both in ksz_set_xmii() and
> in
> lan937x_phylink_mac_config(), called immediately afterwards via
> dev->dev_ops->phylink_mac_config(). Can you explain the differences
> between P_RGMII_ID_IG_ENABLE in regs[P_XMII_CTRL_1] and
> RGMII_1_RX_DELAY_2NS
> in REG_PORT_XMII_CTRL_4?

In lan937x RGMII delays are managed by dll register which is not
supported in other ksz switches. REG_PORT_XMII_CTRL_4 and CTRL_5 are
controlled by the P_RGMII_ID_IG_ENABLE & P_RGMII_ID_EG_ENABLE bit. So I
have moved the generic portion of implementation in ksz_set_xmii and
product specific implementation through phylink_mac_config hooks.

> 
> > +
> > +     /* Write the updated value */
> > +     ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
> > +}
> > +
> >  static void ksz_phylink_mac_config(struct dsa_switch *ds, int
> > port,
> >                                  unsigned int mode,
> >                                  const struct phylink_link_state
> > *state)
> > diff --git a/drivers/net/dsa/microchip/ksz_common.h
> > b/drivers/net/dsa/microchip/ksz_common.h
> > index db836b376341..90f3ec9ddaec 100644
> > --- a/drivers/net/dsa/microchip/ksz_common.h
> > +++ b/drivers/net/dsa/microchip/ksz_common.h
> > @@ -216,6 +216,10 @@ enum ksz_shifts {
> >  };
> > 
> > --
> > 2.36.1
> > 
> 
> 

[RFC Patch net-next 07/10] net: dsa: microchip: apply rgmii tx and rx delay in phylink mac config

[Arun Ramadoss]

This patch apply the rgmii delay to the xmii tune adjust register based
on the interface selected in phylink mac config. There are two rgmii
port in LAN937x and value to be loaded in the register vary depends on
the port selected.

Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
---
 drivers/net/dsa/microchip/lan937x_main.c | 61 ++++++++++++++++++++++++
 drivers/net/dsa/microchip/lan937x_reg.h  | 18 +++++++
 2 files changed, 79 insertions(+)

diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
index d86ffdf976b0..db88ea567ba6 100644
--- a/drivers/net/dsa/microchip/lan937x_main.c
+++ b/drivers/net/dsa/microchip/lan937x_main.c
@@ -315,6 +315,45 @@ int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu)
 	return 0;
 }
 
+static void lan937x_set_tune_adj(struct ksz_device *dev, int port,
+				 u16 reg, u8 val)
+{
+	u16 data16;
+
+	ksz_pread16(dev, port, reg, &data16);
+
+	/* Update tune Adjust */
+	data16 |= FIELD_PREP(PORT_TUNE_ADJ, val);
+	ksz_pwrite16(dev, port, reg, data16);
+
+	/* write DLL reset to take effect */
+	data16 |= PORT_DLL_RESET;
+	ksz_pwrite16(dev, port, reg, data16);
+}
+
+static void lan937x_set_rgmii_tx_delay(struct ksz_device *dev, int port)
+{
+	u8 val;
+
+	/* Apply different codes based on the ports as per characterization
+	 * results
+	 */
+	val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_TX_DELAY_2NS :
+		RGMII_2_TX_DELAY_2NS;
+
+	lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_5, val);
+}
+
+static void lan937x_set_rgmii_rx_delay(struct ksz_device *dev, int port)
+{
+	u8 val;
+
+	val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_RX_DELAY_2NS :
+		RGMII_2_RX_DELAY_2NS;
+
+	lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_4, val);
+}
+
 void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
 			      struct phylink_config *config)
 {
@@ -331,6 +370,9 @@ void lan937x_phylink_mac_config(struct ksz_device *dev, int port,
 				unsigned int mode,
 				const struct phylink_link_state *state)
 {
+	phy_interface_t interface = state->interface;
+	struct ksz_port *p = &dev->ports[port];
+
 	/* Internal PHYs */
 	if (dev->info->internal_phy[port])
 		return;
@@ -341,6 +383,25 @@ void lan937x_phylink_mac_config(struct ksz_device *dev, int port,
 	}
 
 	ksz_set_xmii(dev, port, state->interface);
+
+	/* if the delay is 0, do not enable DLL */
+	if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
+	    interface == PHY_INTERFACE_MODE_RGMII_RXID) {
+		if (p->rgmii_tx_val) {
+			lan937x_set_rgmii_tx_delay(dev, port);
+			dev_info(dev->dev, "Applied rgmii tx delay for the port %d\n",
+				 port);
+		}
+	}
+
+	if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
+	    interface == PHY_INTERFACE_MODE_RGMII_TXID) {
+		if (p->rgmii_rx_val) {
+			lan937x_set_rgmii_rx_delay(dev, port);
+			dev_info(dev->dev, "Applied rgmii rx delay for the port %d\n",
+				 port);
+		}
+	}
 }
 
 int lan937x_setup(struct dsa_switch *ds)
diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h
index a6cb3ca22dc3..ba4adaddb3ec 100644
--- a/drivers/net/dsa/microchip/lan937x_reg.h
+++ b/drivers/net/dsa/microchip/lan937x_reg.h
@@ -136,6 +136,12 @@
 
 #define PORT_MII_SEL_EDGE		BIT(5)
 
+#define REG_PORT_XMII_CTRL_4		0x0304
+#define REG_PORT_XMII_CTRL_5		0x0306
+
+#define PORT_DLL_RESET			BIT(15)
+#define PORT_TUNE_ADJ			GENMASK(13, 7)
+
 /* 4 - MAC */
 #define REG_PORT_MAC_CTRL_0		0x0400
 #define PORT_CHECK_LENGTH		BIT(2)
@@ -161,6 +167,18 @@
 
 #define P_PRIO_CTRL			REG_PORT_MRI_PRIO_CTRL
 
+/* The port number as per the datasheet */
+#define RGMII_2_PORT_NUM		5
+#define RGMII_1_PORT_NUM		6
+
+#define LAN937X_RGMII_2_PORT		(RGMII_2_PORT_NUM - 1)
+#define LAN937X_RGMII_1_PORT		(RGMII_1_PORT_NUM - 1)
+
+#define RGMII_1_TX_DELAY_2NS		2
+#define RGMII_2_TX_DELAY_2NS		0
+#define RGMII_1_RX_DELAY_2NS		0x1B
+#define RGMII_2_RX_DELAY_2NS		0x14
+
 #define LAN937X_TAG_LEN			2
 
 #endif
-- 
2.36.1

Re: [RFC Patch net-next 07/10] net: dsa: microchip: apply rgmii tx and rx delay in phylink mac config

[Vladimir Oltean]

On Tue, Jul 12, 2022 at 09:33:05PM +0530, Arun Ramadoss wrote:
> This patch apply the rgmii delay to the xmii tune adjust register based
> on the interface selected in phylink mac config. There are two rgmii
> port in LAN937x and value to be loaded in the register vary depends on
> the port selected.
> 
> Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
> ---
>  drivers/net/dsa/microchip/lan937x_main.c | 61 ++++++++++++++++++++++++
>  drivers/net/dsa/microchip/lan937x_reg.h  | 18 +++++++
>  2 files changed, 79 insertions(+)
> 
> diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
> index d86ffdf976b0..db88ea567ba6 100644
> --- a/drivers/net/dsa/microchip/lan937x_main.c
> +++ b/drivers/net/dsa/microchip/lan937x_main.c
> @@ -315,6 +315,45 @@ int lan937x_change_mtu(struct ksz_device *dev, int port, int new_mtu)
>  	return 0;
>  }
>  
> +static void lan937x_set_tune_adj(struct ksz_device *dev, int port,
> +				 u16 reg, u8 val)
> +{
> +	u16 data16;
> +
> +	ksz_pread16(dev, port, reg, &data16);
> +
> +	/* Update tune Adjust */
> +	data16 |= FIELD_PREP(PORT_TUNE_ADJ, val);
> +	ksz_pwrite16(dev, port, reg, data16);
> +
> +	/* write DLL reset to take effect */
> +	data16 |= PORT_DLL_RESET;
> +	ksz_pwrite16(dev, port, reg, data16);
> +}
> +
> +static void lan937x_set_rgmii_tx_delay(struct ksz_device *dev, int port)
> +{
> +	u8 val;
> +
> +	/* Apply different codes based on the ports as per characterization
> +	 * results
> +	 */

What characterization result are you referring to? Individual board
designers should do their own characterization, that's why they provide
a p->rgmii_tx_val in the device tree. The value provided there seems to
be ignored and unconditionally replaced with 2 ns here.

> +	val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_TX_DELAY_2NS :
> +		RGMII_2_TX_DELAY_2NS;
> +
> +	lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_5, val);
> +}
> +
> +static void lan937x_set_rgmii_rx_delay(struct ksz_device *dev, int port)
> +{
> +	u8 val;
> +
> +	val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_RX_DELAY_2NS :
> +		RGMII_2_RX_DELAY_2NS;
> +
> +	lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_4, val);
> +}
> +
>  void lan937x_phylink_get_caps(struct ksz_device *dev, int port,
>  			      struct phylink_config *config)
>  {
> @@ -331,6 +370,9 @@ void lan937x_phylink_mac_config(struct ksz_device *dev, int port,
>  				unsigned int mode,
>  				const struct phylink_link_state *state)
>  {
> +	phy_interface_t interface = state->interface;
> +	struct ksz_port *p = &dev->ports[port];
> +
>  	/* Internal PHYs */
>  	if (dev->info->internal_phy[port])
>  		return;
> @@ -341,6 +383,25 @@ void lan937x_phylink_mac_config(struct ksz_device *dev, int port,
>  	}
>  
>  	ksz_set_xmii(dev, port, state->interface);
> +
> +	/* if the delay is 0, do not enable DLL */
> +	if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
> +	    interface == PHY_INTERFACE_MODE_RGMII_RXID) {

Why not all RGMII modes and only these 2? There was a discussion a long
time ago that the "_*ID" values refer to delays applied by an attached PHY.
Here you are refusing to apply RGMII TX delays in the "rgmii" and "rgmii-txid"
modes.

> +		if (p->rgmii_tx_val) {
> +			lan937x_set_rgmii_tx_delay(dev, port);
> +			dev_info(dev->dev, "Applied rgmii tx delay for the port %d\n",
> +				 port);
> +		}
> +	}
> +
> +	if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
> +	    interface == PHY_INTERFACE_MODE_RGMII_TXID) {
> +		if (p->rgmii_rx_val) {
> +			lan937x_set_rgmii_rx_delay(dev, port);
> +			dev_info(dev->dev, "Applied rgmii rx delay for the port %d\n",
> +				 port);
> +		}
> +	}
>  }
>  

Re: [RFC Patch net-next 07/10] net: dsa: microchip: apply rgmii tx and rx delay in phylink mac config

[Arun.Ramadoss]

On Tue, 2022-07-19 at 13:25 +0300, Vladimir Oltean wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> 
> On Tue, Jul 12, 2022 at 09:33:05PM +0530, Arun Ramadoss wrote:
> > This patch apply the rgmii delay to the xmii tune adjust register
> > based
> > on the interface selected in phylink mac config. There are two
> > rgmii
> > port in LAN937x and value to be loaded in the register vary depends
> > on
> > the port selected.
> > 
> > Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
> > ---
> >  drivers/net/dsa/microchip/lan937x_main.c | 61
> > ++++++++++++++++++++++++
> >  drivers/net/dsa/microchip/lan937x_reg.h  | 18 +++++++
> >  2 files changed, 79 insertions(+)
> > 
> > diff --git a/drivers/net/dsa/microchip/lan937x_main.c
> > b/drivers/net/dsa/microchip/lan937x_main.c
> > index d86ffdf976b0..db88ea567ba6 100644
> > --- a/drivers/net/dsa/microchip/lan937x_main.c
> > +++ b/drivers/net/dsa/microchip/lan937x_main.c
> > @@ -315,6 +315,45 @@ int lan937x_change_mtu(struct ksz_device *dev,
> > int port, int new_mtu)
> >       return 0;
> >  }
> > 
> > +
> > +static void lan937x_set_rgmii_tx_delay(struct ksz_device *dev, int
> > port)
> > +{
> > +     u8 val;
> > +
> > +     /* Apply different codes based on the ports as per
> > characterization
> > +      * results
> > +      */
> 
> What characterization result are you referring to? Individual board
> designers should do their own characterization, that's why they
> provide
> a p->rgmii_tx_val in the device tree. The value provided there seems
> to
> be ignored and unconditionally replaced with 2 ns here.

This is the value we got from the post silicon validation team which
has to be programmed to dll register to get the proper delay. The value
is different for rgmii 1 and rgmii2.

> 
> > +     val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_TX_DELAY_2NS :
> > +             RGMII_2_TX_DELAY_2NS;
> > +
> > +     lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_5, val);
> > +}
> > +
> > +
> >  @@ -341,6 +383,25 @@ void lan937x_phylink_mac_config(struct
> > ksz_device *dev, int port,
> >       }
> > 
> >       ksz_set_xmii(dev, port, state->interface);
> > +
> > +     /* if the delay is 0, do not enable DLL */
> > +     if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
> > +         interface == PHY_INTERFACE_MODE_RGMII_RXID) {
> 
> Why not all RGMII modes and only these 2? There was a discussion a
> long
> time ago that the "_*ID" values refer to delays applied by an
> attached PHY.
> Here you are refusing to apply RGMII TX delays in the "rgmii" and
> "rgmii-txid"
> modes.

I have reused the code of ksz9477 cpu config function and added the dll
configuration for lan937x family alone. And understood that if device
tree specificies as rgmii_txid then apply the egress delay, for
rgmii_rxid apply ingress delay, for rgmii_id apply both.
From your comment, I am inferring that apply the mac delay for all the
rgmii interface "rgmii*".
Can you correct me if am I wrong and bit elaborate on it.

> 
> > +             if (p->rgmii_tx_val) {
> > +                     lan937x_set_rgmii_tx_delay(dev, port);
> > +                     dev_info(dev->dev, "Applied rgmii tx delay
> > for the port %d\n",
> > +                              port);
> > +             }
> > +     }
> > +
> > +     if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
> > +         interface == PHY_INTERFACE_MODE_RGMII_TXID) {
> > +             if (p->rgmii_rx_val) {
> > +                     lan937x_set_rgmii_rx_delay(dev, port);
> > +                     dev_info(dev->dev, "Applied rgmii rx delay
> > for the port %d\n",
> > +                              port);
> > +             }
> > +     }
> >  }
> > 

Re: [RFC Patch net-next 07/10] net: dsa: microchip: apply rgmii tx and rx delay in phylink mac config

[Vladimir Oltean]

On Wed, Jul 20, 2022 at 02:51:42PM +0000, Arun.Ramadoss@microchip.com wrote:
> > Why not all RGMII modes and only these 2? There was a discussion a long
> > time ago that the "_*ID" values refer to delays applied by an attached PHY.
> > Here you are refusing to apply RGMII TX delays in the "rgmii" and "rgmii-txid"
> > modes.
> 
> I have reused the code of ksz9477 cpu config function and added the dll
> configuration for lan937x family alone. And understood that if device
> tree specificies as rgmii_txid then apply the egress delay, for
> rgmii_rxid apply ingress delay, for rgmii_id apply both.
> From your comment, I am inferring that apply the mac delay for all the
> rgmii interface "rgmii*".
> Can you correct me if am I wrong and bit elaborate on it.

What we are trying is to interpret what's written in
Documentation/devicetree/bindings/net/ethernet-controller.yaml in a way
that is consistent, even though its wording makes it evident that that
it was written in simpler times.

There it says:

      # RX and TX delays are added by the MAC when required
      - rgmii

      # RGMII with internal RX and TX delays provided by the PHY,
      # the MAC should not add the RX or TX delays in this case
      - rgmii-id

      # RGMII with internal RX delay provided by the PHY, the MAC
      # should not add an RX delay in this case
      - rgmii-rxid

      # RGMII with internal TX delay provided by the PHY, the MAC
      # should not add an TX delay in this case
      - rgmii-txid

The fact that the PHY adds delays in the directions specified by the
phy-mode value is established behavior; yet the MAC's behavior is pretty
much subject to interpretation, and this has resulted in varying
implementations in drivers.

The wise words above say that "RX and TX delays are added by the MAC
when required" - ok but when are they required? Determining this is
impossible based on the phy-mode alone, since there aren't just 2
degrees of freedom who may add delays (the PHY and the MAC). There also
exists the possibility of using serpentine traces (PCB delays), which
practically speaking, can't be described in phy-mode because then, a
potential PHY on the same link would also think they're for itself to
apply.

So the modern interpretation of phy-mode is to say that it simply does
not describe whether a MAC should apply delays in a direction or another.

So a separate set of properties was introduced, "rx-internal-delay-ps"
and "tx-internal-delay-ps". These have the advantage of being located
under the OF node of the MAC, and under the OF node of the PHY respectively.
So it's clearer which side is supposed to configure which delays, and
you also have finer control over the clock skew.

Initially when Prasanna first tried to upstream the lan937x, we discusssed
that since it's a new driver, it should support the modern interpretation
of RGMII delays, and we agreed on that strategy.

Now, with your recent refactoring that makes all switches share the same
probing logic (and OF node parsing), things are in a bit of a greyer area.

For one thing, you seem to have involuntarily inherited support for dubious
legacy bindings, such as the "phy-mode under the switch node" that is
described by commit edecfa98f602 ("net: dsa: microchip: look for
phy-mode in port nodes").

For another, you've inherited the existing interpretation of RGMII
delays from the KSZ9477 driver, which is that the driver interprets the
"phy-mode" as if it's a PHY (when in fact it's a MAC).

The KSZ9477 isn't by far the only MAC driver that applies RGMII delays
based on the phy-mode string, however in the past we made an effort to
update existing DSA drivers to the modern interpretation, see commits:

9ca482a246f0 ("net: dsa: sja1105: parse {rx, tx}-internal-delay-ps properties for RGMII delays")
5654ec78dd7e ("net: dsa: qca8k: rework rgmii delay logic and scan for cpu port 6")

There is a possibility to have a transitioning scheme: if the
"rx-internal-delay-ps" or "tx-internal-delay-ps" properties are present
under the MAC OF node, apply delays based on those. Otherwise, apply
delays based on phy-mode, and warn.

I'd appreciate if you could consider updating the KSZ common driver to
this interpretation of RGMII delays, so that the modern interpretation
becomes more widespread, and there are fewer places from which to copy a
non-standard one.

[RFC Patch net-next 08/10] net: dsa: microchip: ksz9477: use common xmii function

[Arun Ramadoss]

In ksz9477.c file, configuring the xmii register is performed based on
the flag NEW_XMII. The flag is reset for ksz9893 switch and set for
other switch. This patch uses the ksz common xmii set and get function.
The bit values are configured based on the chip id.

Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
---
 drivers/net/dsa/microchip/ksz9477.c     | 153 +-----------------------
 drivers/net/dsa/microchip/ksz9477_reg.h |  18 ---
 drivers/net/dsa/microchip/ksz_common.c  |  38 +++++-
 drivers/net/dsa/microchip/ksz_common.h  |   7 +-
 4 files changed, 49 insertions(+), 167 deletions(-)

diff --git a/drivers/net/dsa/microchip/ksz9477.c b/drivers/net/dsa/microchip/ksz9477.c
index cfa7ddf60718..301283d1ba82 100644
--- a/drivers/net/dsa/microchip/ksz9477.c
+++ b/drivers/net/dsa/microchip/ksz9477.c
@@ -19,11 +19,6 @@
 #include "ksz_common.h"
 #include "ksz9477.h"
 
-/* Used with variable features to indicate capabilities. */
-#define GBIT_SUPPORT			BIT(0)
-#define NEW_XMII			BIT(1)
-#define IS_9893				BIT(2)
-
 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
 {
 	regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
@@ -866,116 +861,18 @@ void ksz9477_port_mirror_del(struct ksz_device *dev, int port,
 			     PORT_MIRROR_SNIFFER, false);
 }
 
-static int ksz9477_get_xmii(struct ksz_device *dev, u8 data)
-{
-	int mode;
-
-	if (dev->features & NEW_XMII) {
-		switch (data & PORT_MII_SEL_M) {
-		case PORT_MII_SEL:
-			mode = 0;
-			break;
-		case PORT_RMII_SEL:
-			mode = 1;
-			break;
-		case PORT_GMII_SEL:
-			mode = 2;
-			break;
-		default:
-			mode = 3;
-		}
-	} else {
-		switch (data & PORT_MII_SEL_M) {
-		case PORT_MII_SEL_S1:
-			mode = 0;
-			break;
-		case PORT_RMII_SEL_S1:
-			mode = 1;
-			break;
-		case PORT_GMII_SEL_S1:
-			mode = 2;
-			break;
-		default:
-			mode = 3;
-		}
-	}
-	return mode;
-}
-
-static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data)
-{
-	u8 xmii;
-
-	if (dev->features & NEW_XMII) {
-		switch (mode) {
-		case 0:
-			xmii = PORT_MII_SEL;
-			break;
-		case 1:
-			xmii = PORT_RMII_SEL;
-			break;
-		case 2:
-			xmii = PORT_GMII_SEL;
-			break;
-		default:
-			xmii = PORT_RGMII_SEL;
-			break;
-		}
-	} else {
-		switch (mode) {
-		case 0:
-			xmii = PORT_MII_SEL_S1;
-			break;
-		case 1:
-			xmii = PORT_RMII_SEL_S1;
-			break;
-		case 2:
-			xmii = PORT_GMII_SEL_S1;
-			break;
-		default:
-			xmii = PORT_RGMII_SEL_S1;
-			break;
-		}
-	}
-	*data &= ~PORT_MII_SEL_M;
-	*data |= xmii;
-}
-
 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port)
 {
 	phy_interface_t interface;
 	bool gbit;
-	int mode;
-	u8 data8;
 
 	if (port < dev->phy_port_cnt)
 		return PHY_INTERFACE_MODE_NA;
-	ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
+
 	gbit = ksz_get_gbit(dev, port);
-	mode = ksz9477_get_xmii(dev, data8);
-	switch (mode) {
-	case 2:
-		interface = PHY_INTERFACE_MODE_GMII;
-		if (gbit)
-			break;
-		fallthrough;
-	case 0:
-		interface = PHY_INTERFACE_MODE_MII;
-		break;
-	case 1:
-		interface = PHY_INTERFACE_MODE_RMII;
-		break;
-	default:
-		interface = PHY_INTERFACE_MODE_RGMII;
-		if (data8 & PORT_RGMII_ID_EG_ENABLE)
-			interface = PHY_INTERFACE_MODE_RGMII_TXID;
-		if (data8 & PORT_RGMII_ID_IG_ENABLE) {
-			interface = PHY_INTERFACE_MODE_RGMII_RXID;
-			if (data8 & PORT_RGMII_ID_EG_ENABLE)
-				interface = PHY_INTERFACE_MODE_RGMII_ID;
-		}
-		break;
-	}
+
+	interface = ksz_get_xmii(dev, port, gbit);
+
 	return interface;
 }
 
@@ -1049,8 +946,8 @@ void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
 {
 	struct ksz_port *p = &dev->ports[port];
 	struct dsa_switch *ds = dev->ds;
-	u8 data8, member;
 	u16 data16;
+	u8 member;
 
 	/* enable tag tail for host port */
 	if (cpu_port)
@@ -1092,42 +989,7 @@ void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
 			     true);
 
 		/* configure MAC to 1G & RGMII mode */
-		ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
-		switch (p->interface) {
-		case PHY_INTERFACE_MODE_MII:
-			ksz9477_set_xmii(dev, 0, &data8);
-			ksz_set_gbit(dev, port, false);
-			p->phydev.speed = SPEED_100;
-			break;
-		case PHY_INTERFACE_MODE_RMII:
-			ksz9477_set_xmii(dev, 1, &data8);
-			ksz_set_gbit(dev, port, false);
-			p->phydev.speed = SPEED_100;
-			break;
-		case PHY_INTERFACE_MODE_GMII:
-			ksz9477_set_xmii(dev, 2, &data8);
-			ksz_set_gbit(dev, port, true);
-			p->phydev.speed = SPEED_1000;
-			break;
-		default:
-			ksz9477_set_xmii(dev, 3, &data8);
-			ksz_set_gbit(dev, port, true);
-			data8 &= ~PORT_RGMII_ID_IG_ENABLE;
-			data8 &= ~PORT_RGMII_ID_EG_ENABLE;
-			if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
-			    p->interface == PHY_INTERFACE_MODE_RGMII_RXID)
-				data8 |= PORT_RGMII_ID_IG_ENABLE;
-			if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
-			    p->interface == PHY_INTERFACE_MODE_RGMII_TXID)
-				data8 |= PORT_RGMII_ID_EG_ENABLE;
-			/* On KSZ9893, disable RGMII in-band status support */
-			if (dev->features & IS_9893)
-				data8 &= ~PORT_MII_MAC_MODE;
-			p->phydev.speed = SPEED_1000;
-			break;
-		}
-		ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8);
-		p->phydev.duplex = 1;
+		ksz_set_xmii(dev, port, p->interface);
 	}
 
 	if (cpu_port)
@@ -1315,9 +1177,6 @@ int ksz9477_switch_init(struct ksz_device *dev)
 			dev->features &= ~GBIT_SUPPORT;
 		dev->phy_port_cnt = 2;
 	} else {
-		/* Chip uses new XMII register definitions. */
-		dev->features |= NEW_XMII;
-
 		/* Chip does not support gigabit. */
 		if (!(data8 & SW_GIGABIT_ABLE))
 			dev->features &= ~GBIT_SUPPORT;
diff --git a/drivers/net/dsa/microchip/ksz9477_reg.h b/drivers/net/dsa/microchip/ksz9477_reg.h
index 6ca859345932..ddf99d1e4bbd 100644
--- a/drivers/net/dsa/microchip/ksz9477_reg.h
+++ b/drivers/net/dsa/microchip/ksz9477_reg.h
@@ -1175,29 +1175,11 @@
 #define PORT_LINK_STATUS_FAIL		BIT(0)
 
 /* 3 - xMII */
-#define REG_PORT_XMII_CTRL_0		0x0300
-
 #define PORT_SGMII_SEL			BIT(7)
 #define PORT_GRXC_ENABLE		BIT(0)
 
-#define REG_PORT_XMII_CTRL_1		0x0301
-
 #define PORT_RMII_CLK_SEL		BIT(7)
 #define PORT_MII_SEL_EDGE		BIT(5)
-#define PORT_RGMII_ID_IG_ENABLE		BIT(4)
-#define PORT_RGMII_ID_EG_ENABLE		BIT(3)
-#define PORT_MII_MAC_MODE		BIT(2)
-#define PORT_MII_SEL_M			0x3
-/* S1 */
-#define PORT_MII_SEL_S1			0x0
-#define PORT_RMII_SEL_S1		0x1
-#define PORT_GMII_SEL_S1		0x2
-#define PORT_RGMII_SEL_S1		0x3
-/* S2 */
-#define PORT_RGMII_SEL			0x0
-#define PORT_RMII_SEL			0x1
-#define PORT_GMII_SEL			0x2
-#define PORT_MII_SEL			0x3
 
 /* 4 - MAC */
 #define REG_PORT_MAC_CTRL_0		0x0400
diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index 649da4c361c1..43c85ff8be5f 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -1428,6 +1428,9 @@ void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface)
 	case PHY_INTERFACE_MODE_RGMII_TXID:
 	case PHY_INTERFACE_MODE_RGMII_RXID:
 		data8 |= bitval[P_RGMII_SEL];
+		/* On KSZ9893, disable RGMII in-band status support */
+		if (dev->features & IS_9893)
+			data8 &= ~P_MII_MAC_MODE;
 		break;
 	default:
 		dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
@@ -1447,6 +1450,39 @@ void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface)
 	ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
 }
 
+phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit)
+{
+	const u8 *bitval = dev->info->bitval;
+	const u16 *regs = dev->info->regs;
+	phy_interface_t interface;
+	u8 data8;
+	u8 val;
+
+	ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
+
+	val = FIELD_GET(P_MII_SEL_M, data8);
+
+	if (val == bitval[P_MII_SEL]) {
+		if (gbit)
+			interface = PHY_INTERFACE_MODE_GMII;
+		else
+			interface = PHY_INTERFACE_MODE_MII;
+	} else if (val == bitval[P_RMII_SEL]) {
+		interface = PHY_INTERFACE_MODE_RGMII;
+	} else {
+		interface = PHY_INTERFACE_MODE_RGMII;
+		if (data8 & P_RGMII_ID_EG_ENABLE)
+			interface = PHY_INTERFACE_MODE_RGMII_TXID;
+		if (data8 & P_RGMII_ID_IG_ENABLE) {
+			interface = PHY_INTERFACE_MODE_RGMII_RXID;
+			if (data8 & P_RGMII_ID_EG_ENABLE)
+				interface = PHY_INTERFACE_MODE_RGMII_ID;
+		}
+	}
+
+	return interface;
+}
+
 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port,
 				   unsigned int mode,
 				   const struct phylink_link_state *state)
@@ -1475,7 +1511,7 @@ bool ksz_get_gbit(struct ksz_device *dev, int port)
 	return gbit;
 }
 
-void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
+static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
 {
 	const u8 *bitval = dev->info->bitval;
 	const u16 *regs = dev->info->regs;
diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
index 90f3ec9ddaec..364e5859139d 100644
--- a/drivers/net/dsa/microchip/ksz_common.h
+++ b/drivers/net/dsa/microchip/ksz_common.h
@@ -314,8 +314,8 @@ void ksz_init_mib_timer(struct ksz_device *dev);
 void ksz_r_mib_stats64(struct ksz_device *dev, int port);
 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
 bool ksz_get_gbit(struct ksz_device *dev, int port);
-void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit);
 void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface);
+phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit);
 extern const struct ksz_chip_data ksz_switch_chips[];
 
 /* Common register access functions */
@@ -479,6 +479,10 @@ static inline int is_lan937x(struct ksz_device *dev)
 
 #define SW_START			0x01
 
+/* Used with variable features to indicate capabilities. */
+#define GBIT_SUPPORT			BIT(0)
+#define IS_9893				BIT(2)
+
 /* xMII configuration */
 #define P_MII_DUPLEX_M			BIT(6)
 #define P_MII_100MBIT_M			BIT(4)
@@ -486,6 +490,7 @@ static inline int is_lan937x(struct ksz_device *dev)
 #define P_MII_1GBIT_M			BIT(6)
 #define P_RGMII_ID_IG_ENABLE		BIT(4)
 #define P_RGMII_ID_EG_ENABLE		BIT(3)
+#define P_MII_MAC_MODE			BIT(2)
 #define P_MII_SEL_M			0x3
 
 /* Regmap tables generation */
-- 
2.36.1

[RFC Patch net-next 09/10] net: dsa: microchip: ksz8795: use common xmii function

[Arun Ramadoss]

This patch updates the ksz8795 cpu configuration to use the ksz common
xmii set functions.

Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
---
 drivers/net/dsa/microchip/ksz8795.c     | 35 +------------------------
 drivers/net/dsa/microchip/ksz8795_reg.h |  8 ------
 2 files changed, 1 insertion(+), 42 deletions(-)

diff --git a/drivers/net/dsa/microchip/ksz8795.c b/drivers/net/dsa/microchip/ksz8795.c
index 911aace42284..8f807d8eace5 100644
--- a/drivers/net/dsa/microchip/ksz8795.c
+++ b/drivers/net/dsa/microchip/ksz8795.c
@@ -1116,7 +1116,6 @@ void ksz8_port_mirror_del(struct ksz_device *dev, int port,
 static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port)
 {
 	struct ksz_port *p = &dev->ports[port];
-	u8 data8;
 
 	if (!p->interface && dev->compat_interface) {
 		dev_warn(dev->dev,
@@ -1126,39 +1125,7 @@ static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port)
 		p->interface = dev->compat_interface;
 	}
 
-	/* Configure MII interface for proper network communication. */
-	ksz_read8(dev, REG_PORT_5_CTRL_6, &data8);
-	data8 &= ~PORT_INTERFACE_TYPE;
-	data8 &= ~PORT_GMII_1GPS_MODE;
-	switch (p->interface) {
-	case PHY_INTERFACE_MODE_MII:
-		p->phydev.speed = SPEED_100;
-		break;
-	case PHY_INTERFACE_MODE_RMII:
-		data8 |= PORT_INTERFACE_RMII;
-		p->phydev.speed = SPEED_100;
-		break;
-	case PHY_INTERFACE_MODE_GMII:
-		data8 |= PORT_GMII_1GPS_MODE;
-		data8 |= PORT_INTERFACE_GMII;
-		p->phydev.speed = SPEED_1000;
-		break;
-	default:
-		data8 &= ~PORT_RGMII_ID_IN_ENABLE;
-		data8 &= ~PORT_RGMII_ID_OUT_ENABLE;
-		if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
-		    p->interface == PHY_INTERFACE_MODE_RGMII_RXID)
-			data8 |= PORT_RGMII_ID_IN_ENABLE;
-		if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
-		    p->interface == PHY_INTERFACE_MODE_RGMII_TXID)
-			data8 |= PORT_RGMII_ID_OUT_ENABLE;
-		data8 |= PORT_GMII_1GPS_MODE;
-		data8 |= PORT_INTERFACE_RGMII;
-		p->phydev.speed = SPEED_1000;
-		break;
-	}
-	ksz_write8(dev, REG_PORT_5_CTRL_6, data8);
-	p->phydev.duplex = 1;
+	ksz_set_xmii(dev, port, p->interface);
 }
 
 void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port)
diff --git a/drivers/net/dsa/microchip/ksz8795_reg.h b/drivers/net/dsa/microchip/ksz8795_reg.h
index a848eb4c54cb..77487d611824 100644
--- a/drivers/net/dsa/microchip/ksz8795_reg.h
+++ b/drivers/net/dsa/microchip/ksz8795_reg.h
@@ -170,15 +170,7 @@
 #define REG_PORT_5_CTRL_6		0x56
 
 #define PORT_MII_INTERNAL_CLOCK		BIT(7)
-#define PORT_GMII_1GPS_MODE		BIT(6)
-#define PORT_RGMII_ID_IN_ENABLE		BIT(4)
-#define PORT_RGMII_ID_OUT_ENABLE	BIT(3)
 #define PORT_GMII_MAC_MODE		BIT(2)
-#define PORT_INTERFACE_TYPE		0x3
-#define PORT_INTERFACE_MII		0
-#define PORT_INTERFACE_RMII		1
-#define PORT_INTERFACE_GMII		2
-#define PORT_INTERFACE_RGMII		3
 
 #define REG_PORT_1_CTRL_7		0x17
 #define REG_PORT_2_CTRL_7		0x27
-- 
2.36.1

[RFC Patch net-next 10/10] net: dsa: microchip: add support for phylink mac config

[Arun Ramadoss]

This patch add support for phylink mac config for ksz series of
switches. All the files ksz8795, ksz9477 and lan937x uses the ksz common
xmii function. Instead of calling from the individual files, it is moved
to the ksz common phylink mac config function.

Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
---
 drivers/net/dsa/microchip/ksz8795.c      |  7 -------
 drivers/net/dsa/microchip/ksz9477.c      |  4 ----
 drivers/net/dsa/microchip/ksz_common.c   | 17 ++++++++++++++++-
 drivers/net/dsa/microchip/ksz_common.h   |  6 +++++-
 drivers/net/dsa/microchip/lan937x_main.c | 11 -----------
 5 files changed, 21 insertions(+), 24 deletions(-)

diff --git a/drivers/net/dsa/microchip/ksz8795.c b/drivers/net/dsa/microchip/ksz8795.c
index 8f807d8eace5..c79a5128235f 100644
--- a/drivers/net/dsa/microchip/ksz8795.c
+++ b/drivers/net/dsa/microchip/ksz8795.c
@@ -26,11 +26,6 @@
 #include "ksz8795_reg.h"
 #include "ksz8.h"
 
-static bool ksz_is_ksz88x3(struct ksz_device *dev)
-{
-	return dev->chip_id == 0x8830;
-}
-
 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
 {
 	regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
@@ -1124,8 +1119,6 @@ static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port)
 			 port);
 		p->interface = dev->compat_interface;
 	}
-
-	ksz_set_xmii(dev, port, p->interface);
 }
 
 void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port)
diff --git a/drivers/net/dsa/microchip/ksz9477.c b/drivers/net/dsa/microchip/ksz9477.c
index 301283d1ba82..4b14d80d27ed 100644
--- a/drivers/net/dsa/microchip/ksz9477.c
+++ b/drivers/net/dsa/microchip/ksz9477.c
@@ -944,7 +944,6 @@ void ksz9477_get_caps(struct ksz_device *dev, int port,
 
 void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
 {
-	struct ksz_port *p = &dev->ports[port];
 	struct dsa_switch *ds = dev->ds;
 	u16 data16;
 	u8 member;
@@ -987,9 +986,6 @@ void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
 		ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
 			     PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
 			     true);
-
-		/* configure MAC to 1G & RGMII mode */
-		ksz_set_xmii(dev, port, p->interface);
 	}
 
 	if (cpu_port)
diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index 43c85ff8be5f..2aee4d31af5f 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -1402,7 +1402,8 @@ static int ksz_max_mtu(struct dsa_switch *ds, int port)
 	return dev->dev_ops->max_mtu(dev, port);
 }
 
-void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface)
+static void ksz_set_xmii(struct ksz_device *dev, int port,
+			 phy_interface_t interface)
 {
 	const u8 *bitval = dev->info->bitval;
 	const u16 *regs = dev->info->regs;
@@ -1489,6 +1490,20 @@ static void ksz_phylink_mac_config(struct dsa_switch *ds, int port,
 {
 	struct ksz_device *dev = ds->priv;
 
+	if (ksz_is_ksz88x3(dev))
+		return;
+
+	/* Internal PHYs */
+	if (dev->info->internal_phy[port])
+		return;
+
+	if (phylink_autoneg_inband(mode)) {
+		dev_err(dev->dev, "In-band AN not supported!\n");
+		return;
+	}
+
+	ksz_set_xmii(dev, port, state->interface);
+
 	if (dev->dev_ops->phylink_mac_config)
 		dev->dev_ops->phylink_mac_config(dev, port, mode, state);
 }
diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
index 364e5859139d..bd057a87c7e7 100644
--- a/drivers/net/dsa/microchip/ksz_common.h
+++ b/drivers/net/dsa/microchip/ksz_common.h
@@ -314,7 +314,6 @@ void ksz_init_mib_timer(struct ksz_device *dev);
 void ksz_r_mib_stats64(struct ksz_device *dev, int port);
 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
 bool ksz_get_gbit(struct ksz_device *dev, int port);
-void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface);
 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit);
 extern const struct ksz_chip_data ksz_switch_chips[];
 
@@ -434,6 +433,11 @@ static inline void ksz_regmap_unlock(void *__mtx)
 	mutex_unlock(mtx);
 }
 
+static inline bool ksz_is_ksz88x3(struct ksz_device *dev)
+{
+	return dev->chip_id == KSZ8830_CHIP_ID;
+}
+
 static inline int is_lan937x(struct ksz_device *dev)
 {
 	return dev->chip_id == LAN9370_CHIP_ID ||
diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c
index db88ea567ba6..89f8282961a5 100644
--- a/drivers/net/dsa/microchip/lan937x_main.c
+++ b/drivers/net/dsa/microchip/lan937x_main.c
@@ -373,17 +373,6 @@ void lan937x_phylink_mac_config(struct ksz_device *dev, int port,
 	phy_interface_t interface = state->interface;
 	struct ksz_port *p = &dev->ports[port];
 
-	/* Internal PHYs */
-	if (dev->info->internal_phy[port])
-		return;
-
-	if (phylink_autoneg_inband(mode)) {
-		dev_err(dev->dev, "In-band AN not supported!\n");
-		return;
-	}
-
-	ksz_set_xmii(dev, port, state->interface);
-
 	/* if the delay is 0, do not enable DLL */
 	if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
 	    interface == PHY_INTERFACE_MODE_RGMII_RXID) {
-- 
2.36.1