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From: Ivan Vecera <ivecera@redhat.com>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: netdev@vger.kernel.org,
	Vadim Fedorenko <vadim.fedorenko@linux.dev>,
	Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
	Jiri Pirko <jiri@resnulli.us>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Prathosh Satish <Prathosh.Satish@microchip.com>,
	Lee Jones <lee@kernel.org>, Kees Cook <kees@kernel.org>,
	Andy Shevchenko <andy@kernel.org>,
	Andrew Morton <akpm@linux-foundation.org>,
	Michal Schmidt <mschmidt@redhat.com>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-hardening@vger.kernel.org
Subject: Re: [PATCH net-next v4 1/8] dt-bindings: dpll: Add DPLL device and pin
Date: Fri, 25 Apr 2025 11:36:17 +0200	[thread overview]
Message-ID: <bc28ca3e-6ccd-4d43-8a51-eb4563a6ed06@redhat.com> (raw)
In-Reply-To: <20250425-manul-of-undeniable-refinement-dc6cdc@kuoka>



On 25. 04. 25 9:39 dop., Krzysztof Kozlowski wrote:
> On Thu, Apr 24, 2025 at 05:47:15PM GMT, Ivan Vecera wrote:
>> Add a common DT schema for DPLL device and its associated pins.
>> The DPLL (device phase-locked loop) is a device used for precise clock
>> synchronization in networking and telecom hardware.
>>
>> The device includes one or more DPLLs (channels) and one or more
>> physical input/output pins.
>>
>> Each DPLL channel is used either to provide a pulse-per-clock signal or
>> to drive an Ethernet equipment clock.
>>
>> The input and output pins have the following properties:
>> * label: specifies board label
>> * connection type: specifies its usage depending on wiring
>> * list of supported or allowed frequencies: depending on how the pin
>>    is connected and where)
>> * embedded sync capability: indicates whether the pin supports this
>>
>> Check:
> 
> This does not belong to commit msg. You do not add compile commands of C
> files, do you?
> 
> Whatever you want to inform and is not relevant in the Git history
> should be in changelog part.

OK

>> $ make dt_binding_check DT_SCHEMA_FILES=/dpll/
>>    SCHEMA  Documentation/devicetree/bindings/processed-schema.json
>> /home/cera/devel/kernel/linux-2.6/Documentation/devicetree/bindings/net/snps,dwmac.yaml: mac-mode: missing type definition
>>    CHKDT   ./Documentation/devicetree/bindings
>>    LINT    ./Documentation/devicetree/bindings
>>    DTEX    Documentation/devicetree/bindings/dpll/dpll-pin.example.dts
>>    DTC [C] Documentation/devicetree/bindings/dpll/dpll-pin.example.dtb
>>    DTEX    Documentation/devicetree/bindings/dpll/dpll-device.example.dts
>>    DTC [C] Documentation/devicetree/bindings/dpll/dpll-device.example.dtb
>>
>> Signed-off-by: Ivan Vecera <ivecera@redhat.com>
>> ---
>> v3->v4:
>> * dropped $Ref from dpll-pin reg property
>> * added maxItems to dpll-pin reg property
>> * fixed paragraph in dpll-pin desc
> 
> ...
> 
>> +
>> +properties:
>> +  $nodename:
>> +    pattern: "^dpll(@.*)?$"
>> +
>> +  "#address-cells":
>> +    const: 0
>> +
>> +  "#size-cells":
>> +    const: 0
>> +
>> +  dpll-types:
>> +    description: List of DPLL channel types, one per DPLL instance.
>> +    $ref: /schemas/types.yaml#/definitions/non-unique-string-array
>> +    items:
>> +      enum: [pps, eec]
> 
> Do channels have other properties as well in general?

No, other characteristics should be deducible either from compatible or
in runtime.

>> +
>> +  input-pins:
>> +    type: object
>> +    description: DPLL input pins
>> +    unevaluatedProperties: false
> 
> Best regards,
> Krzysztof
> 


  reply	other threads:[~2025-04-25  9:36 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-24 15:47 [PATCH net-next v4 0/8] Add Microchip ZL3073x support (part 1) Ivan Vecera
2025-04-24 15:47 ` [PATCH net-next v4 1/8] dt-bindings: dpll: Add DPLL device and pin Ivan Vecera
2025-04-25  7:39   ` Krzysztof Kozlowski
2025-04-25  9:36     ` Ivan Vecera [this message]
2025-04-25  9:40       ` Krzysztof Kozlowski
2025-04-24 15:47 ` [PATCH net-next v4 2/8] dt-bindings: dpll: Add support for Microchip Azurite chip family Ivan Vecera
2025-04-25  7:41   ` Krzysztof Kozlowski
2025-04-25  9:38     ` Ivan Vecera
2025-04-24 15:47 ` [PATCH net-next v4 3/8] mfd: Add Microchip ZL3073x support Ivan Vecera
2025-04-24 16:34   ` Andrew Lunn
2025-04-24 16:49     ` Ivan Vecera
2025-04-25  3:36   ` kernel test robot
2025-04-24 15:47 ` [PATCH net-next v4 4/8] mfd: zl3073x: Add support for devlink device info Ivan Vecera
2025-04-24 15:47 ` [PATCH net-next v4 5/8] mfd: zl3073x: Add functions to work with register mailboxes Ivan Vecera
2025-04-24 16:43   ` Andrew Lunn
2025-04-24 17:10     ` Ivan Vecera
2025-04-24 19:10       ` Andrew Lunn
2025-04-24 19:26         ` Ivan Vecera
2025-04-24 19:29           ` Andrew Lunn
2025-04-24 19:58             ` Ivan Vecera
2025-04-25  6:55               ` Lee Jones
2025-04-25 10:13                 ` Ivan Vecera
2025-04-25 10:17                   ` Lee Jones
2025-04-25 10:29                     ` Ivan Vecera
2025-04-24 19:18       ` Andrew Lunn
2025-04-24 19:53         ` Ivan Vecera
2025-04-24 19:57           ` Andrew Lunn
2025-04-25 13:04             ` Ivan Vecera
2025-04-24 15:47 ` [PATCH net-next v4 6/8] mfd: zl3073x: Fetch invariants during probe Ivan Vecera
2025-04-24 15:47 ` [PATCH net-next v4 7/8] mfd: zl3073x: Add clock_id field Ivan Vecera
2025-04-24 15:47 ` [PATCH net-next v4 8/8] mfd: zl3073x: Register DPLL sub-device during init Ivan Vecera
2025-04-24 15:51 ` [PATCH net-next v4 0/8] Add Microchip ZL3073x support (part 1) Lee Jones
2025-04-24 16:29   ` Ivan Vecera

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