Re: [PATCH v23 01/22] cxl: Add type2 device basic support

[Alejandro Lucero Palau <alucerop@amd.com>]

On 2/11/26 22:11, Cheatham, Benjamin wrote:
> On 2/1/2026 9:54 AM, alejandro.lucero-palau@amd.com wrote:
>> From: Alejandro Lucero <alucerop@amd.com>
>>
>> Differentiate CXL memory expanders (type 3) from CXL device accelerators
>> (type 2) with a new function for initializing cxl_dev_state and a macro
>> for helping accel drivers to embed cxl_dev_state inside a private
>> struct.
>>
>> Move structs to include/cxl as the size of the accel driver private
>> struct embedding cxl_dev_state needs to know the size of this struct.
>>
>> Use same new initialization with the type3 pci driver.
>>
>> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
>> Reviewed-by: Alison Schofield <alison.schofield@intel.com>
>> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
>> ---
>>   drivers/cxl/core/mbox.c      |  12 +-
>>   drivers/cxl/core/memdev.c    |  32 +++++
>>   drivers/cxl/cxl.h            |  97 +--------------
>>   drivers/cxl/cxlmem.h         |  86 +------------
>>   drivers/cxl/pci.c            |  14 +--
>>   include/cxl/cxl.h            | 226 +++++++++++++++++++++++++++++++++++
>>   tools/testing/cxl/test/mem.c |   3 +-
>>   7 files changed, 274 insertions(+), 196 deletions(-)
>>   create mode 100644 include/cxl/cxl.h
>>
>> diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
>> index fa6dd0c94656..bee84d0101d1 100644
>> --- a/drivers/cxl/core/mbox.c
>> +++ b/drivers/cxl/core/mbox.c
>> @@ -1514,23 +1514,21 @@ int cxl_mailbox_init(struct cxl_mailbox *cxl_mbox, struct device *host)
>>   }
>>   EXPORT_SYMBOL_NS_GPL(cxl_mailbox_init, "CXL");
>>   
>> -struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev)
>> +struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev, u64 serial,
>> +						 u16 dvsec)
>>   {
>>   	struct cxl_memdev_state *mds;
>>   	int rc;
>>   
>> -	mds = devm_kzalloc(dev, sizeof(*mds), GFP_KERNEL);
>> +	mds = devm_cxl_dev_state_create(dev, CXL_DEVTYPE_CLASSMEM, serial,
>> +					dvsec, struct cxl_memdev_state, cxlds,
>> +					true);
>>   	if (!mds) {
>>   		dev_err(dev, "No memory available\n");
>>   		return ERR_PTR(-ENOMEM);
>>   	}
>>   
>>   	mutex_init(&mds->event.log_lock);
>> -	mds->cxlds.dev = dev;
>> -	mds->cxlds.reg_map.host = dev;
>> -	mds->cxlds.cxl_mbox.host = dev;
>> -	mds->cxlds.reg_map.resource = CXL_RESOURCE_NONE;
>> -	mds->cxlds.type = CXL_DEVTYPE_CLASSMEM;
>>   
>>   	rc = devm_cxl_register_mce_notifier(dev, &mds->mce_notifier);
>>   	if (rc == -EOPNOTSUPP)
>> diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
>> index af3d0cc65138..22d156f25305 100644
>> --- a/drivers/cxl/core/memdev.c
>> +++ b/drivers/cxl/core/memdev.c
>> @@ -656,6 +656,38 @@ static void detach_memdev(struct work_struct *work)
>>   
>>   static struct lock_class_key cxl_memdev_key;
>>   
>> +static void cxl_dev_state_init(struct cxl_dev_state *cxlds, struct device *dev,
>> +			       enum cxl_devtype type, u64 serial, u16 dvsec,
>> +			       bool has_mbox)
>> +{
>> +	*cxlds = (struct cxl_dev_state) {
>> +		.dev = dev,
>> +		.type = type,
>> +		.serial = serial,
>> +		.cxl_dvsec = dvsec,
>> +		.reg_map.host = dev,
>> +		.reg_map.resource = CXL_RESOURCE_NONE,
>> +	};
>> +
>> +	if (has_mbox)
>> +		cxlds->cxl_mbox.host = dev;
>> +}
>> +
>> +struct cxl_dev_state *_devm_cxl_dev_state_create(struct device *dev,
>> +						 enum cxl_devtype type,
>> +						 u64 serial, u16 dvsec,
>> +						 size_t size, bool has_mbox)
>> +{
>> +	struct cxl_dev_state *cxlds = devm_kzalloc(dev, size, GFP_KERNEL);
>> +
>> +	if (!cxlds)
>> +		return NULL;
>> +
>> +	cxl_dev_state_init(cxlds, dev, type, serial, dvsec, has_mbox);
> Nit: Having a second function to do the init seems overkill here, especially since cxl_dev_state_init() isn't called outside this
> function. I'd fold it into this function instead, but I'm fine with it either way (especially if you were told otherwise before).


Hi Ben,


I do not remember why this was done this way. Maybe some initial need 
which disappeared later.

I can not see a reason now, so I will do so in v24.


Thank you!


>
> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
>> +	return cxlds;
>> +}
>> +EXPORT_SYMBOL_NS_GPL(_devm_cxl_dev_state_create, "CXL");
>> +
>>   static struct cxl_memdev *cxl_memdev_alloc(struct cxl_dev_state *cxlds,
>>   					   const struct file_operations *fops,
>>   					   const struct cxl_memdev_attach *attach)
>> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
>> index e1d47062e1d3..3eaa353e430b 100644
>> --- a/drivers/cxl/cxl.h
>> +++ b/drivers/cxl/cxl.h
>> @@ -12,6 +12,7 @@
>>   #include <linux/node.h>
>>   #include <linux/io.h>
>>   #include <linux/range.h>
>> +#include <cxl/cxl.h>
>>   
>>   extern const struct nvdimm_security_ops *cxl_security_ops;
>>   
>> @@ -201,97 +202,6 @@ static inline int ways_to_eiw(unsigned int ways, u8 *eiw)
>>   #define   CXLDEV_MBOX_BG_CMD_COMMAND_VENDOR_MASK GENMASK_ULL(63, 48)
>>   #define CXLDEV_MBOX_PAYLOAD_OFFSET 0x20
>>   
>> -/*
>> - * Using struct_group() allows for per register-block-type helper routines,
>> - * without requiring block-type agnostic code to include the prefix.
>> - */
>> -struct cxl_regs {
>> -	/*
>> -	 * Common set of CXL Component register block base pointers
>> -	 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure
>> -	 * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure
>> -	 */
>> -	struct_group_tagged(cxl_component_regs, component,
>> -		void __iomem *hdm_decoder;
>> -		void __iomem *ras;
>> -	);
>> -	/*
>> -	 * Common set of CXL Device register block base pointers
>> -	 * @status: CXL 2.0 8.2.8.3 Device Status Registers
>> -	 * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers
>> -	 * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers
>> -	 */
>> -	struct_group_tagged(cxl_device_regs, device_regs,
>> -		void __iomem *status, *mbox, *memdev;
>> -	);
>> -
>> -	struct_group_tagged(cxl_pmu_regs, pmu_regs,
>> -		void __iomem *pmu;
>> -	);
>> -
>> -	/*
>> -	 * RCH downstream port specific RAS register
>> -	 * @aer: CXL 3.0 8.2.1.1 RCH Downstream Port RCRB
>> -	 */
>> -	struct_group_tagged(cxl_rch_regs, rch_regs,
>> -		void __iomem *dport_aer;
>> -	);
>> -
>> -	/*
>> -	 * RCD upstream port specific PCIe cap register
>> -	 * @pcie_cap: CXL 3.0 8.2.1.2 RCD Upstream Port RCRB
>> -	 */
>> -	struct_group_tagged(cxl_rcd_regs, rcd_regs,
>> -		void __iomem *rcd_pcie_cap;
>> -	);
>> -};
>> -
>> -struct cxl_reg_map {
>> -	bool valid;
>> -	int id;
>> -	unsigned long offset;
>> -	unsigned long size;
>> -};
>> -
>> -struct cxl_component_reg_map {
>> -	struct cxl_reg_map hdm_decoder;
>> -	struct cxl_reg_map ras;
>> -};
>> -
>> -struct cxl_device_reg_map {
>> -	struct cxl_reg_map status;
>> -	struct cxl_reg_map mbox;
>> -	struct cxl_reg_map memdev;
>> -};
>> -
>> -struct cxl_pmu_reg_map {
>> -	struct cxl_reg_map pmu;
>> -};
>> -
>> -/**
>> - * struct cxl_register_map - DVSEC harvested register block mapping parameters
>> - * @host: device for devm operations and logging
>> - * @base: virtual base of the register-block-BAR + @block_offset
>> - * @resource: physical resource base of the register block
>> - * @max_size: maximum mapping size to perform register search
>> - * @reg_type: see enum cxl_regloc_type
>> - * @component_map: cxl_reg_map for component registers
>> - * @device_map: cxl_reg_maps for device registers
>> - * @pmu_map: cxl_reg_maps for CXL Performance Monitoring Units
>> - */
>> -struct cxl_register_map {
>> -	struct device *host;
>> -	void __iomem *base;
>> -	resource_size_t resource;
>> -	resource_size_t max_size;
>> -	u8 reg_type;
>> -	union {
>> -		struct cxl_component_reg_map component_map;
>> -		struct cxl_device_reg_map device_map;
>> -		struct cxl_pmu_reg_map pmu_map;
>> -	};
>> -};
>> -
>>   void cxl_probe_component_regs(struct device *dev, void __iomem *base,
>>   			      struct cxl_component_reg_map *map);
>>   void cxl_probe_device_regs(struct device *dev, void __iomem *base,
>> @@ -497,11 +407,6 @@ struct cxl_region_params {
>>   	resource_size_t cache_size;
>>   };
>>   
>> -enum cxl_partition_mode {
>> -	CXL_PARTMODE_RAM,
>> -	CXL_PARTMODE_PMEM,
>> -};
>> -
>>   /*
>>    * Indicate whether this region has been assembled by autodetection or
>>    * userspace assembly. Prevent endpoint decoders outside of automatic
>> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
>> index ef202b34e5ea..281546de426e 100644
>> --- a/drivers/cxl/cxlmem.h
>> +++ b/drivers/cxl/cxlmem.h
>> @@ -113,8 +113,6 @@ int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled,
>>   			 resource_size_t base, resource_size_t len,
>>   			 resource_size_t skipped);
>>   
>> -#define CXL_NR_PARTITIONS_MAX 2
>> -
>>   struct cxl_dpa_info {
>>   	u64 size;
>>   	struct cxl_dpa_part_info {
>> @@ -373,87 +371,6 @@ struct cxl_security_state {
>>   	struct kernfs_node *sanitize_node;
>>   };
>>   
>> -/*
>> - * enum cxl_devtype - delineate type-2 from a generic type-3 device
>> - * @CXL_DEVTYPE_DEVMEM - Vendor specific CXL Type-2 device implementing HDM-D or
>> - *			 HDM-DB, no requirement that this device implements a
>> - *			 mailbox, or other memory-device-standard manageability
>> - *			 flows.
>> - * @CXL_DEVTYPE_CLASSMEM - Common class definition of a CXL Type-3 device with
>> - *			   HDM-H and class-mandatory memory device registers
>> - */
>> -enum cxl_devtype {
>> -	CXL_DEVTYPE_DEVMEM,
>> -	CXL_DEVTYPE_CLASSMEM,
>> -};
>> -
>> -/**
>> - * struct cxl_dpa_perf - DPA performance property entry
>> - * @dpa_range: range for DPA address
>> - * @coord: QoS performance data (i.e. latency, bandwidth)
>> - * @cdat_coord: raw QoS performance data from CDAT
>> - * @qos_class: QoS Class cookies
>> - */
>> -struct cxl_dpa_perf {
>> -	struct range dpa_range;
>> -	struct access_coordinate coord[ACCESS_COORDINATE_MAX];
>> -	struct access_coordinate cdat_coord[ACCESS_COORDINATE_MAX];
>> -	int qos_class;
>> -};
>> -
>> -/**
>> - * struct cxl_dpa_partition - DPA partition descriptor
>> - * @res: shortcut to the partition in the DPA resource tree (cxlds->dpa_res)
>> - * @perf: performance attributes of the partition from CDAT
>> - * @mode: operation mode for the DPA capacity, e.g. ram, pmem, dynamic...
>> - */
>> -struct cxl_dpa_partition {
>> -	struct resource res;
>> -	struct cxl_dpa_perf perf;
>> -	enum cxl_partition_mode mode;
>> -};
>> -
>> -/**
>> - * struct cxl_dev_state - The driver device state
>> - *
>> - * cxl_dev_state represents the CXL driver/device state.  It provides an
>> - * interface to mailbox commands as well as some cached data about the device.
>> - * Currently only memory devices are represented.
>> - *
>> - * @dev: The device associated with this CXL state
>> - * @cxlmd: The device representing the CXL.mem capabilities of @dev
>> - * @reg_map: component and ras register mapping parameters
>> - * @regs: Parsed register blocks
>> - * @cxl_dvsec: Offset to the PCIe device DVSEC
>> - * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)
>> - * @media_ready: Indicate whether the device media is usable
>> - * @dpa_res: Overall DPA resource tree for the device
>> - * @part: DPA partition array
>> - * @nr_partitions: Number of DPA partitions
>> - * @serial: PCIe Device Serial Number
>> - * @type: Generic Memory Class device or Vendor Specific Memory device
>> - * @cxl_mbox: CXL mailbox context
>> - * @cxlfs: CXL features context
>> - */
>> -struct cxl_dev_state {
>> -	struct device *dev;
>> -	struct cxl_memdev *cxlmd;
>> -	struct cxl_register_map reg_map;
>> -	struct cxl_regs regs;
>> -	int cxl_dvsec;
>> -	bool rcd;
>> -	bool media_ready;
>> -	struct resource dpa_res;
>> -	struct cxl_dpa_partition part[CXL_NR_PARTITIONS_MAX];
>> -	unsigned int nr_partitions;
>> -	u64 serial;
>> -	enum cxl_devtype type;
>> -	struct cxl_mailbox cxl_mbox;
>> -#ifdef CONFIG_CXL_FEATURES
>> -	struct cxl_features_state *cxlfs;
>> -#endif
>> -};
>> -
>>   static inline resource_size_t cxl_pmem_size(struct cxl_dev_state *cxlds)
>>   {
>>   	/*
>> @@ -858,7 +775,8 @@ int cxl_dev_state_identify(struct cxl_memdev_state *mds);
>>   int cxl_await_media_ready(struct cxl_dev_state *cxlds);
>>   int cxl_enumerate_cmds(struct cxl_memdev_state *mds);
>>   int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info);
>> -struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev);
>> +struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev, u64 serial,
>> +						 u16 dvsec);
>>   void set_exclusive_cxl_commands(struct cxl_memdev_state *mds,
>>   				unsigned long *cmds);
>>   void clear_exclusive_cxl_commands(struct cxl_memdev_state *mds,
>> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
>> index 1cf232220873..24179cc702bf 100644
>> --- a/drivers/cxl/pci.c
>> +++ b/drivers/cxl/pci.c
>> @@ -911,25 +911,25 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
>>   	int rc, pmu_count;
>>   	unsigned int i;
>>   	bool irq_avail;
>> +	u16 dvsec;
>>   
>>   	rc = pcim_enable_device(pdev);
>>   	if (rc)
>>   		return rc;
>>   	pci_set_master(pdev);
>>   
>> -	mds = cxl_memdev_state_create(&pdev->dev);
>> +	dvsec = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,
>> +					  PCI_DVSEC_CXL_DEVICE);
>> +	if (!dvsec)
>> +		pci_warn(pdev, "Device DVSEC not present, skip CXL.mem init\n");
>> +
>> +	mds = cxl_memdev_state_create(&pdev->dev, pci_get_dsn(pdev), dvsec);
>>   	if (IS_ERR(mds))
>>   		return PTR_ERR(mds);
>>   	cxlds = &mds->cxlds;
>>   	pci_set_drvdata(pdev, cxlds);
>>   
>>   	cxlds->rcd = is_cxl_restricted(pdev);
>> -	cxlds->serial = pci_get_dsn(pdev);
>> -	cxlds->cxl_dvsec = pci_find_dvsec_capability(
>> -		pdev, PCI_VENDOR_ID_CXL, PCI_DVSEC_CXL_DEVICE);
>> -	if (!cxlds->cxl_dvsec)
>> -		dev_warn(&pdev->dev,
>> -			 "Device DVSEC not present, skip CXL.mem init\n");
>>   
>>   	rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map);
>>   	if (rc)
>> diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
>> new file mode 100644
>> index 000000000000..13d448686189
>> --- /dev/null
>> +++ b/include/cxl/cxl.h
>> @@ -0,0 +1,226 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/* Copyright(c) 2020 Intel Corporation. */
>> +/* Copyright(c) 2025 Advanced Micro Devices, Inc. */
>> +
>> +#ifndef __CXL_CXL_H__
>> +#define __CXL_CXL_H__
>> +
>> +#include <linux/node.h>
>> +#include <linux/ioport.h>
>> +#include <cxl/mailbox.h>
>> +
>> +/**
>> + * enum cxl_devtype - delineate type-2 from a generic type-3 device
>> + * @CXL_DEVTYPE_DEVMEM: Vendor specific CXL Type-2 device implementing HDM-D or
>> + *			 HDM-DB, no requirement that this device implements a
>> + *			 mailbox, or other memory-device-standard manageability
>> + *			 flows.
>> + * @CXL_DEVTYPE_CLASSMEM: Common class definition of a CXL Type-3 device with
>> + *			   HDM-H and class-mandatory memory device registers
>> + */
>> +enum cxl_devtype {
>> +	CXL_DEVTYPE_DEVMEM,
>> +	CXL_DEVTYPE_CLASSMEM,
>> +};
>> +
>> +struct device;
>> +
>> +/*
>> + * Using struct_group() allows for per register-block-type helper routines,
>> + * without requiring block-type agnostic code to include the prefix.
>> + */
>> +struct cxl_regs {
>> +	/*
>> +	 * Common set of CXL Component register block base pointers
>> +	 * @hdm_decoder: CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure
>> +	 * @ras: CXL 2.0 8.2.5.9 CXL RAS Capability Structure
>> +	 */
>> +	struct_group_tagged(cxl_component_regs, component,
>> +		void __iomem *hdm_decoder;
>> +		void __iomem *ras;
>> +	);
>> +	/*
>> +	 * Common set of CXL Device register block base pointers
>> +	 * @status: CXL 2.0 8.2.8.3 Device Status Registers
>> +	 * @mbox: CXL 2.0 8.2.8.4 Mailbox Registers
>> +	 * @memdev: CXL 2.0 8.2.8.5 Memory Device Registers
>> +	 */
>> +	struct_group_tagged(cxl_device_regs, device_regs,
>> +		void __iomem *status, *mbox, *memdev;
>> +	);
>> +
>> +	struct_group_tagged(cxl_pmu_regs, pmu_regs,
>> +		void __iomem *pmu;
>> +	);
>> +
>> +	/*
>> +	 * RCH downstream port specific RAS register
>> +	 * @aer: CXL 3.0 8.2.1.1 RCH Downstream Port RCRB
>> +	 */
>> +	struct_group_tagged(cxl_rch_regs, rch_regs,
>> +		void __iomem *dport_aer;
>> +	);
>> +
>> +	/*
>> +	 * RCD upstream port specific PCIe cap register
>> +	 * @pcie_cap: CXL 3.0 8.2.1.2 RCD Upstream Port RCRB
>> +	 */
>> +	struct_group_tagged(cxl_rcd_regs, rcd_regs,
>> +		void __iomem *rcd_pcie_cap;
>> +	);
>> +};
>> +
>> +struct cxl_reg_map {
>> +	bool valid;
>> +	int id;
>> +	unsigned long offset;
>> +	unsigned long size;
>> +};
>> +
>> +struct cxl_component_reg_map {
>> +	struct cxl_reg_map hdm_decoder;
>> +	struct cxl_reg_map ras;
>> +};
>> +
>> +struct cxl_device_reg_map {
>> +	struct cxl_reg_map status;
>> +	struct cxl_reg_map mbox;
>> +	struct cxl_reg_map memdev;
>> +};
>> +
>> +struct cxl_pmu_reg_map {
>> +	struct cxl_reg_map pmu;
>> +};
>> +
>> +/**
>> + * struct cxl_register_map - DVSEC harvested register block mapping parameters
>> + * @host: device for devm operations and logging
>> + * @base: virtual base of the register-block-BAR + @block_offset
>> + * @resource: physical resource base of the register block
>> + * @max_size: maximum mapping size to perform register search
>> + * @reg_type: see enum cxl_regloc_type
>> + * @component_map: cxl_reg_map for component registers
>> + * @device_map: cxl_reg_maps for device registers
>> + * @pmu_map: cxl_reg_maps for CXL Performance Monitoring Units
>> + */
>> +struct cxl_register_map {
>> +	struct device *host;
>> +	void __iomem *base;
>> +	resource_size_t resource;
>> +	resource_size_t max_size;
>> +	u8 reg_type;
>> +	union {
>> +		struct cxl_component_reg_map component_map;
>> +		struct cxl_device_reg_map device_map;
>> +		struct cxl_pmu_reg_map pmu_map;
>> +	};
>> +};
>> +
>> +/**
>> + * struct cxl_dpa_perf - DPA performance property entry
>> + * @dpa_range: range for DPA address
>> + * @coord: QoS performance data (i.e. latency, bandwidth)
>> + * @cdat_coord: raw QoS performance data from CDAT
>> + * @qos_class: QoS Class cookies
>> + */
>> +struct cxl_dpa_perf {
>> +	struct range dpa_range;
>> +	struct access_coordinate coord[ACCESS_COORDINATE_MAX];
>> +	struct access_coordinate cdat_coord[ACCESS_COORDINATE_MAX];
>> +	int qos_class;
>> +};
>> +
>> +enum cxl_partition_mode {
>> +	CXL_PARTMODE_RAM,
>> +	CXL_PARTMODE_PMEM,
>> +};
>> +
>> +/**
>> + * struct cxl_dpa_partition - DPA partition descriptor
>> + * @res: shortcut to the partition in the DPA resource tree (cxlds->dpa_res)
>> + * @perf: performance attributes of the partition from CDAT
>> + * @mode: operation mode for the DPA capacity, e.g. ram, pmem, dynamic...
>> + */
>> +struct cxl_dpa_partition {
>> +	struct resource res;
>> +	struct cxl_dpa_perf perf;
>> +	enum cxl_partition_mode mode;
>> +};
>> +
>> +#define CXL_NR_PARTITIONS_MAX 2
>> +
>> +/**
>> + * struct cxl_dev_state - The driver device state
>> + *
>> + * cxl_dev_state represents the CXL driver/device state.  It provides an
>> + * interface to mailbox commands as well as some cached data about the device.
>> + * Currently only memory devices are represented.
>> + *
>> + * @dev: The device associated with this CXL state
>> + * @cxlmd: The device representing the CXL.mem capabilities of @dev
>> + * @reg_map: component and ras register mapping parameters
>> + * @regs: Parsed register blocks
>> + * @cxl_dvsec: Offset to the PCIe device DVSEC
>> + * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)
>> + * @media_ready: Indicate whether the device media is usable
>> + * @dpa_res: Overall DPA resource tree for the device
>> + * @part: DPA partition array
>> + * @nr_partitions: Number of DPA partitions
>> + * @serial: PCIe Device Serial Number
>> + * @type: Generic Memory Class device or Vendor Specific Memory device
>> + * @cxl_mbox: CXL mailbox context
>> + * @cxlfs: CXL features context
>> + */
>> +struct cxl_dev_state {
>> +	/* public for Type2 drivers */
>> +	struct device *dev;
>> +	struct cxl_memdev *cxlmd;
>> +
>> +	/* private for Type2 drivers */
>> +	struct cxl_register_map reg_map;
>> +	struct cxl_regs regs;
>> +	int cxl_dvsec;
>> +	bool rcd;
>> +	bool media_ready;
>> +	struct resource dpa_res;
>> +	struct cxl_dpa_partition part[CXL_NR_PARTITIONS_MAX];
>> +	unsigned int nr_partitions;
>> +	u64 serial;
>> +	enum cxl_devtype type;
>> +	struct cxl_mailbox cxl_mbox;
>> +#ifdef CONFIG_CXL_FEATURES
>> +	struct cxl_features_state *cxlfs;
>> +#endif
>> +};
>> +
>> +struct cxl_dev_state *_devm_cxl_dev_state_create(struct device *dev,
>> +						 enum cxl_devtype type,
>> +						 u64 serial, u16 dvsec,
>> +						 size_t size, bool has_mbox);
>> +
>> +/**
>> + * cxl_dev_state_create - safely create and cast a cxl dev state embedded in a
>> + * driver specific struct.
>> + *
>> + * @parent: device behind the request
>> + * @type: CXL device type
>> + * @serial: device identification
>> + * @dvsec: dvsec capability offset
>> + * @drv_struct: driver struct embedding a cxl_dev_state struct
>> + * @member: drv_struct member as cxl_dev_state
>> + * @mbox: true if mailbox supported
>> + *
>> + * Returns a pointer to the drv_struct allocated and embedding a cxl_dev_state
>> + * struct initialized.
>> + *
>> + * Introduced for Type2 driver support.
>> + */
>> +#define devm_cxl_dev_state_create(parent, type, serial, dvsec, drv_struct, member, mbox)	\
>> +	({										\
>> +		static_assert(__same_type(struct cxl_dev_state,				\
>> +			      ((drv_struct *)NULL)->member));				\
>> +		static_assert(offsetof(drv_struct, member) == 0);			\
>> +		(drv_struct *)_devm_cxl_dev_state_create(parent, type, serial, dvsec,	\
>> +						      sizeof(drv_struct), mbox);	\
>> +	})
>> +#endif /* __CXL_CXL_H__ */
>> diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c
>> index cb87e8c0e63c..79f42f4474d4 100644
>> --- a/tools/testing/cxl/test/mem.c
>> +++ b/tools/testing/cxl/test/mem.c
>> @@ -1716,7 +1716,7 @@ static int cxl_mock_mem_probe(struct platform_device *pdev)
>>   	if (rc)
>>   		return rc;
>>   
>> -	mds = cxl_memdev_state_create(dev);
>> +	mds = cxl_memdev_state_create(dev, pdev->id + 1, 0);
>>   	if (IS_ERR(mds))
>>   		return PTR_ERR(mds);
>>   
>> @@ -1732,7 +1732,6 @@ static int cxl_mock_mem_probe(struct platform_device *pdev)
>>   	mds->event.buf = (struct cxl_get_event_payload *) mdata->event_buf;
>>   	INIT_DELAYED_WORK(&mds->security.poll_dwork, cxl_mockmem_sanitize_work);
>>   
>> -	cxlds->serial = pdev->id + 1;
>>   	if (is_rcd(pdev))
>>   		cxlds->rcd = true;
>>